the following patch was just integrated into master:
commit 9e70ce0c3ec823a41abc1f44b642d1bdfb14b4cb
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Fri Dec 16 15:32:32 2016 +0100
nb/x4x: Add other Eaglelake IGD PCI DID to list
Currently only there is only one eaglelake board in coreboot
(ga-g41m-es2l) featuring a G41 variant northbridge.
Adding boards with a different variant (Q43, Q45, G43, G45, B43) will
require this change for graphic initialisation.
Change-Id: Ida32c563a99576b66685dfdadf9a534fd6e197dc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17900
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/17900 for details.
-gerrit
the following patch was just integrated into master:
commit 2fe0d75d42904b224be344b1865a2582b20ecea2
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Tue Dec 13 09:15:07 2016 -0800
google/reef: Use exported GPIOs and ACPI regulator for touchscreen
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/17799 for details.
-gerrit
the following patch was just integrated into master:
commit 60f3217ed9a91bcf96a49af83fac3dcbaf54aa88
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Mon Dec 12 09:30:42 2016 -0800
drivers/regulator: Add driver for handling GPIO-based fixed regulator
This change adds the required device node in SSDT for defining
GPIO-based fixed voltage regulator.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that ELAN touchscreen works with exported GPIOs and ACPI
regulator.
Change-Id: I4380aea0929fb7e81dbe83f940e3e51e983819f9
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17798
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/17798 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17766
-gerrit
commit 09c3ee0cd8585ea152612cb15a9f1af7885dec95
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Dec 7 10:45:55 2016 -0700
util/crossgcc: update jenkins-build-toolchain
This allows the make jenkins-build-toolchain to use the
BUILDGCC_OPTIONS variable. Previously, the options were hardcoded.
Add the -b option to BUILDGCC_OPTIONS to always use bootstrapping mode.
Change-Id: I5f4c1d3fc8c714ec3640356ae3c86ae157f486d2
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/crossgcc/Makefile.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc
index cf900ba..9b17300 100644
--- a/util/crossgcc/Makefile.inc
+++ b/util/crossgcc/Makefile.inc
@@ -72,8 +72,9 @@ else
endif # ifeq ($(COMPILER_OUT_OF_DATE),1)
# This target controls what the jenkins builder tests
+jenkins-build-toolchain: BUILDGCC_OPTIONS ?= -y --nocolor -b
jenkins-build-toolchain:
- $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='-y --nocolor'
+ $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)'
rm -f .xcompile
PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does
-cat .xcompile
the following patch was just integrated into master:
commit 690831d148edd04da14204211cb1c83cb12b1ba6
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Dec 16 08:01:09 2016 -0800
google/eve: Set throttle offset to 10 degrees
Set the thermal throttle (prochot) activation to be 10 degrees
below TJmax so PROCHOT# kicks in at 90C instead of 100C.
BUG=chrome-os-partner:58666
TEST=boot on eve, check msr value before and after resume:
> iotools rdmsr 1 0x1a2
0x000000000a6400e6
> echo mem > /sys/power/state
> iotools rdmsr 1 0x1a2
0x000000000a6400e6
Change-Id: I3ab3a050a1e27c18a940bd7519eabaf015ef93eb
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17901
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17901 for details.
-gerrit
the following patch was just integrated into master:
commit 698b3876cc1d17b2aa5e1c7d0e20794c60b801bc
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Tue Oct 11 14:19:07 2016 -0400
amd/gardenia: Enable LPC decodes
Turn on LPC decoding in romstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc)
Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17227
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17227 for details.
-gerrit
the following patch was just integrated into master:
commit ce128a7ef1c11cf6c21c137855b2b28d79bfae31
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Tue Oct 25 18:10:18 2016 -0400
amd/gardenia: Enable HD Audio
Add ALC286 commands and update the PLATFORM_CONFIGURATION structure
with the list address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee)
Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17226
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17226 for details.
-gerrit
the following patch was just integrated into master:
commit 2e0817e9fac9d3e5d4f179236ef9f00823e8df29
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Thu Oct 13 11:42:09 2016 -0400
amd/gardenia: Update PCIe and DDI lanes
Change the Carrizo settings used for Bettong to ones specific
to Stoney on Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb)
Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17225 for details.
-gerrit
the following patch was just integrated into master:
commit ec6912bb2eb39a07e81656098962e8b1bc88790e
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Thu Oct 20 14:01:32 2016 -0400
amd/gardenia: Enable SATA controller
Duplicate the code from DB-FT3lc and use the correct names.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c)
Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17224
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17224 for details.
-gerrit
the following patch was just integrated into master:
commit 081b72405a38551039dddae85c9ddf2e59ddf5e4
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Thu Oct 13 11:41:50 2016 -0400
amd/gardenia: Update xHCI configuration
Remove a duplicated check and setting for xHCI during the
AMD_INIT_RESET callout. This is handled by the wrapper. Also
remove nearby commented code. EcChannel0 is not a member of
FCH_RESET_DATA_BLOCK.
Leave the check in AMD_INIT_ENV. Although AGESA honors what
was previously requested, additional settings depend on the
state of Usb.Xhci0Enable.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd)
Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17223
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17223 for details.
-gerrit