the following patch was just integrated into master:
commit 555c9f9252c40f54ce74f7b01d8e40825dbd7bda
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Dec 7 15:01:54 2016 +0200
ti/beaglebone: Define arch for omap-header build
Required to add rules.h as default include, otherwise we get error:
./src/include/rules.h:128:5: error:
"__COREBOOT_ARM_ARCH__" is not defined [-Werror=undef]
Previously, rules.h was not included in omap-header build at all.
Change-Id: I75265916856f2f21f7966619ea65d63acd599e2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17746
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17746 for details.
-gerrit
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17746
-gerrit
commit 2e33d8a84f704970608db93033113ebd3fefb202
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Dec 7 15:01:54 2016 +0200
ti/beaglebone: Define arch for omap-header build
Required to add rules.h as default include, otherwise we get error:
./src/include/rules.h:128:5: error:
"__COREBOOT_ARM_ARCH__" is not defined [-Werror=undef]
Previously, rules.h was not included in omap-header build at all.
Change-Id: I75265916856f2f21f7966619ea65d63acd599e2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/ti/am335x/Makefile.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc
index 3bfb0fe..5b91981 100644
--- a/src/cpu/ti/am335x/Makefile.inc
+++ b/src/cpu/ti/am335x/Makefile.inc
@@ -21,6 +21,8 @@ endif
$(call add-class,omap-header)
$(eval $(call create_class_compiler,omap-header,arm))
+omap-header-generic-ccopts += -D__COREBOOT_ARM_ARCH__=7
+
real-target: $(obj)/MLO
header_ld := $(call src-to-obj,omap-header,$(dir)/header.ld)
the following patch was just integrated into master:
commit 211b1d8a87d076acd0929300a1cb8fa825f6560d
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Dec 1 07:59:16 2016 +0200
AMD binaryPI: Promote rules.h to default include
Also remove config.h, kconfig.h will pull that one in.
Change-Id: I798b3ffcf86fca19ae4b0103bb901a69db734141
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17667
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17667 for details.
-gerrit
the following patch was just integrated into master:
commit 5efddd7537ee921ade4969b764245fbf87d87372
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Dec 7 14:32:18 2016 +0200
intel/fsp_rangeley: Fix use of __SIMPLE_DEVICE__
Required fix to have rules.h as default include.
Change-Id: I6ce2d4e13de5139a84c709b5836ecd41c0abc836
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17747
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/17747 for details.
-gerrit
the following patch was just integrated into master:
commit c86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Dec 9 17:43:27 2016 +0200
intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.
As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.
There are no reasons to have this as board-specific setting.
Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17806 for details.
-gerrit
the following patch was just integrated into master:
commit c3e0389c058ea097e80d6d95434b56b6edff8389
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Dec 11 15:54:11 2016 +0200
intel/i82801ix: Add HAVE_INTEL_FIRMWARE
Select this to provide menu in menuconfig to add flash
descriptor file. ME or GbE firmwares themselves are not
required, but integrated NIC MAC and SPI configuration
fields are still useful.
Change-Id: I14b86e2f38ec39924d2cbf0932d82f66ed356a03
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17805
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/17805 for details.
-gerrit
the following patch was just integrated into master:
commit 7f0e458720804d91bd8718a1374ace3303cb2090
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Dec 13 10:32:43 2016 +0200
emulation/qemu-q35: Increase default ROM_SIZE
Larger size fits GRUB payload and fixes case to
build 82801ix with HAVE_INTEL_FIRMWARE.
Change-Id: I90e33fb3a0b0e1a60dcc2a9a022bef034f3270d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17830
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17830 for details.
-gerrit
the following patch was just integrated into master:
commit 82e41d813074da4cebfd6d2de7e9f47ecb62a3cf
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Dec 11 13:31:17 2016 +0200
ACPI S3: Signal successful boot
Just before jumping to OS wakeup vector do the same
tasks to signal coreboot completion that would be done
before entry to payload on normal boot path.
Change-Id: I7514c498f40f2d93a4e83a232ef4665f5c21f062
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17794
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/17794 for details.
-gerrit