coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

1 participants
1140 discussions

Patch set updated for coreboot: riscv: enable counters via m[us]counteren
by Ronald G. Minnich 19 Dec '16

19 Dec '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17920 -gerrit commit 7ca40cf2b6adccc97a6740f879deb0af7b5f0b8f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 19 09:06:00 2016 -0800 riscv: enable counters via m[us]counteren The user and supervisor counters could not be safely enabled before as the register numbers were not finalized. Now that everyone agrees, we can enable them. Until we are sure the toolchains are caught up, we use the hardcode name with the register names in comments. As soon as toolchains settle down we'll do one more pass and convert to the symbolic names. Tested on lowrisc bitstream and SPIKE simulator. Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/virtual_memory.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index aceb72e..2c440d2 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -310,14 +310,12 @@ void mstatus_init(void) set_csr(medeleg, delegate); - /* Enable all user/supervisor-mode counters */ - /* We'll turn these on once lowrisc gets their bitstream up to - * 1.9. Right now there's no agreement on the values for these - * architectural registers. - */ - // write_csr(mscounteren, 0b111); - // write_csr(mucounteren, 0b111); - - // for SPIKE: - // write_csr(/*mscounteren*/0x321, 0b111); + // Enable all user/supervisor-mode counters using + // v1.9.1 register addresses. + // They moved from the earlier spec. + // Until we trust our toolchain use the hardcoded constants. + // These were in flux and people who get the older toolchain + // will have difficult-to-debug failures. + write_csr(/*mucounteren*/0x320, 7); + write_csr(/*mscounteren*/0x321, 7); }

1 0

Patch set updated for coreboot: riscv: enable counters via m[us]counteren
by Ronald G. Minnich 19 Dec '16

19 Dec '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17920 -gerrit commit 83136bd64bc95df8e11e5e8e06e3224f2c42a797 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 19 09:06:00 2016 -0800 riscv: enable counters via m[us]counteren The user and supervisor counters could not be safely enabled before as the register numbers were not finalized. Now that everyone agrees, we can enable them. Until we are sure the toolchains are caught up, we use the hardcode name with the register names in comments. As soon as toolchains settle down we'll do one more pass and convert to the symbolic names. Tested on lowrisc bitstream and SPIKE simulator. Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/virtual_memory.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index aceb72e..b9801dd 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -310,14 +310,11 @@ void mstatus_init(void) set_csr(medeleg, delegate); - /* Enable all user/supervisor-mode counters */ - /* We'll turn these on once lowrisc gets their bitstream up to - * 1.9. Right now there's no agreement on the values for these - * architectural registers. - */ - // write_csr(mscounteren, 0b111); - // write_csr(mucounteren, 0b111); - - // for SPIKE: - // write_csr(/*mscounteren*/0x321, 0b111); + // Enable all user/supervisor-mode counters. + // for v1.9 + // Until we trust our toolchain use the hardcoded constants. + // These were in flux and people who get the older toolchain + // will have difficult-to-debug failures. + write_csr(/*mucounteren*/0x320, 7); + write_csr(/*mscounteren*/0x321, 7); }

1 0

New patch to review for coreboot: riscv: enable counters via m[us]counteren
by Ronald G. Minnich 19 Dec '16

19 Dec '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17920 -gerrit commit e6e7abd7996c9136d4df1c5cdbcaaf5a43fc9a1a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 19 09:06:00 2016 -0800 riscv: enable counters via m[us]counteren The user and supervisor counters coult not be safely enabled before as the register numbers were not finalized. Now that everyone agrees, we can enable them. Until we are sure the toolchains are caught up, we use the hardcode name with the register names in comments. As soon as toolchains settle down we'll do one more pass and convert to the symbolic names. Tested on lowrisc bitstream and SPIKE simulator. Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/virtual_memory.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index aceb72e..b9801dd 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -310,14 +310,11 @@ void mstatus_init(void) set_csr(medeleg, delegate); - /* Enable all user/supervisor-mode counters */ - /* We'll turn these on once lowrisc gets their bitstream up to - * 1.9. Right now there's no agreement on the values for these - * architectural registers. - */ - // write_csr(mscounteren, 0b111); - // write_csr(mucounteren, 0b111); - - // for SPIKE: - // write_csr(/*mscounteren*/0x321, 0b111); + // Enable all user/supervisor-mode counters. + // for v1.9 + // Until we trust our toolchain use the hardcoded constants. + // These were in flux and people who get the older toolchain + // will have difficult-to-debug failures. + write_csr(/*mucounteren*/0x320, 7); + write_csr(/*mscounteren*/0x321, 7); }

1 0

Patch merged into coreboot/master: google/poppy: Add new board
by gerrit＠coreboot.org 19 Dec '16

19 Dec '16

the following patch was just integrated into master: commit 06cd903566b57af4698089de4a67dd49bf7e56ed Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 14 12:10:21 2016 -0800 google/poppy: Add new board Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17866 for details. -gerrit

1 0

Patch merged into coreboot/master: amd/mainboard: Clean up bettong, gardenia USB todos
by gerrit＠coreboot.org 19 Dec '16

19 Dec '16

the following patch was just integrated into master: commit 2911b5e509c273add2aee005d4bebff95e0e1116 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Dec 16 12:44:13 2016 -0500 amd/mainboard: Clean up bettong, gardenia USB todos An incorrect board name was propagated over various generations of mainboards. Correct the comments for these. Addressing the todo items will come in a later patch. Change-Id: I4abd028fee5087955a7b6ba8d38f99c8207d24b4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/17903 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> See https://review.coreboot.org/17903 for details. -gerrit

1 0

Patch merged into coreboot/master: motherboard/amd: Clean up bettong, gardenia makefiles
by gerrit＠coreboot.org 19 Dec '16

19 Dec '16

the following patch was just integrated into master: commit 6e404823068e6cacaff7319e426298ba045b03d5 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Dec 16 12:01:24 2016 -0500 motherboard/amd: Clean up bettong, gardenia makefiles Declutter the conditional building of fchec.c. Use the CONFIG setting directly instead of ifeq (). Change-Id: I6d3721764e66e5615a639c1979d60ff1291b5d33 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/17902 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> See https://review.coreboot.org/17902 for details. -gerrit

1 0

Patch merged into coreboot/master: amd/gardenia: Update ACPI routing
by gerrit＠coreboot.org 19 Dec '16

19 Dec '16

the following patch was just integrated into master: commit 28cc06fe0e04cd63021ab396e6476ced947a3627 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Oct 16 16:14:57 2016 -0400 amd/gardenia: Update ACPI routing Reduce the Bettong devices and match up the comments to the northbridge. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from e7c38571be6406453640d671210b2074a91f162e) Change-Id: I53adff741f5cf2bd75c37421949bd30f214f5692 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/17849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17849 for details. -gerrit

1 0

Patch merged into coreboot/master: drivers/intel/gma: Use scaling to simplify fb config
by gerrit＠coreboot.org 19 Dec '16

19 Dec '16

the following patch was just integrated into master: commit a4facf80f2df7ebd51d512c4091ab8df24bb71c9 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Nov 8 12:29:50 2016 +0100 drivers/intel/gma: Use scaling to simplify fb config Utilize libgfxinit's support for scaling to simplify the framebuffer configuration. In case of multiple displays of different resolutions, we had configured one framebuffer big enough for their union, each display only showing its respective upper left window. Instead, we use the smallest resolution now and show the whole image on all displays. Change-Id: I70a9d92f88ef891703829945264f94ac7eff09b0 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17492 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17492 for details. -gerrit

1 0

Patch set updated for coreboot: drivers/intel/gma: Use scaling to simplify fb config
by Nico Huber 19 Dec '16

19 Dec '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17492 -gerrit commit 804ba5c3ee4106cb163caa0cd2430437bfa56a12 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Nov 8 12:29:50 2016 +0100 drivers/intel/gma: Use scaling to simplify fb config Utilize libgfxinit's support for scaling to simplify the framebuffer configuration. In case of multiple displays of different resolutions, we had configured one framebuffer big enough for their union, each display only showing its respective upper left window. Instead, we use the smallest resolution now and show the whole image on all displays. Change-Id: I70a9d92f88ef891703829945264f94ac7eff09b0 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/drivers/intel/gma/hires_fb/gma.adb | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/gma/hires_fb/gma.adb b/src/drivers/intel/gma/hires_fb/gma.adb index 7ebc4f8..87e0900 100644 --- a/src/drivers/intel/gma/hires_fb/gma.adb +++ b/src/drivers/intel/gma/hires_fb/gma.adb @@ -59,9 +59,8 @@ is success : boolean; - stride : Width_Type; - max_h : pos16 := 1; - max_v : pos16 := 1; + min_h : pos16 := pos16'last; + min_v : pos16 := pos16'last; begin lightup_ok := 0; @@ -77,30 +76,24 @@ is for i in Config_Index loop exit when configs (i).Port = Disabled; - max_h := pos16'max (max_h, configs (i).Mode.H_Visible); - max_v := pos16'max (max_v, configs (i).Mode.V_Visible); + min_h := pos16'min (min_h, configs (i).Mode.H_Visible); + min_v := pos16'min (min_v, configs (i).Mode.V_Visible); end loop; - stride := ((Width_Type (max_h) + 63) / 64) * 64; + fb := + (Width => Width_Type (min_h), + Height => Height_Type (min_v), + BPC => 8, + Stride => ((Width_Type (min_h) + 63) / 64) * 64, + Offset => 0); for i in Config_Index loop exit when configs (i).Port = Disabled; - configs (i).Framebuffer := - (Width => Width_Type (configs (i).Mode.H_Visible), - Height => Height_Type (configs (i).Mode.V_Visible), - BPC => 8, - Stride => stride, - Offset => 0); + configs (i).Framebuffer := fb; end loop; HW.GFX.GMA.Dump_Configs (configs); - fb := - (Width => Width_Type (max_h), - Height => Height_Type (max_v), - BPC => 8, - Stride => stride, - Offset => 0); HW.GFX.GMA.Setup_Default_GTT (fb, phys_fb); HW.GFX.Framebuffer_Filler.Fill (linear_fb, fb);

1 0

Patch merged into coreboot/master: drivers/intel/gma: Add textmode support with libgfxinit
by gerrit＠coreboot.org 19 Dec '16

19 Dec '16

the following patch was just integrated into master: commit 66203df660ad2230389597a942f5252074a33aac Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Nov 7 17:24:47 2016 +0100 drivers/intel/gma: Add textmode support with libgfxinit Add an alternative gfxinit implementation for textmode. The legacy VGA plane and textmode is configured through coreboot provided functions. libgfxinit uses this plane as alternative to the usual high resolution plane. Change-Id: Iad0754c50fc6faec35f49583fe1c7cb50ac6c0c5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17279 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/17279 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2016