coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: google/eve: Fix configuration of some GPIOs
by gerrit＠coreboot.org 20 Dec '16

20 Dec '16

the following patch was just integrated into master: commit a4464140f9467f76f1ee515b90451d4723b51ca1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 19 19:50:10 2016 -0800 google/eve: Fix configuration of some GPIOs GPP_D12 needs an internal pull-up to get this rail working on current boards. GPP_D0-GPP_D3 were changed from SPI interface and I just missed this change earlier. BUG=chrome-os-partner:58666 TEST=test camera and touchpad on eve Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17922 for details. -gerrit

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Patch set updated for coreboot: google/eve: Fix configuration of some GPIOs
by Duncan Laurie 20 Dec '16

20 Dec '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17922 -gerrit commit 8a15ed5df42a60501b4a5c10e53d26a08c68de86 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 19 19:50:10 2016 -0800 google/eve: Fix configuration of some GPIOs GPP_D12 needs an internal pull-up to get this rail working on current boards. GPP_D0-GPP_D3 were changed from SPI interface and I just missed this change earlier. BUG=chrome-os-partner:58666 TEST=test camera and touchpad on eve Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 34ae3a4..10642e9 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -120,10 +120,10 @@ static const struct pad_config gpio_table[] = { /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ /* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ +/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ +/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */ +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), @@ -132,7 +132,7 @@ static const struct pad_config gpio_table[] = { /* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ /* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ -/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */ /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),

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Patch set updated for coreboot: google/eve: Fix configuration of some GPIOs
by Duncan Laurie 20 Dec '16

20 Dec '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17922 -gerrit commit ac6336d2aba5d7541ee5f8e67f815017b3075746 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 19 19:50:10 2016 -0800 google/eve: Fix configuration of some GPIOs GPP_D12 needs an internal pull-up to get this rail working on current boards. GPP_D0-GPP_D3 were changed from SPI interface and I just missed this change earlier. BUG=chrome-os-partner:58666 TEST=test camera and touchpad on eve Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 34ae3a4..8311c5b 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -120,10 +120,10 @@ static const struct pad_config gpio_table[] = { /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ /* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ +/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ +/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1), /* TOUCHPAD_RESET */ +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), @@ -132,7 +132,7 @@ static const struct pad_config gpio_table[] = { /* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ /* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ -/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */ /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),

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New patch to review for filo: linux_load: set init_size boot parameter
by Mathias Krause 20 Dec '16

20 Dec '16

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17927 -gerrit commit c7670c29fc6ca0ca7c838f2ced4cc936cfb9821d Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Tue Dec 20 10:28:26 2016 +0100 linux_load: set init_size boot parameter Recent Linux kernels (v4.7+) require the boot loader to copy over the init_size boot parameter, too. We also miss to copy the loadflags. Fix that to comply to the boot protocol v2.10+. This fixes booting kernels v4.7 and later. Change-Id: Ie68d44caedc481c368c63420376caedbdb9a93b5 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- x86/linux_load.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/x86/linux_load.c b/x86/linux_load.c index 7bb37dd..acbb830 100644 --- a/x86/linux_load.c +++ b/x86/linux_load.c @@ -182,7 +182,10 @@ struct linux_params { u32 initrd_addr_max; /* 0x22c */ u32 kernel_alignment; /* 0x230 */ u8 relocatable_kernel; /* 0x234 */ - u8 reserved13[155]; /* 0x22c */ + u8 min_alignment; /* 0x235 */ + u8 reserved13[42]; /* 0x236 */ + u32 init_size; /* 0x260 */ + u8 reserved14[108]; /* 0x264 */ struct e820entry e820_map[E820MAX]; /* 0x2d0 */ u8 reserved16[688]; /* 0x550 */ #define COMMAND_LINE_SIZE 256 @@ -282,6 +285,7 @@ init_linux_params(struct linux_params *params, struct linux_header *hdr) /* Copy some useful values from header */ params->mount_root_rdonly = hdr->root_flags; params->orig_root_dev = hdr->root_dev; + params->loader_flags = hdr->loadflags; /* Video parameters. * This assumes we have VGA in standard 80x25 text mode, @@ -812,6 +816,14 @@ int linux_load(const char *file, const char *cmdline) free(initrd_file); } + /* set init_size */ + if (hdr.protocol_version < 0x020a) { + /* conservative size assumption */ + params->init_size = 3 * kern_size; + } else { + params->init_size = hdr.init_size; + } + file_close(); #if IS_ENABLED(CONFIG_LP_USB) usb_exit();

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New patch to review for coreboot: amd: hudson: Fix position of hudson_fwm
by Ricardo Ribalda Delgado 20 Dec '16

20 Dec '16

Ricardo Ribalda Delgado just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17925 -gerrit commit 884d20521372af8038a418bdcd824375d5a2d1e4 Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Tue Dec 20 10:51:08 2016 +0100 amd: hudson: Fix position of hudson_fwm AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. On this patch we force the position of HUDSON_FWM_POSITION to the position calculated by amdfwrom. Change-Id: Id2ee96ee076293d48ade84fd6e976ca994dcf491 --- src/southbridge/amd/agesa/hudson/Kconfig | 23 ----------------------- src/southbridge/amd/agesa/hudson/Makefile.inc | 3 +-- src/southbridge/amd/pi/hudson/Kconfig | 23 ----------------------- src/southbridge/amd/pi/hudson/Makefile.inc | 3 +-- 4 files changed, 2 insertions(+), 50 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index eed83ae..91ebe03 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -101,29 +101,6 @@ config HUDSON_FWM default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM default n -if HUDSON_FWM - -config HUDSON_FWM_POSITION - hex "Hudson Firmware ROM Position" - default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 - default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 - default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 - default 0xFF820000 if BOARD_ROMSIZE_KB_8192 - default 0xFF020000 if BOARD_ROMSIZE_KB_16384 - help - Hudson requires the firmware MUST be located at - a specific address (ROM start address + 0x20000), otherwise - xhci host Controller can not find or load the xhci firmware. - - The firmware start address is dependent on the ROM chip size. - The default offset is 0x20000 from the ROM start address, namely - 0xFFF20000 if flash chip size is 1M - 0xFFE20000 if flash chip size is 2M - 0xFFC20000 if flash chip size is 4M - 0xFF820000 if flash chip size is 8M - 0xFF020000 if flash chip size is 16M -endif # HUDSON_FWM - config HUDSON_SATA_MODE int "SATA Mode" default 0 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 2e8b13b..7595889 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -35,8 +35,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # +-----------+---------------+----------------+------------+ # EC ROM should be 64K aligned. -HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-multiply, $(CONFIG_COREBOOT_ROMSIZE_KB) 1024)) 0x20000 1) -HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index afa03aa..f6e3355 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -103,29 +103,6 @@ config HUDSON_FWM default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM || HUDSON_PSP default n -if HUDSON_FWM - -config HUDSON_FWM_POSITION - hex "Hudson Firmware ROM Position" - default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 - default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 - default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 - default 0xFF820000 if BOARD_ROMSIZE_KB_8192 - default 0xFF020000 if BOARD_ROMSIZE_KB_16384 - help - Hudson requires the firmware MUST be located at - a specific address (ROM start address + 0x20000), otherwise - xhci host Controller can not find or load the xhci firmware. - - The firmware start address is dependent on the ROM chip size. - The default offset is 0x20000 from the ROM start address, namely - 0xFFF20000 if flash chip size is 1M - 0xFFE20000 if flash chip size is 2M - 0xFFC20000 if flash chip size is 4M - 0xFF820000 if flash chip size is 8M - 0xFF020000 if flash chip size is 16M -endif # HUDSON_FWM - config AMD_PUBKEY_FILE depends on HUDSON_PSP string "AMD public Key" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 292da76..24a757c 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -67,8 +67,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # # EC ROM should be 64K aligned. -HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-multiply, $(CONFIG_COREBOOT_ROMSIZE_KB) 1024)) 0x20000 1) -HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) ## ifeq ($(CONFIG_HUDSON_PSP), y)

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New patch to review for coreboot: agesawrapper: Fix endless loop on bettong
by Ricardo Ribalda Delgado 20 Dec '16

20 Dec '16

Ricardo Ribalda Delgado just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17924 -gerrit commit 75e9650bce71630821c40e8bce0de23c7fcc90b2 Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Tue Dec 20 10:08:45 2016 +0100 agesawrapper: Fix endless loop on bettong AGESA AmdInitEarly() reconfigures the lapic timer in a way that conflicts with lapic/apic_timer. This results in an endless loop when printk() is called after AmdInitEarly() and before the apic_timer is initialized. This patches forces a reconfiguration of the timer after AmdInitEarly() is called. Codepath of the endless loop: printk()-> (...)-> uart_tx_byte-> uart8250_mem_tx_byte-> udelay()-> start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while ((start - value) < ticks); [lapic_read returns the same value after AmdInitEarly()] Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- src/northbridge/amd/pi/agesawrapper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 8e16e75..420a694 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -15,6 +15,7 @@ #include <AGESA.h> #include <cbfs.h> +#include <delay.h> #include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> @@ -107,6 +108,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled; status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + init_timer(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct);

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New patch to review for coreboot: SPD_CACHE: Drop debug statement
by Kyösti Mälkki 20 Dec '16

20 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17923 -gerrit commit 4f35fa719c0bf7ed4daeb202ba98b9ef7016e2b2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 27 04:58:02 2016 +0200 SPD_CACHE: Drop debug statement Output from CBFS functions is enough. Change-Id: I94d4a20a24f88eeacbe4aeb2e03a15974d18b16c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/dram/spd_cache.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index b0344ec..c7dd97d 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -31,7 +31,6 @@ int read_spd_from_cbfs(u8 *buf, int idx) size_t spd_file_len = 0; size_t min_len = (idx + 1) * SPD_SIZE; - printk(BIOS_DEBUG, "read SPD\n"); spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); if (!spd_file)

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Patch set updated for coreboot: mb/asus/p5gc-mx: Add mainboard
by Arthur Heymans 20 Dec '16

20 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17558 -gerrit commit b0f5424ec0be5e4ead27147164f6944aed21c4e2 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Nov 21 17:11:48 2016 +0100 mb/asus/p5gc-mx: Add mainboard Tested to work: * GPU (Nvidia gt210) in PCIe x16 slot; * SATA; * serial; * 800MHz and 1067MHz FSB Core 2 Duo CPUs; * ethernet; * native VGA graphic init. What does not work: * resume from s3 suspend; * superio hardware monitor (not initialised in coreboot). Quirks: * does not boot with just one dimm in slot B. Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/Kconfig | 57 +++++ src/mainboard/asus/p5gc-mx/Kconfig.name | 2 + src/mainboard/asus/p5gc-mx/Makefile.inc | 1 + src/mainboard/asus/p5gc-mx/acpi/ec.asl | 51 ++++ src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl | 75 ++++++ src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl | 46 ++++ src/mainboard/asus/p5gc-mx/acpi/mainboard.asl | 30 +++ src/mainboard/asus/p5gc-mx/acpi/platform.asl | 48 ++++ src/mainboard/asus/p5gc-mx/acpi/superio.asl | 1 + src/mainboard/asus/p5gc-mx/acpi/thermal.asl | 1 + src/mainboard/asus/p5gc-mx/acpi_tables.c | 22 ++ src/mainboard/asus/p5gc-mx/board_info.txt | 6 + src/mainboard/asus/p5gc-mx/cmos.default | 7 + src/mainboard/asus/p5gc-mx/cmos.layout | 97 ++++++++ src/mainboard/asus/p5gc-mx/cstates.c | 20 ++ src/mainboard/asus/p5gc-mx/devicetree.cb | 124 ++++++++++ src/mainboard/asus/p5gc-mx/dsdt.asl | 53 +++++ src/mainboard/asus/p5gc-mx/hda_verb.c | 40 ++++ src/mainboard/asus/p5gc-mx/romstage.c | 275 ++++++++++++++++++++++ 19 files changed, 956 insertions(+) diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig new file mode 100644 index 0000000..0a32ac4 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans <arthur(a)ahemans.xyz +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if BOARD_ASUS_P5GC_MX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627DHG + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_EDID + +config MAINBOARD_DIR + string + default asus/p5gc-mx + +config MAINBOARD_PART_NUMBER + string + default "P5GC-MX" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 2 + +endif # BOARD_ASUS_P5GC_MX diff --git a/src/mainboard/asus/p5gc-mx/Kconfig.name b/src/mainboard/asus/p5gc-mx/Kconfig.name new file mode 100644 index 0000000..a325f58 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5GC_MX + bool "P5GC-MX" diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/asus/p5gc-mx/acpi/ec.asl b/src/mainboard/asus/p5gc-mx/acpi/ec.asl new file mode 100644 index 0000000..5362bb2 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/ec.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + // _REG method requires that an operation region be defined. + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..4aaa33f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 17 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 19 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 17 }, + Package() { 0x001fffff, 2, 0, 18 }, + Package() { 0x001fffff, 3, 0, 19 }, + + }) + + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..84d2a2f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, + + }) +} Else { + Return (Package() { + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + }) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl new file mode 100644 index 0000000..0454c3f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/platform.asl b/src/mainboard/asus/p5gc-mx/acpi/platform.asl new file mode 100644 index 0000000..21eb3df --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/platform.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/superio.asl b/src/mainboard/asus/p5gc-mx/acpi/superio.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/acpi/thermal.asl b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c new file mode 100644 index 0000000..ca4cde6 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/asus/p5gc-mx/board_info.txt b/src/mainboard/asus/p5gc-mx/board_info.txt new file mode 100644 index 0000000..c661268 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5GCMX/ +Release year: 2007 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default new file mode 100644 index 0000000..ab7aac1 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout new file mode 100644 index 0000000..eaf51bb --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -0,0 +1,97 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# RAM initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c new file mode 100644 index 0000000..f683756 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cstates.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <arch/x86/include/arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb new file mode 100644 index 0000000..d04b42a --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x + device lapic 0xACAC off end + end + end + + device domain 0 on + device pci 00.0 on # host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 on # i945 PCIe root port + subsystemid 0x1458 0x5000 + ioapic_irq 2 INTA 0x10 + end + device pci 02.0 on # vga controller + subsystemid 0x1458 0xd000 + ioapic_irq 2 INTA 0x10 + end + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x86" + register "pirqd_routing" = "0x85" + register "pirqe_routing" = "0x83" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x85" + + register "gpe0_en" = "0" + + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + register "p_cnt_throttling_supported" = "0" + + device pci 1b.0 on # High Definition Audio + ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + #device pci 1c.2 off end # PCIe port 3 + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on # USB UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # USB UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # USB UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1d.3 on # USB UHCI + ioapic_irq 2 INTD 0x13 + end + device pci 1d.7 on # USB2 EHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on end # PCI bridge + + device pci 1f.0 on # LPC bridge + ioapic_irq 2 INTA 0x10 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + irq 0x74 = 2 + irq 0xf0 = 0x3a + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0xf0 = 0x83 + end + end + device pci 1f.1 on # IDE + ioapic_irq 2 INTB 0x11 + end + device pci 1f.2 on # SATA + ioapic_irq 2 INTC 0x12 + end + device pci 1f.3 on # SMBus + ioapic_irq 2 INTD 0x13 + end + end + end +end diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl new file mode 100644 index 0000000..187481a --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + //#include "acpi/thermal.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c new file mode 100644 index 0000000..a9c25f3 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0883, /* Vendor ID */ + 0x104382c7, /* Subsystem ID */ + 0x0000000c, /* Number of entries */ + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), + AZALIA_PIN_CFG(0, 0x1e, 0x18561130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c new file mode 100644 index 0000000..bcb7148 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz + * Copyright (C) 2016 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <halt.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> +#include <arch/cpu.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) + +void setup_ich7_gpios(void) +{ + /* TODO: This is highly board specific and should be moved */ + printk(BIOS_DEBUG, " GPIOS..."); + /* General Registers */ + outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +/* + * BSEL0 is connected with GPIO32 + * BSEL1 is connected with GPIO33 with inversed logic + * BSEL2 is connected with GPIO55 + */ +static void setup_sio_gpio(u8 bsel) +{ + int need_reset = 0; + u8 reg, old_reg; + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + reg = 0x9a; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + + pnp_write_config(GPIO_DEV, 0x30, 0x0e); + pnp_write_config(GPIO_DEV, 0xe0, 0xde); + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); + pnp_write_config(GPIO_DEV, 0xf4, 0x80); + pnp_write_config(GPIO_DEV, 0xf5, 0x80); + + /* Invert GPIO33 */ + pnp_write_config(GPIO_DEV, 0xf2, 0x08); + + reg = (bsel & 3) << 2; + old_reg = pnp_read_config(GPIO_DEV, 0xf1); + pnp_write_config(GPIO_DEV, 0xf1, reg); + need_reset += ((reg & 0xc) != (old_reg & 0xc)); + + reg = (bsel >> 2) << 5; + old_reg = pnp_read_config(GPIO_DEV, 0xe1); + pnp_write_config(GPIO_DEV, 0xe1, reg); + need_reset += ((reg & 0x20) != (old_reg & 0x20)); + + pnp_exit_ext_func_mode(GPIO_DEV); + + if (need_reset) { + int i = 1000; + while (i--) + outb(i & 0xff, 0x80); + outb(0xe, 0xcf9); + halt(); + } +} + +static u8 msr_get_fsb(void) +{ + u8 fsbcfg; + msr_t msr; + const u32 eax = cpuid_eax(1); + + /* Netburst */ + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(0x2c); + fsbcfg = (msr.lo >> 16) & 0x7; + } else { /* Intel Core 2 */ + msr = rdmsr(MSR_FSB_FREQ); + fsbcfg = msr.lo & 0x7; + } + + return fsbcfg; +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + // Enable COM1 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d); + // Enable SuperIO Power Management Events + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801); + + /* range 0x15e0 - 0x10ef */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291); + + +} + +static void rcba_config(void) +{ + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Disable unused devices */ + RCBA32(0x3418) = 0x003c0061; + + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030509; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void mainboard_romstage_entry(unsigned long bist) +{ + int s3resume = 0, boot_mode = 0; + + u8 m_bsel; + u8 c_bsel = msr_get_fsb(); + + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + setup_sio_gpio(c_bsel); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected.\n"); + boot_mode = 1; + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + m_bsel = MCHBAR32(CLKCFG) & 7; + printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel); + if (c_bsel != m_bsel) { /* Should not happen */ + printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n"); + outb(0xe, 0xcf9); + halt(); + } + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(s3resume ? 2 : boot_mode, NULL); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +}

1 0

New patch to review for coreboot: google/eve: Fix configuration of some GPIOs
by Duncan Laurie 20 Dec '16

20 Dec '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17922 -gerrit commit 97a18f422735344f87bed441ec07293a0a45a4f0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 19 19:50:10 2016 -0800 google/eve: Fix configuration of some GPIOs GPP_D12 needs an internal pull-up to get this rail working on current boards. GPP_D0-GPP_D3 were changed from SPI interface and I just missed this change earlier. BUG=chrome-os-partner:58666 TEST=test camera and touchpad on eve Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 34ae3a4..ddf2652 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -120,10 +120,10 @@ static const struct pad_config gpio_table[] = { /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ /* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ +/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ +/* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* TOUCHPAD_RESET */ +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), @@ -132,7 +132,7 @@ static const struct pad_config gpio_table[] = { /* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ /* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ -/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */ /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),

1 0

Patch set updated for coreboot: Combine Broadwell Chromeboxes using variant board scheme
by Matt DeVillier 20 Dec '16

20 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17913 -gerrit commit 93575e3e3f6f2420bd370265a95ef76c48e6579b Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Sat Dec 17 17:13:23 2016 -0600 Combine Broadwell Chromeboxes using variant board scheme Combine existing boards google/guado, rikku, and tidus using their common reference board google/jecht as a base. Additional changes besides simple consolidation include: - simplify power LED functions - simplify HDA verb definitions using azelia macros - use common SoC functions to generate FADT table - correct FADT table header version - remove unused haswell_pci_irqs.asl - remove unused header includes (various) - set sane default fan speed (0x4d) for all variants Variant setup modeled after google/beltino Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/guado/Kconfig | 59 --- src/mainboard/google/guado/Kconfig.name | 2 - src/mainboard/google/guado/Makefile.inc | 24 -- src/mainboard/google/guado/acpi/ec.asl | 0 .../google/guado/acpi/haswell_pci_irqs.asl | 82 ---- src/mainboard/google/guado/acpi/mainboard.asl | 69 ---- src/mainboard/google/guado/acpi/platform.asl | 71 ---- src/mainboard/google/guado/acpi/superio.asl | 31 -- src/mainboard/google/guado/acpi/thermal.asl | 339 ---------------- src/mainboard/google/guado/acpi/video.asl | 38 -- src/mainboard/google/guado/acpi_tables.c | 65 --- src/mainboard/google/guado/board_info.txt | 7 - src/mainboard/google/guado/chromeos.c | 105 ----- src/mainboard/google/guado/chromeos.fmd | 38 -- src/mainboard/google/guado/cmos.layout | 132 ------ src/mainboard/google/guado/devicetree.cb | 119 ------ src/mainboard/google/guado/dsdt.asl | 56 --- src/mainboard/google/guado/fadt.c | 154 ------- src/mainboard/google/guado/gpio.h | 120 ------ src/mainboard/google/guado/hda_verb.c | 109 ----- src/mainboard/google/guado/lan.c | 192 --------- src/mainboard/google/guado/mainboard.c | 44 -- src/mainboard/google/guado/onboard.h | 42 -- src/mainboard/google/guado/pei_data.c | 59 --- src/mainboard/google/guado/romstage.c | 64 --- src/mainboard/google/guado/smihandler.c | 90 ----- src/mainboard/google/guado/spd/Makefile.inc | 16 - src/mainboard/google/guado/spd/spd.c | 31 -- src/mainboard/google/guado/spd/spd.h | 22 - src/mainboard/google/guado/thermal.h | 55 --- src/mainboard/google/jecht/Kconfig | 36 +- src/mainboard/google/jecht/Kconfig.name | 13 + src/mainboard/google/jecht/Makefile.inc | 11 +- .../google/jecht/acpi/haswell_pci_irqs.asl | 82 ---- src/mainboard/google/jecht/acpi/mainboard.asl | 8 - src/mainboard/google/jecht/acpi/superio.asl | 22 +- src/mainboard/google/jecht/acpi/thermal.asl | 339 ---------------- src/mainboard/google/jecht/acpi_tables.c | 17 +- src/mainboard/google/jecht/devicetree.cb | 9 +- src/mainboard/google/jecht/dsdt.asl | 2 +- src/mainboard/google/jecht/fadt.c | 113 +----- src/mainboard/google/jecht/gpio.h | 120 ------ src/mainboard/google/jecht/hda_verb.c | 116 +++--- src/mainboard/google/jecht/lan.c | 2 +- src/mainboard/google/jecht/led.c | 31 ++ src/mainboard/google/jecht/mainboard.c | 104 ----- src/mainboard/google/jecht/onboard.h | 17 + src/mainboard/google/jecht/pei_data.c | 59 --- src/mainboard/google/jecht/romstage.c | 16 +- src/mainboard/google/jecht/smihandler.c | 8 + src/mainboard/google/jecht/spd/spd.c | 6 - src/mainboard/google/jecht/thermal.h | 55 --- .../guado/include/variant/acpi/thermal.asl | 339 ++++++++++++++++ .../jecht/variants/guado/include/variant/gpio.h | 120 ++++++ .../jecht/variants/guado/include/variant/thermal.h | 54 +++ .../google/jecht/variants/guado/pei_data.c | 59 +++ .../jecht/include/variant/acpi/thermal.asl | 339 ++++++++++++++++ .../jecht/variants/jecht/include/variant/gpio.h | 120 ++++++ .../jecht/variants/jecht/include/variant/thermal.h | 53 +++ .../google/jecht/variants/jecht/pei_data.c | 59 +++ .../rikku/include/variant/acpi/thermal.asl | 339 ++++++++++++++++ .../jecht/variants/rikku/include/variant/gpio.h | 120 ++++++ .../jecht/variants/rikku/include/variant/thermal.h | 53 +++ .../google/jecht/variants/rikku/pei_data.c | 59 +++ .../tidus/include/variant/acpi/thermal.asl | 447 +++++++++++++++++++++ .../jecht/variants/tidus/include/variant/gpio.h | 120 ++++++ .../jecht/variants/tidus/include/variant/thermal.h | 109 +++++ .../google/jecht/variants/tidus/pei_data.c | 59 +++ src/mainboard/google/rikku/Kconfig | 67 --- src/mainboard/google/rikku/Kconfig.name | 2 - src/mainboard/google/rikku/Makefile.inc | 24 -- src/mainboard/google/rikku/acpi/ec.asl | 0 .../google/rikku/acpi/haswell_pci_irqs.asl | 82 ---- src/mainboard/google/rikku/acpi/mainboard.asl | 69 ---- src/mainboard/google/rikku/acpi/platform.asl | 71 ---- src/mainboard/google/rikku/acpi/superio.asl | 31 -- src/mainboard/google/rikku/acpi/thermal.asl | 339 ---------------- src/mainboard/google/rikku/acpi/video.asl | 38 -- src/mainboard/google/rikku/acpi_tables.c | 65 --- src/mainboard/google/rikku/board_info.txt | 7 - src/mainboard/google/rikku/chromeos.c | 105 ----- src/mainboard/google/rikku/chromeos.fmd | 38 -- src/mainboard/google/rikku/cmos.layout | 132 ------ src/mainboard/google/rikku/devicetree.cb | 119 ------ src/mainboard/google/rikku/dsdt.asl | 56 --- src/mainboard/google/rikku/fadt.c | 154 ------- src/mainboard/google/rikku/gpio.h | 120 ------ src/mainboard/google/rikku/hda_verb.c | 109 ----- src/mainboard/google/rikku/lan.c | 192 --------- src/mainboard/google/rikku/mainboard.c | 44 -- src/mainboard/google/rikku/onboard.h | 42 -- src/mainboard/google/rikku/pei_data.c | 59 --- src/mainboard/google/rikku/romstage.c | 63 --- src/mainboard/google/rikku/smihandler.c | 89 ---- src/mainboard/google/rikku/spd/Makefile.inc | 16 - src/mainboard/google/rikku/spd/spd.c | 31 -- src/mainboard/google/rikku/spd/spd.h | 22 - src/mainboard/google/rikku/thermal.h | 55 --- src/mainboard/google/tidus/Kconfig | 59 --- src/mainboard/google/tidus/Kconfig.name | 2 - src/mainboard/google/tidus/Makefile.inc | 24 -- src/mainboard/google/tidus/acpi/ec.asl | 0 .../google/tidus/acpi/haswell_pci_irqs.asl | 82 ---- src/mainboard/google/tidus/acpi/mainboard.asl | 69 ---- src/mainboard/google/tidus/acpi/platform.asl | 71 ---- src/mainboard/google/tidus/acpi/superio.asl | 31 -- src/mainboard/google/tidus/acpi/thermal.asl | 447 --------------------- src/mainboard/google/tidus/acpi/video.asl | 38 -- src/mainboard/google/tidus/acpi_tables.c | 63 --- src/mainboard/google/tidus/board_info.txt | 7 - src/mainboard/google/tidus/chromeos.c | 105 ----- src/mainboard/google/tidus/chromeos.fmd | 38 -- src/mainboard/google/tidus/cmos.layout | 132 ------ src/mainboard/google/tidus/devicetree.cb | 125 ------ src/mainboard/google/tidus/dsdt.asl | 56 --- src/mainboard/google/tidus/fadt.c | 154 ------- src/mainboard/google/tidus/gpio.h | 120 ------ src/mainboard/google/tidus/hda_verb.c | 109 ----- src/mainboard/google/tidus/lan.c | 192 --------- src/mainboard/google/tidus/led.c | 31 -- src/mainboard/google/tidus/mainboard.c | 44 -- src/mainboard/google/tidus/onboard.h | 50 --- src/mainboard/google/tidus/pei_data.c | 59 --- src/mainboard/google/tidus/romstage.c | 61 --- src/mainboard/google/tidus/smihandler.c | 85 ---- src/mainboard/google/tidus/spd/Makefile.inc | 16 - src/mainboard/google/tidus/spd/spd.c | 31 -- src/mainboard/google/tidus/spd/spd.h | 22 - src/mainboard/google/tidus/thermal.h | 107 ----- 129 files changed, 2647 insertions(+), 7894 deletions(-) diff --git a/src/mainboard/google/guado/Kconfig b/src/mainboard/google/guado/Kconfig deleted file mode 100644 index ce6ee07..0000000 --- a/src/mainboard/google/guado/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -if BOARD_GOOGLE_GUADO - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SOC_INTEL_BROADWELL - select BOARD_ROMSIZE_KB_8192 - select SUPERIO_ITE_IT8772F - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - select PHYSICAL_REC_SWITCH - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/guado - -config MAINBOARD_PART_NUMBER - string - default "Guado" - -config IRQ_SLOT_COUNT - int - default 18 - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - - -config MAINBOARD_FAMILY - string - depends on GENERATE_SMBIOS_TABLES - default "Google_Guado" - -config GBB_HWID - string - depends on CHROMEOS - default "GUADO TEST A-A 7416" -endif diff --git a/src/mainboard/google/guado/Kconfig.name b/src/mainboard/google/guado/Kconfig.name deleted file mode 100644 index e8ae9fd..0000000 --- a/src/mainboard/google/guado/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_GUADO - bool "Guado" diff --git a/src/mainboard/google/guado/Makefile.inc b/src/mainboard/google/guado/Makefile.inc deleted file mode 100644 index 0557cc2..0000000 --- a/src/mainboard/google/guado/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += lan.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -romstage-y += pei_data.c -ramstage-y += pei_data.c diff --git a/src/mainboard/google/guado/acpi/ec.asl b/src/mainboard/google/guado/acpi/ec.asl deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/google/guado/acpi/haswell_pci_irqs.asl b/src/mainboard/google/guado/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9..0000000 --- a/src/mainboard/google/guado/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/guado/acpi/mainboard.asl b/src/mainboard/google/guado/acpi/mainboard.asl deleted file mode 100644 index 37457fc..0000000 --- a/src/mainboard/google/guado/acpi/mainboard.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/guado/onboard.h> - -Scope (\_SB) -{ - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } -} - -/* - * LAN connected to Root Port 3, becomes Root Port 1 after coalesce - */ -Scope (\_SB.PCI0.RP01) -{ - Device (ETH0) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { GUADO_NIC_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (GUADO_NIC_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (Local0) - } - } - } -} - -/* - * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce - */ -Scope (\_SB.PCI0.RP02) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { GUADO_WLAN_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (GUADO_WLAN_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (Local0) - } - } - } -} diff --git a/src/mainboard/google/guado/acpi/platform.asl b/src/mainboard/google/guado/acpi/platform.asl deleted file mode 100644 index 06de271..0000000 --- a/src/mainboard/google/guado/acpi/platform.asl +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Initialize thermal defaults */ - \_TZ.THRM._INI () - - Return(Package(){0,0}) -} diff --git a/src/mainboard/google/guado/acpi/superio.asl b/src/mainboard/google/guado/acpi/superio.asl deleted file mode 100644 index 9b71632..0000000 --- a/src/mainboard/google/guado/acpi/superio.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Values should match those defined in devicetree.cb */ - -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR - -#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard -#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 - -#include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/google/guado/acpi/thermal.asl b/src/mainboard/google/guado/acpi/thermal.asl deleted file mode 100644 index e686eab..0000000 --- a/src/mainboard/google/guado/acpi/thermal.asl +++ /dev/null @@ -1,339 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../thermal.h" - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - // Start fan at state 4 = lowest temp state - Method (_INI) - { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - - Method (TCHK, 0, Serialized) - { - // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) - - // Check for "no reading available - If (LEqual (Local0, 0x80)) { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - - // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - - // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) - - // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { - Return (CTOK (\TMAX)) - } - - // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) - Return (CTOK (Local0)) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for SuperIO to re-poll - Sleep (1000) - - // Re-read temperature from SuperIO - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (FAN0_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - } - - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (FAN1_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN1_THRESHOLD_ON)) - } - } - - Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { - Return (CTOK (FAN2_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN2_THRESHOLD_ON)) - } - } - - Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { - Return (CTOK (FAN3_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN3_THRESHOLD_ON)) - } - } - - Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { - Return (CTOK (FAN4_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN4_THRESHOLD_ON)) - } - } - - Name (_AL0, Package () { FAN0 }) - Name (_AL1, Package () { FAN1 }) - Name (_AL2, Package () { FAN2 }) - Name (_AL3, Package () { FAN3 }) - Name (_AL4, Package () { FAN4 }) - - PowerResource (FNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP2, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 2)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP3, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 3)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP4, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 4)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - Device (FAN0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { FNP0 }) - } - - Device (FAN1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { FNP1 }) - } - - Device (FAN2) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 2) - Name (_PR0, Package () { FNP2 }) - } - - Device (FAN3) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 3) - Name (_PR0, Package () { FNP3 }) - } - - Device (FAN4) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 4) - Name (_PR0, Package () { FNP4 }) - } - } -} diff --git a/src/mainboard/google/guado/acpi/video.asl b/src/mainboard/google/guado/acpi/video.asl deleted file mode 100644 index 6894655..0000000 --- a/src/mainboard/google/guado/acpi/video.asl +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/google/guado/acpi_tables.c b/src/mainboard/google/guado/acpi_tables.c deleted file mode 100644 index aa7f16f..0000000 --- a/src/mainboard/google/guado/acpi_tables.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/acpi.h> -#include <soc/nvs.h> -#include "thermal.h" - - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tmps = TEMPERATURE_SENSOR_ID; - - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 1; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} diff --git a/src/mainboard/google/guado/board_info.txt b/src/mainboard/google/guado/board_info.txt deleted file mode 100644 index aa7a848..0000000 --- a/src/mainboard/google/guado/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Vendor name: Asus -Board name: Chromebox2 -Category: half -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/guado/chromeos.c b/src/mainboard/google/guado/chromeos.c deleted file mode 100644 index 710ab48..0000000 --- a/src/mainboard/google/guado/chromeos.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/sata.h> - -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 - -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 -#define FLAG_DEV_MODE 2 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, - {GPIO_REC_MODE, ACTIVE_LOW, - get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, 1, "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -#ifdef __PRE_RAM__ -void save_chromeos_gpios(void) -{ - u32 flags = 0; - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} -#endif - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/guado/chromeos.fmd b/src/mainboard/google/guado/chromeos.fmd deleted file mode 100644 index 113fba6..0000000 --- a/src/mainboard/google/guado/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/google/guado/cmos.layout b/src/mainboard/google/guado/cmos.layout deleted file mode 100644 index c508d64..0000000 --- a/src/mainboard/google/guado/cmos.layout +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/guado/devicetree.cb b/src/mainboard/google/guado/devicetree.cb deleted file mode 100644 index 34929a1..0000000 --- a/src/mainboard/google/guado/devicetree.cb +++ /dev/null @@ -1,119 +0,0 @@ -chip soc/intel/broadwell - - # Disable eDP Hotplug - register "gpu_dp_d_hotplug" = "0x00" - - # Enable DisplayPort C Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Enable FAN2 - register "fan2_enable" = "1" - - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/guado/dsdt.asl b/src/mainboard/google/guado/dsdt.asl deleted file mode 100644 index c3d1fc9..0000000 --- a/src/mainboard/google/guado/dsdt.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <soc/intel/broadwell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> - } - } - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/google/guado/fadt.c b/src/mainboard/google/guado/fadt.c deleted file mode 100644 index c377d67..0000000 --- a/src/mainboard/google/guado/fadt.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <soc/acpi.h> -#include <cpu/x86/smm.h> -#include <soc/pch.h> -#include <soc/iomap.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = ACPI_BASE_ADDRESS; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/guado/gpio.h b/src/mainboard/google/guado/gpio.h deleted file mode 100644 index 4c167e3..0000000 --- a/src/mainboard/google/guado/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef GUADO_GPIO_H -#define GUADO_GPIO_H - -#include <soc/gpio.h> - -static const struct gpio_config mainboard_gpio_config[] = { - PCH_GPIO_UNUSED, /* 0: UNUSED */ - PCH_GPIO_UNUSED, /* 1: UNUSED */ - PCH_GPIO_UNUSED, /* 2: UNUSED */ - PCH_GPIO_UNUSED, /* 3: UNUSED */ - PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ - PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ - PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - PCH_GPIO_UNUSED, /* 11: SMBALERT */ - PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ - PCH_GPIO_UNUSED, /* 13: UNUSED */ - PCH_GPIO_UNUSED, /* 14: UNUSED */ - PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 16: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ - PCH_GPIO_UNUSED, /* 18: UNUSED */ - PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ - PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ - PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ - PCH_GPIO_UNUSED, /* 23: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ - PCH_GPIO_UNUSED, /* 25: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ - PCH_GPIO_UNUSED, /* 27: UNUSED */ - PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ - PCH_GPIO_UNUSED, /* 29: UNUSED */ - PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ - PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ - PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ - PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - PCH_GPIO_UNUSED, /* 37: UNUSED */ - PCH_GPIO_UNUSED, /* 38: UNUSED */ - PCH_GPIO_UNUSED, /* 39: UNUSED */ - PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ - PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ - PCH_GPIO_UNUSED, /* 44: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ - PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ - PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ - PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ - PCH_GPIO_UNUSED, /* 51: UNUSED */ - PCH_GPIO_UNUSED, /* 52: UNUSED */ - PCH_GPIO_UNUSED, /* 53: UNUSED */ - PCH_GPIO_UNUSED, /* 54: UNUSED */ - PCH_GPIO_UNUSED, /* 55: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ - PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ - PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ - PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ - PCH_GPIO_UNUSED, /* 61: UNUSED */ - PCH_GPIO_UNUSED, /* 62: UNUSED */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - PCH_GPIO_UNUSED, /* 64: UNUSED */ - PCH_GPIO_UNUSED, /* 65: UNUSED */ - PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 67: UNUSED */ - PCH_GPIO_UNUSED, /* 68: UNUSED */ - PCH_GPIO_UNUSED, /* 69: UNUSED */ - PCH_GPIO_UNUSED, /* 70: UNUSED */ - PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - PCH_GPIO_UNUSED, /* 72: UNUSED */ - PCH_GPIO_UNUSED, /* 73: UNUSED */ - PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - PCH_GPIO_UNUSED, /* 76: UNUSED */ - PCH_GPIO_UNUSED, /* 77: UNUSED */ - PCH_GPIO_UNUSED, /* 78: UNUSED */ - PCH_GPIO_UNUSED, /* 79: UNUSED */ - PCH_GPIO_UNUSED, /* 80: UNUSED */ - PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - PCH_GPIO_UNUSED, /* 83: UNUSED */ - PCH_GPIO_UNUSED, /* 84: UNUSED */ - PCH_GPIO_UNUSED, /* 85: UNUSED */ - PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 87: UNUSED */ - PCH_GPIO_UNUSED, /* 88: UNUSED */ - PCH_GPIO_UNUSED, /* 89: UNUSED */ - PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_UNUSED, /* 91: UNUSED */ - PCH_GPIO_UNUSED, /* 92: UNUSED */ - PCH_GPIO_UNUSED, /* 93: UNUSED */ - PCH_GPIO_UNUSED, /* 94: UNUSED */ - PCH_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/guado/hda_verb.c b/src/mainboard/google/guado/hda_verb.c deleted file mode 100644 index 284015d..0000000 --- a/src/mainboard/google/guado/hda_verb.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 - 0x10ec0283, // Subsystem ID - 0x0000000c, // Number of jacks (NID entries) - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - 0x00172083, - 0x00172102, - 0x001722ec, - 0x00172310, - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) DMIC */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - - /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - 0x01471cf0, - 0x01471d11, - 0x01471e11, - 0x01471f40, - - /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, - - /* Pin Complex (NID 0x18) MIC1 PORTB */ - 0x01971c11, // group 1, cap 1 - 0x01971d10, // black, jack detect - 0x01971ea7, // mic in, analog - 0x01971f03, // connector, left panel - - /* Pin Complex (NID 0x19) MIC2 PORTF */ - 0x01871cf0, - 0x01871d11, - 0x01871e11, - 0x01871f41, - - /* Pin Complex (NID 0x1A) LINE1 PORTC */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1B) LINE2 PORTE */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1d) PCBeep */ - 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable - 0x01d71d81, // mute spkr on hpout - 0x01d71e15, // pcbeep en able, checksum - 0x01d71f40, // no physical, internal - - /* Pin Complex (NID 0x1E) SPDIF-OUT */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - - /* Pin Complex (NID 0x21) HPOUT PORT-I */ - 0x02171c1f, // group1, - 0x02171d10, // black, jack detect - 0x02171e21, // HPOut, 1/8 stereo - 0x02171f03, // connector, left panel - - /* Undocumented settings from Realtek (needed for beep_gen) */ - /* Widget node 0x20 */ - 0x02050010, - 0x02040c20, - 0x0205001b, - 0x0204081b, -}; - -const u32 pc_beep_verbs[] = { - 0x00170500, /* power up everything (codec, dac, adc, mixers) */ - 0x01470740, /* enable speaker out */ - 0x01470c02, /* set speaker EAPD pin */ - 0x0143b01f, /* unmute speaker */ - 0x00c37100, /* unmute mixer nid 0xc input 1 */ - 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ -}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/guado/lan.c b/src/mainboard/google/guado/lan.c deleted file mode 100644 index 0d97dbe..0000000 --- a/src/mainboard/google/guado/lan.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <string.h> -#include <types.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <fmap.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "onboard.h" - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", - *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_DEBUG, - "Error: Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(GUADO_NIC_VENDOR_ID, - GUADO_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((GUADO_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/guado/mainboard.c b/src/mainboard/google/guado/mainboard.c deleted file mode 100644 index 7e57505..0000000 --- a/src/mainboard/google/guado/mainboard.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "onboard.h" - -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} - -static void mainboard_init(device_t dev) -{ - lan_init(); -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/guado/onboard.h b/src/mainboard/google/guado/onboard.h deleted file mode 100644 index 783c44a..0000000 --- a/src/mainboard/google/guado/onboard.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#ifndef __ACPI__ -void lan_init(void); -#endif - -/* defines for programming the MAC address */ -#define GUADO_NIC_VENDOR_ID 0x10EC -#define GUADO_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define GUADO_NIC_LED_MODE 0x00 - -/* NIC wake is GPIO 8 */ -#define GUADO_NIC_WAKE_GPIO 8 - -/* WLAN wake is GPIO 10 */ -#define GUADO_WLAN_WAKE_GPIO 10 - -/* IT8772F defs */ -#define IT8772F_BASE 0x2e -#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) -#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) -#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) - -#endif diff --git a/src/mainboard/google/guado/pei_data.c b/src/mainboard/google/guado/pei_data.c deleted file mode 100644 index 1b5ea51..0000000 --- a/src/mainboard/google/guado/pei_data.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - pei_data->ec_present = 0; - - /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, - USB_PORT_MINI_PCIE); - /* P1: Port A, CN22 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, - USB_PORT_INTERNAL); - /* P2: Port B, CN23 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, - USB_PORT_INTERNAL); - /* P3: WLAN */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_MINI_PCIE); - /* P4: Port C, CN25 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P5: Port D, CN25 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, - USB_PORT_SKIP); - - /* P1: CN22 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); - /* P2: CN23 */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: CN25 */ - pei_data_usb3_port(pei_data, 2, 1, 2, 0); - /* P4: CN25 */ - pei_data_usb3_port(pei_data, 3, 1, 2, 0); -} diff --git a/src/mainboard/google/guado/romstage.c b/src/mainboard/google/guado/romstage.c deleted file mode 100644 index 24acc80..0000000 --- a/src/mainboard/google/guado/romstage.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> -#include <mainboard/google/guado/spd/spd.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8772f/it8772f.h> -#include "gpio.h" -#include "onboard.h" - - -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data pei_data; - - post_code(0x32); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; - - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); -} - -void mainboard_pre_console_init(void) -{ - /* Early SuperIO setup */ - ite_kill_watchdog(IT8772F_GPIO_DEV); - it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); - ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Turn On GPIO10.LED */ - it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, - SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - -} diff --git a/src/mainboard/google/guado/smihandler.c b/src/mainboard/google/guado/smihandler.c deleted file mode 100644 index d37cc33..0000000 --- a/src/mainboard/google/guado/smihandler.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <elog.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <superio/ite/it8772f/it8772f.h> -#include "onboard.h" - - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - return 1; -} - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x01 /* polarity */, 0x01 /* 1=pullup */, - 0x01 /* output */, 0x00, /* 0=Alternate function */ - SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - break; - case ACPI_S5: - it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, - SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - break; - default: - break; - } - return; -} - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - break; - case APM_CNT_ACPI_DISABLE: - break; - } - return 0; -} diff --git a/src/mainboard/google/guado/spd/Makefile.inc b/src/mainboard/google/guado/spd/Makefile.inc deleted file mode 100644 index 275d983..0000000 --- a/src/mainboard/google/guado/spd/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c diff --git a/src/mainboard/google/guado/spd/spd.c b/src/mainboard/google/guado/spd/spd.c deleted file mode 100644 index 5df4d14..0000000 --- a/src/mainboard/google/guado/spd/spd.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/pei_data.h> -#include <mainboard/google/guado/spd/spd.h> - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - pei_data->spd_addresses[0] = 0xa0; - pei_data->spd_addresses[1] = 0x00; - pei_data->spd_addresses[2] = 0xa4; - pei_data->spd_addresses[3] = 0x00; - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; - // Enable 2x refresh mode - pei_data->ddr_refresh_2x = 1; - pei_data->dq_pins_interleaved = 1; -} diff --git a/src/mainboard/google/guado/spd/spd.h b/src/mainboard/google/guado/spd/spd.h deleted file mode 100644 index 02709cd..0000000 --- a/src/mainboard/google/guado/spd/spd.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/guado/thermal.h b/src/mainboard/google/guado/thermal.h deleted file mode 100644 index 685b988..0000000 --- a/src/mainboard/google/guado/thermal.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -#define TEMPERATURE_SENSOR_ID 0 /* PECI */ - -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 40 -#define FAN3_THRESHOLD_ON 50 -#define FAN3_PWM 0x55 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 55 -#define FAN2_THRESHOLD_ON 67 -#define FAN2_PWM 0xa6 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 65 -#define FAN1_THRESHOLD_ON 70 -#define FAN1_PWM 0xc0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 90 -#define FAN0_THRESHOLD_ON 100 -#define FAN0_PWM 0xff - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 104 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 - -#endif diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 8a30a4d..37dac7e 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,7 +1,5 @@ -if BOARD_GOOGLE_JECHT - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y +config BOARD_GOOGLE_BASEBOARD_JECHT + def_bool n select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F @@ -11,7 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select INTEL_INT15 + +if BOARD_GOOGLE_BASEBOARD_JECHT config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -23,9 +22,28 @@ config MAINBOARD_DIR string default google/jecht + +config VARIANT_DIR + string + default "guado" if BOARD_GOOGLE_GUADO + default "jecht" if BOARD_GOOGLE_JECHT + default "rikku" if BOARD_GOOGLE_RIKKU + default "tidus" if BOARD_GOOGLE_TIDUS + config MAINBOARD_PART_NUMBER string - default "Jecht" + default "Guado" if BOARD_GOOGLE_GUADO + default "Jecht" if BOARD_GOOGLE_JECHT + default "Rikku" if BOARD_GOOGLE_RIKKU + default "Tidus" if BOARD_GOOGLE_TIDUS + +config GBB_HWID + string + depends on CHROMEOS + default "GUADO TEST A-A 7416" if BOARD_GOOGLE_GUADO + default "JECHT TEST A-A 8958" if BOARD_GOOGLE_JECHT + default "RIKKU TEST A-A 0702" if BOARD_GOOGLE_RIKKU + default "TIDUS TEST A-A 0595" if BOARD_GOOGLE_TIDUS config MAX_CPUS int @@ -33,7 +51,7 @@ config MAX_CPUS config VGA_BIOS_FILE string - default "pci8086,0166.rom" + default "pci8086,0406.rom" config HAVE_IFD_BIN bool @@ -43,8 +61,4 @@ config HAVE_ME_BIN bool default n -config GBB_HWID - string - depends on CHROMEOS - default "JECHT TEST A-A 8958" endif diff --git a/src/mainboard/google/jecht/Kconfig.name b/src/mainboard/google/jecht/Kconfig.name index af806ee..2a07654 100644 --- a/src/mainboard/google/jecht/Kconfig.name +++ b/src/mainboard/google/jecht/Kconfig.name @@ -1,2 +1,15 @@ +config BOARD_GOOGLE_GUADO + bool "Guado" + select BOARD_GOOGLE_BASEBOARD_JECHT + config BOARD_GOOGLE_JECHT bool "Jecht" + select BOARD_GOOGLE_BASEBOARD_JECHT + +config BOARD_GOOGLE_RIKKU + bool "Rikku" + select BOARD_GOOGLE_BASEBOARD_JECHT + +config BOARD_GOOGLE_TIDUS + bool "Tidus" + select BOARD_GOOGLE_BASEBOARD_JECHT diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 0557cc2..4438ace 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -18,7 +18,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c -romstage-y += pei_data.c -ramstage-y += pei_data.c +romstage-y += variants/$(VARIANT_DIR)/pei_data.c +ramstage-y += variants/$(VARIANT_DIR)/pei_data.c + +romstage-y += led.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include \ No newline at end of file diff --git a/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl b/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9..0000000 --- a/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/jecht/acpi/mainboard.asl b/src/mainboard/google/jecht/acpi/mainboard.asl index b069446..16e6352 100644 --- a/src/mainboard/google/jecht/acpi/mainboard.asl +++ b/src/mainboard/google/jecht/acpi/mainboard.asl @@ -25,14 +25,6 @@ Scope (\_SB) } /* - * LPC Trusted Platform Module - */ -Scope (\_SB.PCI0.LPCB) -{ - #include <drivers/pc80/tpm/acpi/tpm.asl> -} - -/* * LAN connected to Root Port 3, becomes Root Port 1 after coalesce */ Scope (\_SB.PCI0.RP01) diff --git a/src/mainboard/google/jecht/acpi/superio.asl b/src/mainboard/google/jecht/acpi/superio.asl index 9b71632..1d37792 100644 --- a/src/mainboard/google/jecht/acpi/superio.asl +++ b/src/mainboard/google/jecht/acpi/superio.asl @@ -15,17 +15,17 @@ /* Values should match those defined in devicetree.cb */ -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR -#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard -#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 +#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard +#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 #include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/google/jecht/acpi/thermal.asl b/src/mainboard/google/jecht/acpi/thermal.asl deleted file mode 100644 index e686eab..0000000 --- a/src/mainboard/google/jecht/acpi/thermal.asl +++ /dev/null @@ -1,339 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../thermal.h" - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - // Start fan at state 4 = lowest temp state - Method (_INI) - { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - - Method (TCHK, 0, Serialized) - { - // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) - - // Check for "no reading available - If (LEqual (Local0, 0x80)) { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - - // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - - // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) - - // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { - Return (CTOK (\TMAX)) - } - - // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) - Return (CTOK (Local0)) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for SuperIO to re-poll - Sleep (1000) - - // Re-read temperature from SuperIO - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (FAN0_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - } - - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (FAN1_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN1_THRESHOLD_ON)) - } - } - - Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { - Return (CTOK (FAN2_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN2_THRESHOLD_ON)) - } - } - - Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { - Return (CTOK (FAN3_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN3_THRESHOLD_ON)) - } - } - - Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { - Return (CTOK (FAN4_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN4_THRESHOLD_ON)) - } - } - - Name (_AL0, Package () { FAN0 }) - Name (_AL1, Package () { FAN1 }) - Name (_AL2, Package () { FAN2 }) - Name (_AL3, Package () { FAN3 }) - Name (_AL4, Package () { FAN4 }) - - PowerResource (FNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP2, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 2)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP3, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 3)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP4, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 4)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - Device (FAN0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { FNP0 }) - } - - Device (FAN1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { FNP1 }) - } - - Device (FAN2) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 2) - Name (_PR0, Package () { FNP2 }) - } - - Device (FAN3) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 3) - Name (_PR0, Package () { FNP3 }) - } - - Device (FAN4) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 4) - Name (_PR0, Package () { FNP4 }) - } - } -} diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 655acc6..0c6a372 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -26,7 +26,17 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/nvs.h> -#include "thermal.h" +#include <variant/thermal.h> + + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = TEMPERATURE_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -38,10 +48,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* Disable USB ports in S5 */ gnvs->s5u0 = 0; - gnvs->tmps = TEMPERATURE_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 4d16ed6..8a2129f 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,9 +9,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - - - register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x8a" register "pirqc_routing" = "0x8b" @@ -84,8 +81,14 @@ chip soc/intel/broadwell register "skip_keyboard" = "1" # Enable PECI on TMPIN3 register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" # Enable FAN2 register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 3132aab..1ac3288 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -44,7 +44,7 @@ DefinitionBlock( } // Thermal handler - #include "acpi/thermal.asl" + #include <variant/acpi/thermal.asl> // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index c377d67..70fd2ce 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -15,21 +15,16 @@ */ #include <string.h> -#include <device/pci.h> #include <soc/acpi.h> -#include <cpu/x86/smm.h> -#include <soc/pch.h> -#include <soc/iomap.h> -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = ACPI_BASE_ADDRESS; memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); @@ -40,114 +35,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_in_fadt(fadt); header->checksum = acpi_checksum((void *) fadt, header->length); diff --git a/src/mainboard/google/jecht/gpio.h b/src/mainboard/google/jecht/gpio.h deleted file mode 100644 index 94e6516..0000000 --- a/src/mainboard/google/jecht/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef JECHT_GPIO_H -#define JECHT_GPIO_H - -#include <soc/gpio.h> - -static const struct gpio_config mainboard_gpio_config[] = { - PCH_GPIO_UNUSED, /* 0: UNUSED */ - PCH_GPIO_UNUSED, /* 1: UNUSED */ - PCH_GPIO_UNUSED, /* 2: UNUSED */ - PCH_GPIO_UNUSED, /* 3: UNUSED */ - PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ - PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ - PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - PCH_GPIO_UNUSED, /* 11: SMBALERT */ - PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ - PCH_GPIO_UNUSED, /* 13: UNUSED */ - PCH_GPIO_UNUSED, /* 14: UNUSED */ - PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 16: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ - PCH_GPIO_UNUSED, /* 18: UNUSED */ - PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ - PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ - PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ - PCH_GPIO_UNUSED, /* 23: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ - PCH_GPIO_UNUSED, /* 25: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ - PCH_GPIO_UNUSED, /* 27: UNUSED */ - PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ - PCH_GPIO_UNUSED, /* 29: UNUSED */ - PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ - PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ - PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ - PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - PCH_GPIO_UNUSED, /* 37: UNUSED */ - PCH_GPIO_UNUSED, /* 38: UNUSED */ - PCH_GPIO_UNUSED, /* 39: UNUSED */ - PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ - PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ - PCH_GPIO_UNUSED, /* 44: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ - PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ - PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_UNUSED, /* 49: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ - PCH_GPIO_UNUSED, /* 51: UNUSED */ - PCH_GPIO_UNUSED, /* 52: UNUSED */ - PCH_GPIO_UNUSED, /* 53: UNUSED */ - PCH_GPIO_UNUSED, /* 54: UNUSED */ - PCH_GPIO_UNUSED, /* 55: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ - PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ - PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ - PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ - PCH_GPIO_UNUSED, /* 61: UNUSED */ - PCH_GPIO_UNUSED, /* 62: UNUSED */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - PCH_GPIO_UNUSED, /* 64: UNUSED */ - PCH_GPIO_UNUSED, /* 65: UNUSED */ - PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 67: UNUSED */ - PCH_GPIO_UNUSED, /* 68: UNUSED */ - PCH_GPIO_UNUSED, /* 69: UNUSED */ - PCH_GPIO_UNUSED, /* 70: UNUSED */ - PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - PCH_GPIO_UNUSED, /* 72: UNUSED */ - PCH_GPIO_UNUSED, /* 73: UNUSED */ - PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - PCH_GPIO_UNUSED, /* 76: UNUSED */ - PCH_GPIO_UNUSED, /* 77: UNUSED */ - PCH_GPIO_UNUSED, /* 78: UNUSED */ - PCH_GPIO_UNUSED, /* 79: UNUSED */ - PCH_GPIO_UNUSED, /* 80: UNUSED */ - PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - PCH_GPIO_UNUSED, /* 83: UNUSED */ - PCH_GPIO_UNUSED, /* 84: UNUSED */ - PCH_GPIO_UNUSED, /* 85: UNUSED */ - PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 87: UNUSED */ - PCH_GPIO_UNUSED, /* 88: UNUSED */ - PCH_GPIO_UNUSED, /* 89: UNUSED */ - PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_UNUSED, /* 91: UNUSED */ - PCH_GPIO_UNUSED, /* 92: UNUSED */ - PCH_GPIO_UNUSED, /* 93: UNUSED */ - PCH_GPIO_UNUSED, /* 94: UNUSED */ - PCH_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 284015d..01ba78f 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -19,75 +19,59 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 0x10ec0283, // Subsystem ID - 0x0000000c, // Number of jacks (NID entries) + 0x0000000e, // Number of jacks (NID entries) - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - 0x00172083, - 0x00172102, - 0x001722ec, - 0x00172310, + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x11790670), /* Pin Widget Verb Table */ - /* Pin Complex (NID 0x12) DMIC */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - - /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - 0x01471cf0, - 0x01471d11, - 0x01471e11, - 0x01471f40, - - /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, - - /* Pin Complex (NID 0x18) MIC1 PORTB */ - 0x01971c11, // group 1, cap 1 - 0x01971d10, // black, jack detect - 0x01971ea7, // mic in, analog - 0x01971f03, // connector, left panel - - /* Pin Complex (NID 0x19) MIC2 PORTF */ - 0x01871cf0, - 0x01871d11, - 0x01871e11, - 0x01871f41, - - /* Pin Complex (NID 0x1A) LINE1 PORTC */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1B) LINE2 PORTE */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1d) PCBeep */ - 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable - 0x01d71d81, // mute spkr on hpout - 0x01d71e15, // pcbeep en able, checksum - 0x01d71f40, // no physical, internal - - /* Pin Complex (NID 0x1E) SPDIF-OUT */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, + /* Pin Complex (NID 0x12) DMIC - Disabled */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ + AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0), + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* Pin Complex (NID 0x18) MIC1 PORTB */ + // group 1, cap 1 + // black, jack detect + // mic in, analog + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x18, 0x03a71011), + + /* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) PCBeep */ + // eapd low on ex-amp, laptop, custom enable + // mute spkr on hpout + // pcbeep en able, checksum + // no physical, internal + AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d), + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), /* Pin Complex (NID 0x21) HPOUT PORT-I */ - 0x02171c1f, // group1, - 0x02171d10, // black, jack detect - 0x02171e21, // HPOut, 1/8 stereo - 0x02171f03, // connector, left panel + // group1, + // black, jack detect + // HPOut, 1/8 stereo + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), /* Undocumented settings from Realtek (needed for beep_gen) */ /* Widget node 0x20 */ @@ -95,6 +79,12 @@ const u32 cim_verb_data[] = { 0x02040c20, 0x0205001b, 0x0204081b, + + /* Tuned jack detection */ + 0x02050043, + 0x0204A614, + 0x02050047, + 0x02049470, }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index bb6ff6e..59ed111 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <southbridge/intel/bd82x6x/pch.h> +#include <soc/pch.h> #include "onboard.h" static unsigned int search(char *p, u8 *a, unsigned int lengthp, diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c new file mode 100644 index 0000000..50cf32e --- /dev/null +++ b/src/mainboard/google/jecht/led.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <superio/ite/it8772f/it8772f.h> +#include "onboard.h" + +void set_power_led(int state) +{ + it8772f_gpio_led(IT8772F_GPIO_DEV, + 1, /* set */ + 0x01, /* select */ + state == LED_OFF ? 0x00 : 0x01, /* polarity */ + state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ + 0x01, /* output */ + state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ + SIO_GPIO_BLINK_GPIO10, + IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); +} diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index cacf0e7..7e57505 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -14,22 +14,8 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> -#include <smbios.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -39,92 +25,6 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -#if CONFIG_VGA_ROM_RUN -static int int15_handler(void) -{ - int res = 0; - - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); - - switch (X86_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default - */ - X86_AX = 0x005f; - X86_CX = 0x0001; - res = 1; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) * - * bit 2 = EFP * - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) * - * bit 6 = EFP2 * - * bit 7 = LFP2 - */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - X86_AX = 0x005f; - X86_CX = 0x0003; - res = 1; - break; - case 0x5f70: - switch ((X86_CX >> 8) & 0xff) { - case 0: - /* Get Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 1: - /* Set Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 2: - /* Get SG/Non-SG mode */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", - ((X86_CX >> 8) & 0xff)); - break; - } - break; - - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); - break; - } - return res; -} -#endif - static void mainboard_init(device_t dev) { lan_init(); @@ -137,10 +37,6 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if CONFIG_VGA_ROM_RUN - /* Install custom int15 handler for VGA OPROM */ - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index f5212d0..96c792c 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -18,6 +18,14 @@ #ifndef __ACPI__ void lan_init(void); + +void set_power_led(int state); + +enum { + LED_OFF = 0, + LED_ON, + LED_BLINK, +}; #endif /* defines for programming the MAC address */ @@ -33,4 +41,13 @@ void lan_init(void); /* WLAN wake is GPIO 10 */ #define JECHT_WLAN_WAKE_GPIO 10 +/* USB Charger Control: GPIO26 */ +#define GPIO_USB_CTL_1 26 + +/* IT8772F defs */ +#define IT8772F_BASE 0x2e +#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) +#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) +#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) + #endif diff --git a/src/mainboard/google/jecht/pei_data.c b/src/mainboard/google/jecht/pei_data.c deleted file mode 100644 index 1b5ea51..0000000 --- a/src/mainboard/google/jecht/pei_data.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - pei_data->ec_present = 0; - - /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, - USB_PORT_MINI_PCIE); - /* P1: Port A, CN22 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, - USB_PORT_INTERNAL); - /* P2: Port B, CN23 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, - USB_PORT_INTERNAL); - /* P3: WLAN */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_MINI_PCIE); - /* P4: Port C, CN25 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P5: Port D, CN25 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, - USB_PORT_SKIP); - - /* P1: CN22 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); - /* P2: CN23 */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: CN25 */ - pei_data_usb3_port(pei_data, 2, 1, 2, 0); - /* P4: CN25 */ - pei_data_usb3_port(pei_data, 3, 1, 2, 0); -} diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 2d19b26..a71d3fe 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -25,11 +25,9 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <mainboard/google/jecht/spd/spd.h> -#include "gpio.h" +#include <variant/gpio.h> +#include "onboard.h" -#define DUMMY_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) void mainboard_romstage_entry(struct romstage_params *rp) { @@ -53,7 +51,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) void mainboard_pre_console_init(void) { /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(DUMMY_DEV); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); + ite_kill_watchdog(IT8772F_GPIO_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn On Power LED */ + set_power_led(LED_ON); + } diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 3b47ac6..8243354 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -27,6 +27,7 @@ #include <soc/nvs.h> #include <soc/pm.h> #include <soc/smm.h> +#include "onboard.h" int mainboard_io_trap_handler(int smif) { @@ -58,8 +59,15 @@ void mainboard_smi_sleep(u8 slp_typ) /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: + set_power_led(LED_BLINK); + + /* Enable DCP mode */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) { + set_gpio(GPIO_USB_CTL_1, 0); + } break; case ACPI_S5: + set_power_led(LED_OFF); break; } } diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 407dd7f..2540964 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -13,13 +13,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> -#include <endian.h> -#include <string.h> -#include <soc/gpio.h> #include <soc/pei_data.h> -#include <soc/romstage.h> #include <mainboard/google/jecht/spd/spd.h> /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/jecht/thermal.h b/src/mainboard/google/jecht/thermal.h deleted file mode 100644 index 3e8a7da..0000000 --- a/src/mainboard/google/jecht/thermal.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -#define TEMPERATURE_SENSOR_ID 0 /* PECI */ - -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 50 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x76 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 59 -#define FAN2_THRESHOLD_ON 65 -#define FAN2_PWM 0x98 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 68 -#define FAN1_THRESHOLD_ON 75 -#define FAN1_PWM 0xbf - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 80 -#define FAN0_THRESHOLD_ON 86 -#define FAN0_PWM 0xdc - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 98 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 - -#endif diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..1cd1b9b --- /dev/null +++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (0)) + } Else { + Return (CTOK (0)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h b/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h new file mode 100644 index 0000000..4c167e3 --- /dev/null +++ b/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GUADO_GPIO_H +#define GUADO_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h new file mode 100644 index 0000000..68421ed --- /dev/null +++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is at default speed */ +#define FAN4_PWM 0x4d + + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x55 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0xa6 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 65 +#define FAN1_THRESHOLD_ON 70 +#define FAN1_PWM 0xc0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 90 +#define FAN0_THRESHOLD_ON 100 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c new file mode 100644 index 0000000..1b5ea51 --- /dev/null +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..1cd1b9b --- /dev/null +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (0)) + } Else { + Return (CTOK (0)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h b/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h new file mode 100644 index 0000000..94e6516 --- /dev/null +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef JECHT_GPIO_H +#define JECHT_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_UNUSED, /* 49: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h new file mode 100644 index 0000000..29559eb --- /dev/null +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is at default speed */ +#define FAN4_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 50 +#define FAN3_THRESHOLD_ON 55 +#define FAN3_PWM 0x76 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 59 +#define FAN2_THRESHOLD_ON 65 +#define FAN2_PWM 0x98 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 68 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xbf + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 80 +#define FAN0_THRESHOLD_ON 86 +#define FAN0_PWM 0xdc + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 98 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c new file mode 100644 index 0000000..1b5ea51 --- /dev/null +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..151ac51 --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (0)) + } Else { + Return (CTOK (0)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h b/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h new file mode 100644 index 0000000..f58ad24 --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef RIKKU_GPIO_H +#define RIKKU_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h new file mode 100644 index 0000000..b914453 --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is at default speed */ +#define FAN4_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 42 +#define FAN3_THRESHOLD_ON 47 +#define FAN3_PWM 0xa5 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 54 +#define FAN2_THRESHOLD_ON 59 +#define FAN2_PWM 0xb2 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 66 +#define FAN1_THRESHOLD_ON 71 +#define FAN1_PWM 0xc9 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 78 +#define FAN0_THRESHOLD_ON 83 +#define FAN0_PWM 0xd8 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c new file mode 100644 index 0000000..4eeabbe --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..78e7bf7 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl @@ -0,0 +1,447 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + Name (F0ON, FAN0_2_THRESHOLD_ON) + Name (F0OF, FAN0_2_THRESHOLD_OFF) + Name (F0PW, FAN0_2_PWM) + Name (F1ON, FAN1_2_THRESHOLD_ON) + Name (F1OF, FAN1_2_THRESHOLD_OFF) + Name (F1PW, FAN1_2_PWM) + Name (F2ON, FAN2_2_THRESHOLD_ON) + Name (F2OF, FAN2_2_THRESHOLD_OFF) + Name (F2PW, FAN2_2_PWM) + Name (F3ON, FAN3_2_THRESHOLD_ON) + Name (F3OF, FAN3_2_THRESHOLD_OFF) + Name (F3PW, FAN3_2_PWM) + Name (F4PW, FAN4_2_PWM) + Name (THTB, 2) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Thermal Table 0 + Method (TTB0, 0) { + Store (FAN0_0_THRESHOLD_ON, F0ON) + Store (FAN0_0_THRESHOLD_OFF, F0OF) + Store (FAN0_0_PWM, F0PW) + Store (FAN1_0_THRESHOLD_ON, F1ON) + Store (FAN1_0_THRESHOLD_OFF, F1OF) + Store (FAN1_0_PWM, F1PW) + Store (FAN2_0_THRESHOLD_ON, F2ON) + Store (FAN2_0_THRESHOLD_OFF, F2OF) + Store (FAN2_0_PWM, F2PW) + Store (FAN3_0_THRESHOLD_ON, F3ON) + Store (FAN3_0_THRESHOLD_OFF, F3OF) + Store (FAN3_0_PWM, F3PW) + Store (FAN4_0_PWM, F4PW) + Store (0, THTB) + } + + // Thermal Table 1 + Method (TTB1, 0) { + Store (FAN0_1_THRESHOLD_ON, F0ON) + Store (FAN0_1_THRESHOLD_OFF, F0OF) + Store (FAN0_1_PWM, F0PW) + Store (FAN1_1_THRESHOLD_ON, F1ON) + Store (FAN1_1_THRESHOLD_OFF, F1OF) + Store (FAN1_1_PWM, F1PW) + Store (FAN2_1_THRESHOLD_ON, F2ON) + Store (FAN2_1_THRESHOLD_OFF, F2OF) + Store (FAN2_1_PWM, F2PW) + Store (FAN3_1_THRESHOLD_ON, F3ON) + Store (FAN3_1_THRESHOLD_OFF, F3OF) + Store (FAN3_1_PWM, F3PW) + Store (FAN4_1_PWM, F4PW) + Store (1, THTB) + } + + // Thermal Table 2 + Method (TTB2, 0) { + Store (FAN0_2_THRESHOLD_ON, F0ON) + Store (FAN0_2_THRESHOLD_OFF, F0OF) + Store (FAN0_2_PWM, F0PW) + Store (FAN1_2_THRESHOLD_ON, F1ON) + Store (FAN1_2_THRESHOLD_OFF, F1OF) + Store (FAN1_2_PWM, F1PW) + Store (FAN2_2_THRESHOLD_ON, F2ON) + Store (FAN2_2_THRESHOLD_OFF, F2OF) + Store (FAN2_2_PWM, F2PW) + Store (FAN3_2_THRESHOLD_ON, F3ON) + Store (FAN3_2_THRESHOLD_OFF, F3OF) + Store (FAN3_2_PWM, F3PW) + Store (FAN4_2_PWM, F4PW) + Store (2, THTB) + } + + // Update Thermal Table + Method (UPTB, 0) { + // Get System Temperature via SuperIO TMPIN2 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN2, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) + } + + If (LEqual (THTB, 2)) { + If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { + TTB0 () + } ElseIf (LGreaterEqual (Local0, THERMAL_POLICY_1_THRESHOLD_ON)) { + TTB1 () + } + } ElseIf (LEqual (THTB, 1)) { + If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { + TTB0 () + } ElseIf (LLessEqual (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { + TTB2 () + } + } Else { + If (LLess (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { + TTB2 () + } ElseIf (LLessEqual (Local0, THERMAL_POLICY_0_THRESHOLD_OFF)) { + TTB1 () + } + } + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Update Thermal Table + UPTB () + + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (F0OF)) + } Else { + Return (CTOK (F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (F1OF)) + } Else { + Return (CTOK (F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (F2OF)) + } Else { + Return (CTOK (F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (F3OF)) + } Else { + Return (CTOK (F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (0)) + } Else { + Return (CTOK (0)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (F0PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h b/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h new file mode 100644 index 0000000..846fe81 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef TIDUS_GPIO_H +#define TIDUS_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 48: USB4_PWR_EN */ + PCH_GPIO_OUT_LOW, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h new file mode 100644 index 0000000..4236424 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Thermal Policy 0 */ +/* Fan is at default speed */ +#define FAN4_0_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_0_THRESHOLD_OFF 62 +#define FAN3_0_THRESHOLD_ON 70 +#define FAN3_0_PWM 0x5e + +/* Fan is at MEDIUM speed */ +#define FAN2_0_THRESHOLD_OFF 68 +#define FAN2_0_THRESHOLD_ON 81 +#define FAN2_0_PWM 0x78 + +/* Fan is at HIGH speed */ +#define FAN1_0_THRESHOLD_OFF 78 +#define FAN1_0_THRESHOLD_ON 91 +#define FAN1_0_PWM 0x93 + +/* Fan is at FULL speed */ +#define FAN0_0_THRESHOLD_OFF 88 +#define FAN0_0_THRESHOLD_ON 100 +#define FAN0_0_PWM 0xb0 + +/* Thermal Policy 1 */ +/* Fan is at default speed */ +#define FAN4_1_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_1_THRESHOLD_OFF 62 +#define FAN3_1_THRESHOLD_ON 70 +#define FAN3_1_PWM 0x5e + +/* Fan is at MEDIUM speed */ +#define FAN2_1_THRESHOLD_OFF 68 +#define FAN2_1_THRESHOLD_ON 81 +#define FAN2_1_PWM 0x70 + +/* Fan is at HIGH speed */ +#define FAN1_1_THRESHOLD_OFF 78 +#define FAN1_1_THRESHOLD_ON 91 +#define FAN1_1_PWM 0x83 + +/* Fan is at FULL speed */ +#define FAN0_1_THRESHOLD_OFF 88 +#define FAN0_1_THRESHOLD_ON 100 +#define FAN0_1_PWM 0x93 + +/* Thermal Policy 2 */ +/* Fan is at default speed */ +#define FAN4_2_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_2_THRESHOLD_OFF 62 +#define FAN3_2_THRESHOLD_ON 70 +#define FAN3_2_PWM 0x59 + +/* Fan is at MEDIUM speed */ +#define FAN2_2_THRESHOLD_OFF 68 +#define FAN2_2_THRESHOLD_ON 81 +#define FAN2_2_PWM 0x63 + +/* Fan is at HIGH speed */ +#define FAN1_2_THRESHOLD_OFF 78 +#define FAN1_2_THRESHOLD_ON 91 +#define FAN1_2_PWM 0x6e + +/* Fan is at FULL speed */ +#define FAN0_2_THRESHOLD_OFF 88 +#define FAN0_2_THRESHOLD_ON 100 +#define FAN0_2_PWM 0x7e + +/* Threshold to change thermal policy */ +#define THERMAL_POLICY_0_THRESHOLD_OFF 38 +#define THERMAL_POLICY_0_THRESHOLD_ON 40 + +#define THERMAL_POLICY_1_THRESHOLD_OFF 33 +#define THERMAL_POLICY_1_THRESHOLD_ON 35 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 103 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 105 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c new file mode 100644 index 0000000..7c03422 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P1: Port 3, USB3 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port 4, USB4 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: Mini Card */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port 1, USB1 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port 2, USB2 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: Pin Header */ + pei_data_usb2_port(pei_data, 7, 0x0040, 1, 3, + USB_PORT_INTERNAL); + + /* P1: USB1 */ + pei_data_usb3_port(pei_data, 0, 1, 2, 0); + /* P2: USB2 */ + pei_data_usb3_port(pei_data, 1, 1, 2, 0); + /* P3: USB3 */ + pei_data_usb3_port(pei_data, 2, 1, 0, 0); + /* P4: USB4 */ + pei_data_usb3_port(pei_data, 3, 1, 1, 0); +} diff --git a/src/mainboard/google/rikku/Kconfig b/src/mainboard/google/rikku/Kconfig deleted file mode 100644 index 8dc1551..0000000 --- a/src/mainboard/google/rikku/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -if BOARD_GOOGLE_RIKKU - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SOC_INTEL_BROADWELL - select BOARD_ROMSIZE_KB_8192 - select SUPERIO_ITE_IT8772F - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - select PHYSICAL_REC_SWITCH - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - -config VBOOT_REFCODE_INDEX - hex - default 0x3 - -config MAINBOARD_DIR - string - default google/rikku - -config MAINBOARD_PART_NUMBER - string - default "Rikku" - -config IRQ_SLOT_COUNT - int - default 18 - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config MAINBOARD_FAMILY - string - depends on GENERATE_SMBIOS_TABLES - default "Google_Rikku" - -config GBB_HWID - string - depends on CHROMEOS - default "RIKKU TEST A-A 0702" - -endif diff --git a/src/mainboard/google/rikku/Kconfig.name b/src/mainboard/google/rikku/Kconfig.name deleted file mode 100644 index 00552d0..0000000 --- a/src/mainboard/google/rikku/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_RIKKU - bool "Rikku" diff --git a/src/mainboard/google/rikku/Makefile.inc b/src/mainboard/google/rikku/Makefile.inc deleted file mode 100644 index 552aa06..0000000 --- a/src/mainboard/google/rikku/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += lan.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -romstage-y += pei_data.c -ramstage-y += pei_data.c diff --git a/src/mainboard/google/rikku/acpi/ec.asl b/src/mainboard/google/rikku/acpi/ec.asl deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl b/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9..0000000 --- a/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/rikku/acpi/mainboard.asl b/src/mainboard/google/rikku/acpi/mainboard.asl deleted file mode 100644 index fefb7a6..0000000 --- a/src/mainboard/google/rikku/acpi/mainboard.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/rikku/onboard.h> - -Scope (\_SB) -{ - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } -} - -/* - * LAN connected to Root Port 3, becomes Root Port 1 after coalesce - */ -Scope (\_SB.PCI0.RP01) -{ - Device (ETH0) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { RIKKU_NIC_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (RIKKU_NIC_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (Local0) - } - } - } -} - -/* - * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce - */ -Scope (\_SB.PCI0.RP02) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { RIKKU_WLAN_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (RIKKU_WLAN_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (Local0) - } - } - } -} diff --git a/src/mainboard/google/rikku/acpi/platform.asl b/src/mainboard/google/rikku/acpi/platform.asl deleted file mode 100644 index 7ff90a8..0000000 --- a/src/mainboard/google/rikku/acpi/platform.asl +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Initialize thermal defaults */ - \_TZ.THRM._INI () - - Return(Package(){0,0}) -} diff --git a/src/mainboard/google/rikku/acpi/superio.asl b/src/mainboard/google/rikku/acpi/superio.asl deleted file mode 100644 index 9b71632..0000000 --- a/src/mainboard/google/rikku/acpi/superio.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Values should match those defined in devicetree.cb */ - -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR - -#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard -#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 - -#include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/google/rikku/acpi/thermal.asl b/src/mainboard/google/rikku/acpi/thermal.asl deleted file mode 100644 index 1d9ff08..0000000 --- a/src/mainboard/google/rikku/acpi/thermal.asl +++ /dev/null @@ -1,339 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../thermal.h" - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - // Start fan at state 4 = lowest temp state - Method (_INI) - { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - - Method (TCHK, 0, Serialized) - { - // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) - - // Check for "no reading available - If (LEqual (Local0, 0x80)) { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - - // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - - // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) - - // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { - Return (CTOK (\TMAX)) - } - - // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) - Return (CTOK (Local0)) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for SuperIO to re-poll - Sleep (1000) - - // Re-read temperature from SuperIO - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (FAN0_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN0_THRESHOLD_ON)) - } - } - - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (FAN1_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN1_THRESHOLD_ON)) - } - } - - Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { - Return (CTOK (FAN2_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN2_THRESHOLD_ON)) - } - } - - Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { - Return (CTOK (FAN3_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN3_THRESHOLD_ON)) - } - } - - Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { - Return (CTOK (FAN4_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN4_THRESHOLD_ON)) - } - } - - Name (_AL0, Package () { FAN0 }) - Name (_AL1, Package () { FAN1 }) - Name (_AL2, Package () { FAN2 }) - Name (_AL3, Package () { FAN3 }) - Name (_AL4, Package () { FAN4 }) - - PowerResource (FNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP2, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 2)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP3, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 3)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP4, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 4)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - Device (FAN0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { FNP0 }) - } - - Device (FAN1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { FNP1 }) - } - - Device (FAN2) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 2) - Name (_PR0, Package () { FNP2 }) - } - - Device (FAN3) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 3) - Name (_PR0, Package () { FNP3 }) - } - - Device (FAN4) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 4) - Name (_PR0, Package () { FNP4 }) - } - } -} diff --git a/src/mainboard/google/rikku/acpi/video.asl b/src/mainboard/google/rikku/acpi/video.asl deleted file mode 100644 index 6894655..0000000 --- a/src/mainboard/google/rikku/acpi/video.asl +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/google/rikku/acpi_tables.c b/src/mainboard/google/rikku/acpi_tables.c deleted file mode 100644 index 6626219..0000000 --- a/src/mainboard/google/rikku/acpi_tables.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/acpi.h> -#include <soc/nvs.h> -#include "thermal.h" - - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tmps = TEMPERATURE_SENSOR_ID; - - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 1; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} diff --git a/src/mainboard/google/rikku/board_info.txt b/src/mainboard/google/rikku/board_info.txt deleted file mode 100644 index f705964..0000000 --- a/src/mainboard/google/rikku/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Vendor name: Acer -Board name: Chromebox CXI2 -Category: half -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/rikku/chromeos.c b/src/mainboard/google/rikku/chromeos.c deleted file mode 100644 index b007484..0000000 --- a/src/mainboard/google/rikku/chromeos.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/sata.h> - -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 - -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 -#define FLAG_DEV_MODE 2 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, - {GPIO_REC_MODE, ACTIVE_LOW, - get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, 1, "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -#ifdef __PRE_RAM__ -void save_chromeos_gpios(void) -{ - u32 flags = 0; - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} -#endif - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/rikku/chromeos.fmd b/src/mainboard/google/rikku/chromeos.fmd deleted file mode 100644 index 113fba6..0000000 --- a/src/mainboard/google/rikku/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/google/rikku/cmos.layout b/src/mainboard/google/rikku/cmos.layout deleted file mode 100644 index c508d64..0000000 --- a/src/mainboard/google/rikku/cmos.layout +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/rikku/devicetree.cb b/src/mainboard/google/rikku/devicetree.cb deleted file mode 100644 index 34929a1..0000000 --- a/src/mainboard/google/rikku/devicetree.cb +++ /dev/null @@ -1,119 +0,0 @@ -chip soc/intel/broadwell - - # Disable eDP Hotplug - register "gpu_dp_d_hotplug" = "0x00" - - # Enable DisplayPort C Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Enable FAN2 - register "fan2_enable" = "1" - - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/rikku/dsdt.asl b/src/mainboard/google/rikku/dsdt.asl deleted file mode 100644 index edb04f0..0000000 --- a/src/mainboard/google/rikku/dsdt.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <soc/intel/broadwell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> - } - } - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/google/rikku/fadt.c b/src/mainboard/google/rikku/fadt.c deleted file mode 100644 index ace819d..0000000 --- a/src/mainboard/google/rikku/fadt.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <soc/acpi.h> -#include <cpu/x86/smm.h> -#include <soc/pch.h> -#include <soc/iomap.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = ACPI_BASE_ADDRESS; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/rikku/gpio.h b/src/mainboard/google/rikku/gpio.h deleted file mode 100644 index f58ad24..0000000 --- a/src/mainboard/google/rikku/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef RIKKU_GPIO_H -#define RIKKU_GPIO_H - -#include <soc/gpio.h> - -static const struct gpio_config mainboard_gpio_config[] = { - PCH_GPIO_UNUSED, /* 0: UNUSED */ - PCH_GPIO_UNUSED, /* 1: UNUSED */ - PCH_GPIO_UNUSED, /* 2: UNUSED */ - PCH_GPIO_UNUSED, /* 3: UNUSED */ - PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ - PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ - PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - PCH_GPIO_UNUSED, /* 11: SMBALERT */ - PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ - PCH_GPIO_UNUSED, /* 13: UNUSED */ - PCH_GPIO_UNUSED, /* 14: UNUSED */ - PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 16: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ - PCH_GPIO_UNUSED, /* 18: UNUSED */ - PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ - PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ - PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ - PCH_GPIO_UNUSED, /* 23: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ - PCH_GPIO_UNUSED, /* 25: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ - PCH_GPIO_UNUSED, /* 27: UNUSED */ - PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ - PCH_GPIO_UNUSED, /* 29: UNUSED */ - PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ - PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ - PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ - PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - PCH_GPIO_UNUSED, /* 37: UNUSED */ - PCH_GPIO_UNUSED, /* 38: UNUSED */ - PCH_GPIO_UNUSED, /* 39: UNUSED */ - PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ - PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ - PCH_GPIO_UNUSED, /* 44: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ - PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ - PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ - PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ - PCH_GPIO_UNUSED, /* 51: UNUSED */ - PCH_GPIO_UNUSED, /* 52: UNUSED */ - PCH_GPIO_UNUSED, /* 53: UNUSED */ - PCH_GPIO_UNUSED, /* 54: UNUSED */ - PCH_GPIO_UNUSED, /* 55: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ - PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ - PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ - PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ - PCH_GPIO_UNUSED, /* 61: UNUSED */ - PCH_GPIO_UNUSED, /* 62: UNUSED */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - PCH_GPIO_UNUSED, /* 64: UNUSED */ - PCH_GPIO_UNUSED, /* 65: UNUSED */ - PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 67: UNUSED */ - PCH_GPIO_UNUSED, /* 68: UNUSED */ - PCH_GPIO_UNUSED, /* 69: UNUSED */ - PCH_GPIO_UNUSED, /* 70: UNUSED */ - PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - PCH_GPIO_UNUSED, /* 72: UNUSED */ - PCH_GPIO_UNUSED, /* 73: UNUSED */ - PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - PCH_GPIO_UNUSED, /* 76: UNUSED */ - PCH_GPIO_UNUSED, /* 77: UNUSED */ - PCH_GPIO_UNUSED, /* 78: UNUSED */ - PCH_GPIO_UNUSED, /* 79: UNUSED */ - PCH_GPIO_UNUSED, /* 80: UNUSED */ - PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - PCH_GPIO_UNUSED, /* 83: UNUSED */ - PCH_GPIO_UNUSED, /* 84: UNUSED */ - PCH_GPIO_UNUSED, /* 85: UNUSED */ - PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 87: UNUSED */ - PCH_GPIO_UNUSED, /* 88: UNUSED */ - PCH_GPIO_UNUSED, /* 89: UNUSED */ - PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_UNUSED, /* 91: UNUSED */ - PCH_GPIO_UNUSED, /* 92: UNUSED */ - PCH_GPIO_UNUSED, /* 93: UNUSED */ - PCH_GPIO_UNUSED, /* 94: UNUSED */ - PCH_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/rikku/hda_verb.c b/src/mainboard/google/rikku/hda_verb.c deleted file mode 100644 index 284015d..0000000 --- a/src/mainboard/google/rikku/hda_verb.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 - 0x10ec0283, // Subsystem ID - 0x0000000c, // Number of jacks (NID entries) - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - 0x00172083, - 0x00172102, - 0x001722ec, - 0x00172310, - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) DMIC */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - - /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - 0x01471cf0, - 0x01471d11, - 0x01471e11, - 0x01471f40, - - /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, - - /* Pin Complex (NID 0x18) MIC1 PORTB */ - 0x01971c11, // group 1, cap 1 - 0x01971d10, // black, jack detect - 0x01971ea7, // mic in, analog - 0x01971f03, // connector, left panel - - /* Pin Complex (NID 0x19) MIC2 PORTF */ - 0x01871cf0, - 0x01871d11, - 0x01871e11, - 0x01871f41, - - /* Pin Complex (NID 0x1A) LINE1 PORTC */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1B) LINE2 PORTE */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1d) PCBeep */ - 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable - 0x01d71d81, // mute spkr on hpout - 0x01d71e15, // pcbeep en able, checksum - 0x01d71f40, // no physical, internal - - /* Pin Complex (NID 0x1E) SPDIF-OUT */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - - /* Pin Complex (NID 0x21) HPOUT PORT-I */ - 0x02171c1f, // group1, - 0x02171d10, // black, jack detect - 0x02171e21, // HPOut, 1/8 stereo - 0x02171f03, // connector, left panel - - /* Undocumented settings from Realtek (needed for beep_gen) */ - /* Widget node 0x20 */ - 0x02050010, - 0x02040c20, - 0x0205001b, - 0x0204081b, -}; - -const u32 pc_beep_verbs[] = { - 0x00170500, /* power up everything (codec, dac, adc, mixers) */ - 0x01470740, /* enable speaker out */ - 0x01470c02, /* set speaker EAPD pin */ - 0x0143b01f, /* unmute speaker */ - 0x00c37100, /* unmute mixer nid 0xc input 1 */ - 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ -}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c deleted file mode 100644 index 7d797c3..0000000 --- a/src/mainboard/google/rikku/lan.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <string.h> -#include <types.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <fmap.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "onboard.h" - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", - *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_DEBUG, - "Error: Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(RIKKU_NIC_VENDOR_ID, - RIKKU_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((RIKKU_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/rikku/mainboard.c b/src/mainboard/google/rikku/mainboard.c deleted file mode 100644 index 79c9711..0000000 --- a/src/mainboard/google/rikku/mainboard.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "onboard.h" - -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} - -static void mainboard_init(device_t dev) -{ - lan_init(); -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/rikku/onboard.h b/src/mainboard/google/rikku/onboard.h deleted file mode 100644 index 2711162..0000000 --- a/src/mainboard/google/rikku/onboard.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#ifndef __ACPI__ -void lan_init(void); -#endif - -/* defines for programming the MAC address */ -#define RIKKU_NIC_VENDOR_ID 0x10EC -#define RIKKU_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define RIKKU_NIC_LED_MODE 0x00 - -/* NIC wake is GPIO 8 */ -#define RIKKU_NIC_WAKE_GPIO 8 - -/* WLAN wake is GPIO 10 */ -#define RIKKU_WLAN_WAKE_GPIO 10 - -/* IT8772F defs */ -#define IT8772F_BASE 0x2e -#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) -#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) -#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) - -#endif diff --git a/src/mainboard/google/rikku/pei_data.c b/src/mainboard/google/rikku/pei_data.c deleted file mode 100644 index 4eeabbe..0000000 --- a/src/mainboard/google/rikku/pei_data.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - pei_data->ec_present = 0; - - /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, - USB_PORT_MINI_PCIE); - /* P1: Port A, CN22 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, - USB_PORT_INTERNAL); - /* P2: Port B, CN23 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, - USB_PORT_INTERNAL); - /* P3: WLAN */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_MINI_PCIE); - /* P4: Port C, CN25 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P5: Port D, CN25 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P7: EMPTY */ - pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, - USB_PORT_SKIP); - - /* P1: CN22 */ - pei_data_usb3_port(pei_data, 0, 1, 0, 0); - /* P2: CN23 */ - pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: CN25 */ - pei_data_usb3_port(pei_data, 2, 1, 2, 0); - /* P4: CN25 */ - pei_data_usb3_port(pei_data, 3, 1, 2, 0); -} diff --git a/src/mainboard/google/rikku/romstage.c b/src/mainboard/google/rikku/romstage.c deleted file mode 100644 index 5f06ed9..0000000 --- a/src/mainboard/google/rikku/romstage.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> -#include <mainboard/google/rikku/spd/spd.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8772f/it8772f.h> -#include "gpio.h" -#include "onboard.h" - -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data pei_data; - - post_code(0x32); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; - - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); -} - -void mainboard_pre_console_init(void) -{ - /* Early SuperIO setup */ - ite_kill_watchdog(IT8772F_GPIO_DEV); - it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); - ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Turn On GPIO10.LED */ - it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, - SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - -} diff --git a/src/mainboard/google/rikku/smihandler.c b/src/mainboard/google/rikku/smihandler.c deleted file mode 100644 index 4331a1f..0000000 --- a/src/mainboard/google/rikku/smihandler.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <elog.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <superio/ite/it8772f/it8772f.h> -#include "onboard.h" - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - return 1; -} - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x01 /* polarity */, 0x01 /* 1=pullup */, - 0x01 /* output */, 0x00, /* 0=Alternate function */ - SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - break; - case ACPI_S5: - it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, - SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - break; - default: - break; - } - return; -} - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - break; - case APM_CNT_ACPI_DISABLE: - break; - } - return 0; -} diff --git a/src/mainboard/google/rikku/spd/Makefile.inc b/src/mainboard/google/rikku/spd/Makefile.inc deleted file mode 100644 index 90f22d8..0000000 --- a/src/mainboard/google/rikku/spd/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c diff --git a/src/mainboard/google/rikku/spd/spd.c b/src/mainboard/google/rikku/spd/spd.c deleted file mode 100644 index 4366d8a..0000000 --- a/src/mainboard/google/rikku/spd/spd.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/pei_data.h> -#include <mainboard/google/rikku/spd/spd.h> - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - pei_data->spd_addresses[0] = 0xa0; - pei_data->spd_addresses[1] = 0x00; - pei_data->spd_addresses[2] = 0xa4; - pei_data->spd_addresses[3] = 0x00; - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; - // Enable 2x refresh mode - pei_data->ddr_refresh_2x = 1; - pei_data->dq_pins_interleaved = 1; -} diff --git a/src/mainboard/google/rikku/spd/spd.h b/src/mainboard/google/rikku/spd/spd.h deleted file mode 100644 index e48d93f..0000000 --- a/src/mainboard/google/rikku/spd/spd.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/rikku/thermal.h b/src/mainboard/google/rikku/thermal.h deleted file mode 100644 index 92e9b98..0000000 --- a/src/mainboard/google/rikku/thermal.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -#define TEMPERATURE_SENSOR_ID 0 /* PECI */ - -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x84 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 42 -#define FAN3_THRESHOLD_ON 47 -#define FAN3_PWM 0xa5 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 54 -#define FAN2_THRESHOLD_ON 59 -#define FAN2_PWM 0xb2 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 66 -#define FAN1_THRESHOLD_ON 71 -#define FAN1_PWM 0xc9 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 78 -#define FAN0_THRESHOLD_ON 83 -#define FAN0_PWM 0xd8 - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 - -#endif diff --git a/src/mainboard/google/tidus/Kconfig b/src/mainboard/google/tidus/Kconfig deleted file mode 100644 index 8d9b4860..0000000 --- a/src/mainboard/google/tidus/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -if BOARD_GOOGLE_TIDUS - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SOC_INTEL_BROADWELL - select BOARD_ROMSIZE_KB_8192 - select SUPERIO_ITE_IT8772F - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - select PHYSICAL_REC_SWITCH - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/tidus - -config MAINBOARD_PART_NUMBER - string - default "Tidus" - -config IRQ_SLOT_COUNT - int - default 18 - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - - -config MAINBOARD_FAMILY - string - depends on GENERATE_SMBIOS_TABLES - default "Google_Tidus" - -config GBB_HWID - string - depends on CHROMEOS - default "TIDUS TEST A-A 0595" -endif diff --git a/src/mainboard/google/tidus/Kconfig.name b/src/mainboard/google/tidus/Kconfig.name deleted file mode 100644 index f4f6943..0000000 --- a/src/mainboard/google/tidus/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_TIDUS - bool "Tidus" diff --git a/src/mainboard/google/tidus/Makefile.inc b/src/mainboard/google/tidus/Makefile.inc deleted file mode 100644 index d06150d..0000000 --- a/src/mainboard/google/tidus/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += lan.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c - -romstage-y += pei_data.c led.c -ramstage-y += pei_data.c diff --git a/src/mainboard/google/tidus/acpi/ec.asl b/src/mainboard/google/tidus/acpi/ec.asl deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/google/tidus/acpi/haswell_pci_irqs.asl b/src/mainboard/google/tidus/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9..0000000 --- a/src/mainboard/google/tidus/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/tidus/acpi/mainboard.asl b/src/mainboard/google/tidus/acpi/mainboard.asl deleted file mode 100644 index 31a6c95..0000000 --- a/src/mainboard/google/tidus/acpi/mainboard.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/tidus/onboard.h> - -Scope (\_SB) -{ - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } -} - -/* - * LAN connected to Root Port 3, becomes Root Port 1 after coalesce - */ -Scope (\_SB.PCI0.RP01) -{ - Device (ETH0) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { TIDUS_NIC_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (TIDUS_NIC_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (Local0) - } - } - } -} - -/* - * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce - */ -Scope (\_SB.PCI0.RP02) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { TIDUS_WLAN_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (TIDUS_WLAN_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (Local0) - } - } - } -} diff --git a/src/mainboard/google/tidus/acpi/platform.asl b/src/mainboard/google/tidus/acpi/platform.asl deleted file mode 100644 index 06de271..0000000 --- a/src/mainboard/google/tidus/acpi/platform.asl +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Initialize thermal defaults */ - \_TZ.THRM._INI () - - Return(Package(){0,0}) -} diff --git a/src/mainboard/google/tidus/acpi/superio.asl b/src/mainboard/google/tidus/acpi/superio.asl deleted file mode 100644 index 9b71632..0000000 --- a/src/mainboard/google/tidus/acpi/superio.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Values should match those defined in devicetree.cb */ - -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR - -#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard -#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 - -#include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/google/tidus/acpi/thermal.asl b/src/mainboard/google/tidus/acpi/thermal.asl deleted file mode 100644 index 78e7bf7..0000000 --- a/src/mainboard/google/tidus/acpi/thermal.asl +++ /dev/null @@ -1,447 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../thermal.h" - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - Name (F0ON, FAN0_2_THRESHOLD_ON) - Name (F0OF, FAN0_2_THRESHOLD_OFF) - Name (F0PW, FAN0_2_PWM) - Name (F1ON, FAN1_2_THRESHOLD_ON) - Name (F1OF, FAN1_2_THRESHOLD_OFF) - Name (F1PW, FAN1_2_PWM) - Name (F2ON, FAN2_2_THRESHOLD_ON) - Name (F2OF, FAN2_2_THRESHOLD_OFF) - Name (F2PW, FAN2_2_PWM) - Name (F3ON, FAN3_2_THRESHOLD_ON) - Name (F3OF, FAN3_2_THRESHOLD_OFF) - Name (F3PW, FAN3_2_PWM) - Name (F4PW, FAN4_2_PWM) - Name (THTB, 2) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Thermal Table 0 - Method (TTB0, 0) { - Store (FAN0_0_THRESHOLD_ON, F0ON) - Store (FAN0_0_THRESHOLD_OFF, F0OF) - Store (FAN0_0_PWM, F0PW) - Store (FAN1_0_THRESHOLD_ON, F1ON) - Store (FAN1_0_THRESHOLD_OFF, F1OF) - Store (FAN1_0_PWM, F1PW) - Store (FAN2_0_THRESHOLD_ON, F2ON) - Store (FAN2_0_THRESHOLD_OFF, F2OF) - Store (FAN2_0_PWM, F2PW) - Store (FAN3_0_THRESHOLD_ON, F3ON) - Store (FAN3_0_THRESHOLD_OFF, F3OF) - Store (FAN3_0_PWM, F3PW) - Store (FAN4_0_PWM, F4PW) - Store (0, THTB) - } - - // Thermal Table 1 - Method (TTB1, 0) { - Store (FAN0_1_THRESHOLD_ON, F0ON) - Store (FAN0_1_THRESHOLD_OFF, F0OF) - Store (FAN0_1_PWM, F0PW) - Store (FAN1_1_THRESHOLD_ON, F1ON) - Store (FAN1_1_THRESHOLD_OFF, F1OF) - Store (FAN1_1_PWM, F1PW) - Store (FAN2_1_THRESHOLD_ON, F2ON) - Store (FAN2_1_THRESHOLD_OFF, F2OF) - Store (FAN2_1_PWM, F2PW) - Store (FAN3_1_THRESHOLD_ON, F3ON) - Store (FAN3_1_THRESHOLD_OFF, F3OF) - Store (FAN3_1_PWM, F3PW) - Store (FAN4_1_PWM, F4PW) - Store (1, THTB) - } - - // Thermal Table 2 - Method (TTB2, 0) { - Store (FAN0_2_THRESHOLD_ON, F0ON) - Store (FAN0_2_THRESHOLD_OFF, F0OF) - Store (FAN0_2_PWM, F0PW) - Store (FAN1_2_THRESHOLD_ON, F1ON) - Store (FAN1_2_THRESHOLD_OFF, F1OF) - Store (FAN1_2_PWM, F1PW) - Store (FAN2_2_THRESHOLD_ON, F2ON) - Store (FAN2_2_THRESHOLD_OFF, F2OF) - Store (FAN2_2_PWM, F2PW) - Store (FAN3_2_THRESHOLD_ON, F3ON) - Store (FAN3_2_THRESHOLD_OFF, F3OF) - Store (FAN3_2_PWM, F3PW) - Store (FAN4_2_PWM, F4PW) - Store (2, THTB) - } - - // Update Thermal Table - Method (UPTB, 0) { - // Get System Temperature via SuperIO TMPIN2 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN2, Local0) - - // Check for "no reading available - If (LEqual (Local0, 0x80)) { - Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) - } - - // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) - } - - If (LEqual (THTB, 2)) { - If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { - TTB0 () - } ElseIf (LGreaterEqual (Local0, THERMAL_POLICY_1_THRESHOLD_ON)) { - TTB1 () - } - } ElseIf (LEqual (THTB, 1)) { - If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { - TTB0 () - } ElseIf (LLessEqual (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { - TTB2 () - } - } Else { - If (LLess (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { - TTB2 () - } ElseIf (LLessEqual (Local0, THERMAL_POLICY_0_THRESHOLD_OFF)) { - TTB1 () - } - } - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - // Start fan at state 4 = lowest temp state - Method (_INI) - { - Store (4, \FLVL) - Store (FAN4_2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - - Method (TCHK, 0, Serialized) - { - // Update Thermal Table - UPTB () - - // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) - - // Check for "no reading available - If (LEqual (Local0, 0x80)) { - Return (CTOK (FAN0_0_THRESHOLD_ON)) - } - - // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Return (CTOK (FAN0_0_THRESHOLD_ON)) - } - - // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) - - // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { - Return (CTOK (\TMAX)) - } - - // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) - Return (CTOK (Local0)) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for SuperIO to re-poll - Sleep (1000) - - // Re-read temperature from SuperIO - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (F0OF)) - } Else { - Return (CTOK (F0ON)) - } - } - - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (F1OF)) - } Else { - Return (CTOK (F1ON)) - } - } - - Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { - Return (CTOK (F2OF)) - } Else { - Return (CTOK (F2ON)) - } - } - - Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { - Return (CTOK (F3OF)) - } Else { - Return (CTOK (F3ON)) - } - } - - Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { - Return (CTOK (0)) - } Else { - Return (CTOK (0)) - } - } - - Name (_AL0, Package () { FAN0 }) - Name (_AL1, Package () { FAN1 }) - Name (_AL2, Package () { FAN2 }) - Name (_AL3, Package () { FAN3 }) - Name (_AL4, Package () { FAN4 }) - - PowerResource (FNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (F0PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (1, \FLVL) - Store (F1PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (F1PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (2, \FLVL) - Store (F2PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP2, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 2)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (F2PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (3, \FLVL) - Store (F3PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP3, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 3)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (F3PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP4, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 4)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - Device (FAN0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { FNP0 }) - } - - Device (FAN1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { FNP1 }) - } - - Device (FAN2) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 2) - Name (_PR0, Package () { FNP2 }) - } - - Device (FAN3) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 3) - Name (_PR0, Package () { FNP3 }) - } - - Device (FAN4) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 4) - Name (_PR0, Package () { FNP4 }) - } - } -} diff --git a/src/mainboard/google/tidus/acpi/video.asl b/src/mainboard/google/tidus/acpi/video.asl deleted file mode 100644 index 6894655..0000000 --- a/src/mainboard/google/tidus/acpi/video.asl +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/google/tidus/acpi_tables.c b/src/mainboard/google/tidus/acpi_tables.c deleted file mode 100644 index 0ee7934..0000000 --- a/src/mainboard/google/tidus/acpi_tables.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/acpi.h> -#include <soc/nvs.h> -#include "thermal.h" - - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 1; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - acpi_init_gnvs(gnvs); - - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} diff --git a/src/mainboard/google/tidus/board_info.txt b/src/mainboard/google/tidus/board_info.txt deleted file mode 100644 index a4e9890..0000000 --- a/src/mainboard/google/tidus/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Vendor name: Lenovo -Board name: ThinkCentre Chromebox -Category: half -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/tidus/chromeos.c b/src/mainboard/google/tidus/chromeos.c deleted file mode 100644 index 710ab48..0000000 --- a/src/mainboard/google/tidus/chromeos.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/sata.h> - -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 - -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 -#define FLAG_DEV_MODE 2 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, - {GPIO_REC_MODE, ACTIVE_LOW, - get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, 1, "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -#ifdef __PRE_RAM__ -void save_chromeos_gpios(void) -{ - u32 flags = 0; - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} -#endif - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/tidus/chromeos.fmd b/src/mainboard/google/tidus/chromeos.fmd deleted file mode 100644 index 113fba6..0000000 --- a/src/mainboard/google/tidus/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/google/tidus/cmos.layout b/src/mainboard/google/tidus/cmos.layout deleted file mode 100644 index c508d64..0000000 --- a/src/mainboard/google/tidus/cmos.layout +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/tidus/devicetree.cb b/src/mainboard/google/tidus/devicetree.cb deleted file mode 100644 index 73afdb3..0000000 --- a/src/mainboard/google/tidus/devicetree.cb +++ /dev/null @@ -1,125 +0,0 @@ -chip soc/intel/broadwell - - # Disable eDP Hotplug - register "gpu_dp_d_hotplug" = "0x00" - - # Enable DisplayPort C Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Enable Thermal Diode on TMPIN1 - register "tmpin1_mode" = "0" - # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" - # Enable FAN2 - register "fan2_enable" = "1" - # Default FAN2 speed - register "fan2_speed" = "0x4d" - - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/tidus/dsdt.asl b/src/mainboard/google/tidus/dsdt.asl deleted file mode 100644 index c3d1fc9..0000000 --- a/src/mainboard/google/tidus/dsdt.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <soc/intel/broadwell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> - } - } - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/google/tidus/fadt.c b/src/mainboard/google/tidus/fadt.c deleted file mode 100644 index c377d67..0000000 --- a/src/mainboard/google/tidus/fadt.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <soc/acpi.h> -#include <cpu/x86/smm.h> -#include <soc/pch.h> -#include <soc/iomap.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = ACPI_BASE_ADDRESS; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/tidus/gpio.h b/src/mainboard/google/tidus/gpio.h deleted file mode 100644 index 846fe81..0000000 --- a/src/mainboard/google/tidus/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef TIDUS_GPIO_H -#define TIDUS_GPIO_H - -#include <soc/gpio.h> - -static const struct gpio_config mainboard_gpio_config[] = { - PCH_GPIO_UNUSED, /* 0: UNUSED */ - PCH_GPIO_UNUSED, /* 1: UNUSED */ - PCH_GPIO_UNUSED, /* 2: UNUSED */ - PCH_GPIO_UNUSED, /* 3: UNUSED */ - PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ - PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ - PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - PCH_GPIO_UNUSED, /* 11: SMBALERT */ - PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ - PCH_GPIO_UNUSED, /* 13: UNUSED */ - PCH_GPIO_UNUSED, /* 14: UNUSED */ - PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 16: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ - PCH_GPIO_UNUSED, /* 18: UNUSED */ - PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ - PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ - PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ - PCH_GPIO_UNUSED, /* 23: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ - PCH_GPIO_UNUSED, /* 25: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ - PCH_GPIO_UNUSED, /* 27: UNUSED */ - PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ - PCH_GPIO_UNUSED, /* 29: UNUSED */ - PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ - PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ - PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ - PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - PCH_GPIO_UNUSED, /* 37: UNUSED */ - PCH_GPIO_UNUSED, /* 38: UNUSED */ - PCH_GPIO_UNUSED, /* 39: UNUSED */ - PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ - PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ - PCH_GPIO_UNUSED, /* 44: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ - PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ - PCH_GPIO_OUT_HIGH, /* 48: USB4_PWR_EN */ - PCH_GPIO_OUT_LOW, /* 49: POWER_LED */ - PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ - PCH_GPIO_UNUSED, /* 51: UNUSED */ - PCH_GPIO_UNUSED, /* 52: UNUSED */ - PCH_GPIO_UNUSED, /* 53: UNUSED */ - PCH_GPIO_UNUSED, /* 54: UNUSED */ - PCH_GPIO_UNUSED, /* 55: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ - PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ - PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ - PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ - PCH_GPIO_UNUSED, /* 61: UNUSED */ - PCH_GPIO_UNUSED, /* 62: UNUSED */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - PCH_GPIO_UNUSED, /* 64: UNUSED */ - PCH_GPIO_UNUSED, /* 65: UNUSED */ - PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 67: UNUSED */ - PCH_GPIO_UNUSED, /* 68: UNUSED */ - PCH_GPIO_UNUSED, /* 69: UNUSED */ - PCH_GPIO_UNUSED, /* 70: UNUSED */ - PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - PCH_GPIO_UNUSED, /* 72: UNUSED */ - PCH_GPIO_UNUSED, /* 73: UNUSED */ - PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - PCH_GPIO_UNUSED, /* 76: UNUSED */ - PCH_GPIO_UNUSED, /* 77: UNUSED */ - PCH_GPIO_UNUSED, /* 78: UNUSED */ - PCH_GPIO_UNUSED, /* 79: UNUSED */ - PCH_GPIO_UNUSED, /* 80: UNUSED */ - PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - PCH_GPIO_UNUSED, /* 83: UNUSED */ - PCH_GPIO_UNUSED, /* 84: UNUSED */ - PCH_GPIO_UNUSED, /* 85: UNUSED */ - PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 87: UNUSED */ - PCH_GPIO_UNUSED, /* 88: UNUSED */ - PCH_GPIO_UNUSED, /* 89: UNUSED */ - PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_UNUSED, /* 91: UNUSED */ - PCH_GPIO_UNUSED, /* 92: UNUSED */ - PCH_GPIO_UNUSED, /* 93: UNUSED */ - PCH_GPIO_UNUSED, /* 94: UNUSED */ - PCH_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/tidus/hda_verb.c b/src/mainboard/google/tidus/hda_verb.c deleted file mode 100644 index 284015d..0000000 --- a/src/mainboard/google/tidus/hda_verb.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 - 0x10ec0283, // Subsystem ID - 0x0000000c, // Number of jacks (NID entries) - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - 0x00172083, - 0x00172102, - 0x001722ec, - 0x00172310, - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) DMIC */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - - /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - 0x01471cf0, - 0x01471d11, - 0x01471e11, - 0x01471f40, - - /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, - - /* Pin Complex (NID 0x18) MIC1 PORTB */ - 0x01971c11, // group 1, cap 1 - 0x01971d10, // black, jack detect - 0x01971ea7, // mic in, analog - 0x01971f03, // connector, left panel - - /* Pin Complex (NID 0x19) MIC2 PORTF */ - 0x01871cf0, - 0x01871d11, - 0x01871e11, - 0x01871f41, - - /* Pin Complex (NID 0x1A) LINE1 PORTC */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1B) LINE2 PORTE */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1d) PCBeep */ - 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable - 0x01d71d81, // mute spkr on hpout - 0x01d71e15, // pcbeep en able, checksum - 0x01d71f40, // no physical, internal - - /* Pin Complex (NID 0x1E) SPDIF-OUT */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - - /* Pin Complex (NID 0x21) HPOUT PORT-I */ - 0x02171c1f, // group1, - 0x02171d10, // black, jack detect - 0x02171e21, // HPOut, 1/8 stereo - 0x02171f03, // connector, left panel - - /* Undocumented settings from Realtek (needed for beep_gen) */ - /* Widget node 0x20 */ - 0x02050010, - 0x02040c20, - 0x0205001b, - 0x0204081b, -}; - -const u32 pc_beep_verbs[] = { - 0x00170500, /* power up everything (codec, dac, adc, mixers) */ - 0x01470740, /* enable speaker out */ - 0x01470c02, /* set speaker EAPD pin */ - 0x0143b01f, /* unmute speaker */ - 0x00c37100, /* unmute mixer nid 0xc input 1 */ - 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ -}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/tidus/lan.c b/src/mainboard/google/tidus/lan.c deleted file mode 100644 index 6f965cf..0000000 --- a/src/mainboard/google/tidus/lan.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <string.h> -#include <types.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <fmap.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "onboard.h" - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", - *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_DEBUG, - "Error: Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(TIDUS_NIC_VENDOR_ID, - TIDUS_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((TIDUS_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/tidus/led.c b/src/mainboard/google/tidus/led.c deleted file mode 100644 index a21b3b5..0000000 --- a/src/mainboard/google/tidus/led.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <superio/ite/it8772f/it8772f.h> -#include "onboard.h" - -void set_power_led(int state) -{ - it8772f_gpio_led(IT8772F_GPIO_DEV, - 1, /* set */ - 0x01, /* select */ - state == LED_OFF ? 0x00 : 0x01, /* polarity */ - state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ - 0x01, /* output */ - state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ - SIO_GPIO_BLINK_GPIO10, - IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); -} diff --git a/src/mainboard/google/tidus/mainboard.c b/src/mainboard/google/tidus/mainboard.c deleted file mode 100644 index 7e57505..0000000 --- a/src/mainboard/google/tidus/mainboard.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "onboard.h" - -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} - -static void mainboard_init(device_t dev) -{ - lan_init(); -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/tidus/onboard.h b/src/mainboard/google/tidus/onboard.h deleted file mode 100644 index 6085c7d..0000000 --- a/src/mainboard/google/tidus/onboard.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#ifndef __ACPI__ -void lan_init(void); - -void set_power_led(int state); - -enum { - LED_OFF = 0, - LED_ON, - LED_BLINK, -}; -#endif - -/* defines for programming the MAC address */ -#define TIDUS_NIC_VENDOR_ID 0x10EC -#define TIDUS_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define TIDUS_NIC_LED_MODE 0x00 - -/* NIC wake is GPIO 8 */ -#define TIDUS_NIC_WAKE_GPIO 8 - -/* WLAN wake is GPIO 10 */ -#define TIDUS_WLAN_WAKE_GPIO 10 - -/* IT8772F defs */ -#define IT8772F_BASE 0x2e -#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) -#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) -#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) - -#endif diff --git a/src/mainboard/google/tidus/pei_data.c b/src/mainboard/google/tidus/pei_data.c deleted file mode 100644 index 7c03422..0000000 --- a/src/mainboard/google/tidus/pei_data.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - pei_data->ec_present = 0; - - /* P0: VP8 */ - pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP, - USB_PORT_MINI_PCIE); - /* P1: Port 3, USB3 */ - pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, - USB_PORT_INTERNAL); - /* P2: Port 4, USB4 */ - pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, - USB_PORT_INTERNAL); - /* P3: Mini Card */ - pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_MINI_PCIE); - /* P4: Port 1, USB1 */ - pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P5: Port 2, USB2 */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, - USB_PORT_INTERNAL); - /* P6: Card Reader */ - pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); - /* P7: Pin Header */ - pei_data_usb2_port(pei_data, 7, 0x0040, 1, 3, - USB_PORT_INTERNAL); - - /* P1: USB1 */ - pei_data_usb3_port(pei_data, 0, 1, 2, 0); - /* P2: USB2 */ - pei_data_usb3_port(pei_data, 1, 1, 2, 0); - /* P3: USB3 */ - pei_data_usb3_port(pei_data, 2, 1, 0, 0); - /* P4: USB4 */ - pei_data_usb3_port(pei_data, 3, 1, 1, 0); -} diff --git a/src/mainboard/google/tidus/romstage.c b/src/mainboard/google/tidus/romstage.c deleted file mode 100644 index 703eaea..0000000 --- a/src/mainboard/google/tidus/romstage.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> -#include <mainboard/google/tidus/spd/spd.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8772f/it8772f.h> -#include "gpio.h" -#include "onboard.h" - - -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data pei_data; - - post_code(0x32); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; - - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); -} - -void mainboard_pre_console_init(void) -{ - /* Early SuperIO setup */ - ite_kill_watchdog(IT8772F_GPIO_DEV); - it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); - ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Turn On GPIO10.LED */ - set_power_led(LED_ON); - -} diff --git a/src/mainboard/google/tidus/smihandler.c b/src/mainboard/google/tidus/smihandler.c deleted file mode 100644 index 6bd93d3..0000000 --- a/src/mainboard/google/tidus/smihandler.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <elog.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include "onboard.h" - -/* USB Charger Control: GPIO26 */ -#define GPIO_USB_CTL_1 26 - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - return 1; -} - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - set_power_led(LED_BLINK); - - /* Enable DCP mode */ - set_gpio(GPIO_USB_CTL_1, 0); - break; - case ACPI_S5: - set_power_led(LED_OFF); - break; - } -} - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - break; - case APM_CNT_ACPI_DISABLE: - break; - } - return 0; -} diff --git a/src/mainboard/google/tidus/spd/Makefile.inc b/src/mainboard/google/tidus/spd/Makefile.inc deleted file mode 100644 index 275d983..0000000 --- a/src/mainboard/google/tidus/spd/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c diff --git a/src/mainboard/google/tidus/spd/spd.c b/src/mainboard/google/tidus/spd/spd.c deleted file mode 100644 index bf5bda0..0000000 --- a/src/mainboard/google/tidus/spd/spd.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/pei_data.h> -#include <mainboard/google/tidus/spd/spd.h> - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - pei_data->spd_addresses[0] = 0xa0; - pei_data->spd_addresses[1] = 0x00; - pei_data->spd_addresses[2] = 0xa4; - pei_data->spd_addresses[3] = 0x00; - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; - // Enable 2x refresh mode - pei_data->ddr_refresh_2x = 1; - pei_data->dq_pins_interleaved = 1; -} diff --git a/src/mainboard/google/tidus/spd/spd.h b/src/mainboard/google/tidus/spd/spd.h deleted file mode 100644 index 02709cd..0000000 --- a/src/mainboard/google/tidus/spd/spd.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/tidus/thermal.h b/src/mainboard/google/tidus/thermal.h deleted file mode 100644 index 31e416f..0000000 --- a/src/mainboard/google/tidus/thermal.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -/* Thermal Policy 0 */ -/* Fan is at default speed */ -#define FAN4_0_PWM 0x4d - -/* Fan is at LOW speed */ -#define FAN3_0_THRESHOLD_OFF 62 -#define FAN3_0_THRESHOLD_ON 70 -#define FAN3_0_PWM 0x5e - -/* Fan is at MEDIUM speed */ -#define FAN2_0_THRESHOLD_OFF 68 -#define FAN2_0_THRESHOLD_ON 81 -#define FAN2_0_PWM 0x78 - -/* Fan is at HIGH speed */ -#define FAN1_0_THRESHOLD_OFF 78 -#define FAN1_0_THRESHOLD_ON 91 -#define FAN1_0_PWM 0x93 - -/* Fan is at FULL speed */ -#define FAN0_0_THRESHOLD_OFF 88 -#define FAN0_0_THRESHOLD_ON 100 -#define FAN0_0_PWM 0xb0 - -/* Thermal Policy 1 */ -/* Fan is at default speed */ -#define FAN4_1_PWM 0x4d - -/* Fan is at LOW speed */ -#define FAN3_1_THRESHOLD_OFF 62 -#define FAN3_1_THRESHOLD_ON 70 -#define FAN3_1_PWM 0x5e - -/* Fan is at MEDIUM speed */ -#define FAN2_1_THRESHOLD_OFF 68 -#define FAN2_1_THRESHOLD_ON 81 -#define FAN2_1_PWM 0x70 - -/* Fan is at HIGH speed */ -#define FAN1_1_THRESHOLD_OFF 78 -#define FAN1_1_THRESHOLD_ON 91 -#define FAN1_1_PWM 0x83 - -/* Fan is at FULL speed */ -#define FAN0_1_THRESHOLD_OFF 88 -#define FAN0_1_THRESHOLD_ON 100 -#define FAN0_1_PWM 0x93 - -/* Thermal Policy 2 */ -/* Fan is at default speed */ -#define FAN4_2_PWM 0x4d - -/* Fan is at LOW speed */ -#define FAN3_2_THRESHOLD_OFF 62 -#define FAN3_2_THRESHOLD_ON 70 -#define FAN3_2_PWM 0x59 - -/* Fan is at MEDIUM speed */ -#define FAN2_2_THRESHOLD_OFF 68 -#define FAN2_2_THRESHOLD_ON 81 -#define FAN2_2_PWM 0x63 - -/* Fan is at HIGH speed */ -#define FAN1_2_THRESHOLD_OFF 78 -#define FAN1_2_THRESHOLD_ON 91 -#define FAN1_2_PWM 0x6e - -/* Fan is at FULL speed */ -#define FAN0_2_THRESHOLD_OFF 88 -#define FAN0_2_THRESHOLD_ON 100 -#define FAN0_2_PWM 0x7e - -/* Threshold to change thermal policy */ -#define THERMAL_POLICY_0_THRESHOLD_OFF 38 -#define THERMAL_POLICY_0_THRESHOLD_ON 40 - -#define THERMAL_POLICY_1_THRESHOLD_OFF 33 -#define THERMAL_POLICY_1_THRESHOLD_ON 35 - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 103 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 105 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 105 - -#endif

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coreboot-gerrit December 2016