Patch set updated for coreboot: drivers/intel/gma: Add textmode support with libgfxinit
by Nico Huber 19 Dec '16
by Nico Huber 19 Dec '16
19 Dec '16
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17279
-gerrit
commit 221655cde6a537e9994a6ea214ae009462517fb3
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Nov 7 17:24:47 2016 +0100
drivers/intel/gma: Add textmode support with libgfxinit
Add an alternative gfxinit implementation for textmode. The legacy VGA
plane and textmode is configured through coreboot provided functions.
libgfxinit uses this plane as alternative to the usual high resolution
plane.
Change-Id: Iad0754c50fc6faec35f49583fe1c7cb50ac6c0c5
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/device/Kconfig | 1 +
src/drivers/intel/gma/Makefile.inc | 6 +-
src/drivers/intel/gma/gma.adb | 117 ---------------------------------
src/drivers/intel/gma/hires_fb/gma.adb | 117 +++++++++++++++++++++++++++++++++
src/drivers/intel/gma/text_fb/gma.adb | 75 +++++++++++++++++++++
5 files changed, 198 insertions(+), 118 deletions(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index d238547..c90da89 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -53,6 +53,7 @@ config MAINBOARD_USE_LIBGFXINIT
bool "Use libgfxinit for native graphics initialization"
depends on MAINBOARD_DO_NATIVE_VGA_INIT
depends on MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select RAMSTAGE_LIBHWBASE
default n
help
diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc
index a4e007c..d4d6c08 100644
--- a/src/drivers/intel/gma/Makefile.inc
+++ b/src/drivers/intel/gma/Makefile.inc
@@ -40,6 +40,10 @@ CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime
subdirs-y += ../../../../3rdparty/libgfxinit
ramstage-y += gma.ads
-ramstage-y += gma.adb
+ifeq ($(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE),y)
+ramstage-y += hires_fb/gma.adb
+else
+ramstage-y += text_fb/gma.adb
+endif
endif # CONFIG_MAINBOARD_USE_LIBGFXINIT
diff --git a/src/drivers/intel/gma/gma.adb b/src/drivers/intel/gma/gma.adb
deleted file mode 100644
index 7ebc4f8..0000000
--- a/src/drivers/intel/gma/gma.adb
+++ /dev/null
@@ -1,117 +0,0 @@
-with HW.GFX;
-with HW.GFX.Framebuffer_Filler;
-with HW.GFX.GMA;
-
-use HW.GFX;
-use HW.GFX.GMA;
-
-with GMA.Mainboard;
-
-package body GMA
-is
-
- vbe_valid : boolean := false;
-
- linear_fb_addr : word64;
-
- fb : Framebuffer_Type;
-
- function vbe_mode_info_valid return Interfaces.C.int
- is
- begin
- return (if vbe_valid then 1 else 0);
- end vbe_mode_info_valid;
-
- procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer)
- is
- use type word32;
- begin
- framebuffer :=
- (tag => 0,
- size => 0,
- physical_address => linear_fb_addr,
- x_resolution => word32 (fb.Width),
- y_resolution => word32 (fb.Height),
- bytes_per_line => 4 * word32 (fb.Stride),
- bits_per_pixel => 32,
- reserved_mask_pos => 24,
- reserved_mask_size => 8,
- red_mask_pos => 16,
- red_mask_size => 8,
- green_mask_pos => 8,
- green_mask_size => 8,
- blue_mask_pos => 0,
- blue_mask_size => 8);
- end fill_lb_framebuffer;
-
- ----------------------------------------------------------------------------
-
- procedure gfxinit
- (mmio_base : in word64;
- linear_fb : in word64;
- phys_fb : in word32;
- lightup_ok : out Interfaces.C.int)
- is
- use type pos32;
-
- ports : Port_List;
- configs : Configs_Type;
-
- success : boolean;
-
- stride : Width_Type;
- max_h : pos16 := 1;
- max_v : pos16 := 1;
- begin
- lightup_ok := 0;
-
- HW.GFX.GMA.Initialize
- (MMIO_Base => mmio_base,
- Success => success);
-
- if success then
- ports := Mainboard.ports;
- HW.GFX.GMA.Scan_Ports (configs, ports);
-
- if configs (Primary).Port /= Disabled then
- for i in Config_Index loop
- exit when configs (i).Port = Disabled;
-
- max_h := pos16'max (max_h, configs (i).Mode.H_Visible);
- max_v := pos16'max (max_v, configs (i).Mode.V_Visible);
- end loop;
-
- stride := ((Width_Type (max_h) + 63) / 64) * 64;
- for i in Config_Index loop
- exit when configs (i).Port = Disabled;
-
- configs (i).Framebuffer :=
- (Width => Width_Type (configs (i).Mode.H_Visible),
- Height => Height_Type (configs (i).Mode.V_Visible),
- BPC => 8,
- Stride => stride,
- Offset => 0);
- end loop;
-
- HW.GFX.GMA.Dump_Configs (configs);
-
- fb :=
- (Width => Width_Type (max_h),
- Height => Height_Type (max_v),
- BPC => 8,
- Stride => stride,
- Offset => 0);
- HW.GFX.GMA.Setup_Default_GTT (fb, phys_fb);
- HW.GFX.Framebuffer_Filler.Fill (linear_fb, fb);
-
- HW.GFX.GMA.Update_Outputs (configs);
-
- linear_fb_addr := linear_fb;
- vbe_valid := true;
-
- lightup_ok := 1;
- end if;
- end if;
- end gfxinit;
-
-end GMA;
diff --git a/src/drivers/intel/gma/hires_fb/gma.adb b/src/drivers/intel/gma/hires_fb/gma.adb
new file mode 100644
index 0000000..7ebc4f8
--- /dev/null
+++ b/src/drivers/intel/gma/hires_fb/gma.adb
@@ -0,0 +1,117 @@
+with HW.GFX;
+with HW.GFX.Framebuffer_Filler;
+with HW.GFX.GMA;
+
+use HW.GFX;
+use HW.GFX.GMA;
+
+with GMA.Mainboard;
+
+package body GMA
+is
+
+ vbe_valid : boolean := false;
+
+ linear_fb_addr : word64;
+
+ fb : Framebuffer_Type;
+
+ function vbe_mode_info_valid return Interfaces.C.int
+ is
+ begin
+ return (if vbe_valid then 1 else 0);
+ end vbe_mode_info_valid;
+
+ procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer)
+ is
+ use type word32;
+ begin
+ framebuffer :=
+ (tag => 0,
+ size => 0,
+ physical_address => linear_fb_addr,
+ x_resolution => word32 (fb.Width),
+ y_resolution => word32 (fb.Height),
+ bytes_per_line => 4 * word32 (fb.Stride),
+ bits_per_pixel => 32,
+ reserved_mask_pos => 24,
+ reserved_mask_size => 8,
+ red_mask_pos => 16,
+ red_mask_size => 8,
+ green_mask_pos => 8,
+ green_mask_size => 8,
+ blue_mask_pos => 0,
+ blue_mask_size => 8);
+ end fill_lb_framebuffer;
+
+ ----------------------------------------------------------------------------
+
+ procedure gfxinit
+ (mmio_base : in word64;
+ linear_fb : in word64;
+ phys_fb : in word32;
+ lightup_ok : out Interfaces.C.int)
+ is
+ use type pos32;
+
+ ports : Port_List;
+ configs : Configs_Type;
+
+ success : boolean;
+
+ stride : Width_Type;
+ max_h : pos16 := 1;
+ max_v : pos16 := 1;
+ begin
+ lightup_ok := 0;
+
+ HW.GFX.GMA.Initialize
+ (MMIO_Base => mmio_base,
+ Success => success);
+
+ if success then
+ ports := Mainboard.ports;
+ HW.GFX.GMA.Scan_Ports (configs, ports);
+
+ if configs (Primary).Port /= Disabled then
+ for i in Config_Index loop
+ exit when configs (i).Port = Disabled;
+
+ max_h := pos16'max (max_h, configs (i).Mode.H_Visible);
+ max_v := pos16'max (max_v, configs (i).Mode.V_Visible);
+ end loop;
+
+ stride := ((Width_Type (max_h) + 63) / 64) * 64;
+ for i in Config_Index loop
+ exit when configs (i).Port = Disabled;
+
+ configs (i).Framebuffer :=
+ (Width => Width_Type (configs (i).Mode.H_Visible),
+ Height => Height_Type (configs (i).Mode.V_Visible),
+ BPC => 8,
+ Stride => stride,
+ Offset => 0);
+ end loop;
+
+ HW.GFX.GMA.Dump_Configs (configs);
+
+ fb :=
+ (Width => Width_Type (max_h),
+ Height => Height_Type (max_v),
+ BPC => 8,
+ Stride => stride,
+ Offset => 0);
+ HW.GFX.GMA.Setup_Default_GTT (fb, phys_fb);
+ HW.GFX.Framebuffer_Filler.Fill (linear_fb, fb);
+
+ HW.GFX.GMA.Update_Outputs (configs);
+
+ linear_fb_addr := linear_fb;
+ vbe_valid := true;
+
+ lightup_ok := 1;
+ end if;
+ end if;
+ end gfxinit;
+
+end GMA;
diff --git a/src/drivers/intel/gma/text_fb/gma.adb b/src/drivers/intel/gma/text_fb/gma.adb
new file mode 100644
index 0000000..bbb6d74
--- /dev/null
+++ b/src/drivers/intel/gma/text_fb/gma.adb
@@ -0,0 +1,75 @@
+with HW.GFX;
+with HW.GFX.GMA;
+
+use HW.GFX;
+use HW.GFX.GMA;
+
+with GMA.Mainboard;
+
+package body GMA
+is
+
+ function vbe_mode_info_valid return Interfaces.C.int
+ is
+ begin
+ return 0;
+ end vbe_mode_info_valid;
+
+ procedure fill_lb_framebuffer (framebuffer : out lb_framebuffer)
+ is
+ begin
+ null;
+ end fill_lb_framebuffer;
+
+ ----------------------------------------------------------------------------
+
+ procedure gfxinit
+ (mmio_base : in word64;
+ linear_fb : in word64;
+ phys_fb : in word32;
+ lightup_ok : out Interfaces.C.int)
+ is
+ ports : Port_List;
+ configs : Configs_Type;
+
+ success : boolean;
+
+ -- from pc80/vga driver
+ procedure vga_io_init;
+ pragma Import (C, vga_io_init, "vga_io_init");
+ procedure vga_textmode_init;
+ pragma Import (C, vga_textmode_init, "vga_textmode_init");
+ begin
+ lightup_ok := 0;
+
+ HW.GFX.GMA.Initialize
+ (MMIO_Base => mmio_base,
+ Success => success);
+
+ if success then
+ ports := Mainboard.ports;
+ HW.GFX.GMA.Scan_Ports
+ (Configs => configs,
+ Ports => ports,
+ Max_Pipe => Primary);
+
+ if configs (Primary).Port /= Disabled then
+ vga_io_init;
+ vga_textmode_init;
+
+ configs (Primary).Framebuffer :=
+ (Width => 640,
+ Height => 400,
+ BPC => Auto_BPC, -- ignored for VGA plane
+ Stride => 320, -- ignored
+ Offset => VGA_PLANE_FRAMEBUFFER_OFFSET);
+
+ HW.GFX.GMA.Dump_Configs (configs);
+ HW.GFX.GMA.Update_Outputs (configs);
+
+ lightup_ok := 1;
+ end if;
+ end if;
+ end gfxinit;
+
+end GMA;
1
0
Patch set updated for coreboot: skylake: Restore target offset value after exiting from S3
by Sumeet R Pawnikar 19 Dec '16
by Sumeet R Pawnikar 19 Dec '16
19 Dec '16
Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17889
-gerrit
commit dd905e347a245dcc42683734ee0ae0e70ae888b9
Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Date: Thu Dec 15 19:29:51 2016 +0530
skylake: Restore target offset value after exiting from S3
Before entering in S3, the target offset value is 10 degree C.
After exiting from S3, Coreboot is not restoring the target offset value
and it is setting it to the default value as 0.
With the default target offset value as 0 and target temperature Tjmax
value as 100 degree C, Pcode firmware starts taking prochot action at
100 degree C [Tjmax-Offset].
But before Pcode firmware starts prochot action at 100 degree C, device
is getting shutdown at 99 degree C due to DPTF critical CPU temperature
after exiting from S3.
So, this patch restores the target offset value after exiting from S3.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built for skylake platform and verified the target offset value
before and after S3.
Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
src/mainboard/google/chell/devicetree.cb | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 34250d3..2ffaec6 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -183,6 +183,8 @@ chip soc/intel/skylake
# PL2 override 15W
register "tdp_pl2_override" = "15"
+ register "tcc_offset" = "10" # TCC of 90C
+
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
1
0
Patch merged into coreboot/master: pcengines/apu2: add board support
by gerritï¼ coreboot.org 19 Dec '16
by gerritï¼ coreboot.org 19 Dec '16
19 Dec '16
the following patch was just integrated into master:
commit dcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5
Author: Piotr Król <piotr.krol(a)3mdeb.com>
Date: Fri May 27 12:04:13 2016 +0200
pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.
Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.
memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.
SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872
SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.
Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu…
Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See https://review.coreboot.org/14138 for details.
-gerrit
1
0
19 Dec '16
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17558
-gerrit
commit 82ef454e8ed238a287fa3087b7fe50451babb68c
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Mon Nov 21 17:11:48 2016 +0100
mb/asus/p5gc-mx: Add mainboard
Tested to work:
* GPU (Nvidia gt210) in PCIe x16 slot;
* SATA;
* serial;
* 800MHz and 1067MHz FSB Core 2 Duo CPUs;
* ethernet;
* native VGA graphic init.
What does not work:
* resume from s3 suspend;
* superio hardware monitor (not initialised in coreboot).
Quirks:
* does not boot with just one dimm in slot B.
Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/mainboard/asus/p5gc-mx/Kconfig | 57 +++++
src/mainboard/asus/p5gc-mx/Kconfig.name | 2 +
src/mainboard/asus/p5gc-mx/Makefile.inc | 1 +
src/mainboard/asus/p5gc-mx/acpi/ec.asl | 51 ++++
src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl | 75 ++++++
src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl | 46 ++++
src/mainboard/asus/p5gc-mx/acpi/mainboard.asl | 30 +++
src/mainboard/asus/p5gc-mx/acpi/platform.asl | 48 ++++
src/mainboard/asus/p5gc-mx/acpi/superio.asl | 1 +
src/mainboard/asus/p5gc-mx/acpi/thermal.asl | 1 +
src/mainboard/asus/p5gc-mx/acpi_tables.c | 32 +++
src/mainboard/asus/p5gc-mx/board_info.txt | 6 +
src/mainboard/asus/p5gc-mx/cmos.default | 7 +
src/mainboard/asus/p5gc-mx/cmos.layout | 97 ++++++++
src/mainboard/asus/p5gc-mx/cstates.c | 20 ++
src/mainboard/asus/p5gc-mx/devicetree.cb | 124 ++++++++++
src/mainboard/asus/p5gc-mx/dsdt.asl | 53 +++++
src/mainboard/asus/p5gc-mx/hda_verb.c | 40 ++++
src/mainboard/asus/p5gc-mx/romstage.c | 275 ++++++++++++++++++++++
19 files changed, 966 insertions(+)
diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig
new file mode 100644
index 0000000..0a32ac4
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/Kconfig
@@ -0,0 +1,57 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans <arthur(a)ahemans.xyz
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+if BOARD_ASUS_P5GC_MX
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ select CHECK_SLFRCS_ON_RESUME
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627DHG
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ select CHANNEL_XOR_RANDOMIZATION
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_EDID
+
+config MAINBOARD_DIR
+ string
+ default asus/p5gc-mx
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P5GC-MX"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 2
+
+endif # BOARD_ASUS_P5GC_MX
diff --git a/src/mainboard/asus/p5gc-mx/Kconfig.name b/src/mainboard/asus/p5gc-mx/Kconfig.name
new file mode 100644
index 0000000..a325f58
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_P5GC_MX
+ bool "P5GC-MX"
diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc
new file mode 100644
index 0000000..f9621db
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += cstates.c
diff --git a/src/mainboard/asus/p5gc-mx/acpi/ec.asl b/src/mainboard/asus/p5gc-mx/acpi/ec.asl
new file mode 100644
index 0000000..5362bb2
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/ec.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ // _REG method requires that an operation region be defined.
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000
+ // for EC initialization before a driver
+ // is loaded
+ }
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+
+ // TODO EC Query methods
+
+ // TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000..4aaa33f
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 16 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 16 },
+ Package() { 0x001cffff, 1, 0, 17 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 16 },
+ Package() { 0x001dffff, 1, 0, 17 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 19 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 16 },
+ Package() { 0x001fffff, 1, 0, 17 },
+ Package() { 0x001fffff, 2, 0, 18 },
+ Package() { 0x001fffff, 3, 0, 19 },
+
+ })
+
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..84d2a2f
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+
+If (PICM) {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x15 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x16 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 },
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 },
+
+ })
+} Else {
+ Return (Package() {
+ Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ })
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl
new file mode 100644
index 0000000..0454c3f
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (SLPB)
+{
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/platform.asl b/src/mainboard/asus/p5gc-mx/acpi/platform.asl
new file mode 100644
index 0000000..21eb3df
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/platform.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/asus/p5gc-mx/acpi/superio.asl b/src/mainboard/asus/p5gc-mx/acpi/superio.asl
new file mode 100644
index 0000000..4107d3b
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/acpi/thermal.asl b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl
new file mode 100644
index 0000000..4107d3b
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl
@@ -0,0 +1 @@
+/* dummy */
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c
new file mode 100644
index 0000000..677ebcf
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <arch/ioapic.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/asus/p5gc-mx/board_info.txt b/src/mainboard/asus/p5gc-mx/board_info.txt
new file mode 100644
index 0000000..c661268
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/P5GCMX/
+Release year: 2007
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default
new file mode 100644
index 0000000..ab7aac1
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+baud_rate=115200
+debug_level=Spew
+hyper_threading=Enable
+nmi=Enable
+boot_devices=''
+gfx_uma_size=8M
\ No newline at end of file
diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout
new file mode 100644
index 0000000..eaf51bb
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/cmos.layout
@@ -0,0 +1,97 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+# -----------------------------------------------------------------
+entries
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+
+# coreboot config options: northbridge
+411 3 e 11 gfx_uma_size
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 80 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# RAM initialization internal data
+1024 8 r 0 C0WL0REOST
+1032 8 r 0 C1WL0REOST
+1040 8 r 0 RCVENMT
+1048 4 r 0 C0DRT1
+1052 4 r 0 C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+11 0 1M
+11 1 4M
+11 2 8M
+11 3 16M
+11 4 32M
+11 5 48M
+11 6 64M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c
new file mode 100644
index 0000000..f683756
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/cstates.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
new file mode 100644
index 0000000..d04b42a
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -0,0 +1,124 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/i945
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x
+ device lapic 0xACAC off end
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on # host bridge
+ subsystemid 0x1458 0x5000
+ end
+ device pci 01.0 on # i945 PCIe root port
+ subsystemid 0x1458 0x5000
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 02.0 on # vga controller
+ subsystemid 0x1458 0xd000
+ ioapic_irq 2 INTA 0x10
+ end
+
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x86"
+ register "pirqd_routing" = "0x85"
+ register "pirqe_routing" = "0x83"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x85"
+
+ register "gpe0_en" = "0"
+
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+
+ register "p_cnt_throttling_supported" = "0"
+
+ device pci 1b.0 on # High Definition Audio
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ #device pci 1c.2 off end # PCIe port 3
+ #device pci 1c.3 off end # PCIe port 4
+ #device pci 1c.4 off end # PCIe port 5
+ #device pci 1c.5 off end # PCIe port 6
+ device pci 1d.0 on # USB UHCI
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1d.1 on # USB UHCI
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1d.2 on # USB UHCI
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1d.3 on # USB UHCI
+ ioapic_irq 2 INTD 0x13
+ end
+ device pci 1d.7 on # USB2 EHCI
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1e.0 on end # PCI bridge
+
+ device pci 1f.0 on # LPC bridge
+ ioapic_irq 2 INTA 0x10
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ irq 0x74 = 2
+ irq 0xf0 = 0x3a
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0xf0 = 0x83
+ end
+ end
+ device pci 1f.1 on # IDE
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1f.2 on # SATA
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1f.3 on # SMBus
+ ioapic_irq 2 INTD 0x13
+ end
+ end
+ end
+end
diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl
new file mode 100644
index 0000000..187481a
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ // Thermal Zone
+ //#include "acpi/thermal.asl"
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/i945/acpi/i945.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c
new file mode 100644
index 0000000..a9c25f3
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/hda_verb.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0883, /* Vendor ID */
+ 0x104382c7, /* Subsystem ID */
+ 0x0000000c, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19850),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
+ AZALIA_PIN_CFG(0, 0x1e, 0x18561130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
new file mode 100644
index 0000000..bcb7148
--- /dev/null
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz
+ * Copyright (C) 2016 Kyösti Mälkki <kyosti.malkki(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <halt.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <arch/cpu.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
+
+void setup_ich7_gpios(void)
+{
+ /* TODO: This is highly board specific and should be moved */
+ printk(BIOS_DEBUG, " GPIOS...");
+ /* General Registers */
+ outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ /* Output Control Registers */
+ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
+ /* Input Control Registers */
+ outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+ outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+ outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
+}
+
+/*
+ * BSEL0 is connected with GPIO32
+ * BSEL1 is connected with GPIO33 with inversed logic
+ * BSEL2 is connected with GPIO55
+ */
+static void setup_sio_gpio(u8 bsel)
+{
+ int need_reset = 0;
+ u8 reg, old_reg;
+
+ pnp_enter_ext_func_mode(GPIO_DEV);
+ pnp_set_logical_device(GPIO_DEV);
+
+ reg = 0x9a;
+ old_reg = pnp_read_config(GPIO_DEV, 0x2c);
+ pnp_write_config(GPIO_DEV, 0x2c, reg);
+ need_reset = (reg != old_reg);
+
+ pnp_write_config(GPIO_DEV, 0x30, 0x0e);
+ pnp_write_config(GPIO_DEV, 0xe0, 0xde);
+ pnp_write_config(GPIO_DEV, 0xf0, 0xf3);
+ pnp_write_config(GPIO_DEV, 0xf4, 0x80);
+ pnp_write_config(GPIO_DEV, 0xf5, 0x80);
+
+ /* Invert GPIO33 */
+ pnp_write_config(GPIO_DEV, 0xf2, 0x08);
+
+ reg = (bsel & 3) << 2;
+ old_reg = pnp_read_config(GPIO_DEV, 0xf1);
+ pnp_write_config(GPIO_DEV, 0xf1, reg);
+ need_reset += ((reg & 0xc) != (old_reg & 0xc));
+
+ reg = (bsel >> 2) << 5;
+ old_reg = pnp_read_config(GPIO_DEV, 0xe1);
+ pnp_write_config(GPIO_DEV, 0xe1, reg);
+ need_reset += ((reg & 0x20) != (old_reg & 0x20));
+
+ pnp_exit_ext_func_mode(GPIO_DEV);
+
+ if (need_reset) {
+ int i = 1000;
+ while (i--)
+ outb(i & 0xff, 0x80);
+ outb(0xe, 0xcf9);
+ halt();
+ }
+}
+
+static u8 msr_get_fsb(void)
+{
+ u8 fsbcfg;
+ msr_t msr;
+ const u32 eax = cpuid_eax(1);
+
+ /* Netburst */
+ if (((eax >> 8) & 0xf) == 0xf) {
+ msr = rdmsr(0x2c);
+ fsbcfg = (msr.lo >> 16) & 0x7;
+ } else { /* Intel Core 2 */
+ msr = rdmsr(MSR_FSB_FREQ);
+ fsbcfg = msr.lo & 0x7;
+ }
+
+ return fsbcfg;
+}
+
+static void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ // Set COM1/COM2 decode range
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ // Enable COM1
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d);
+ // Enable SuperIO Power Management Events
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
+
+ /* range 0x15e0 - 0x10ef */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291);
+
+
+}
+
+static void rcba_config(void)
+{
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+
+ /* Disable unused devices */
+ RCBA32(0x3418) = 0x003c0061;
+
+ /* Enable PCIe Root Port Clock Gate */
+ RCBA32(0x341c) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030509;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ int s3resume = 0, boot_mode = 0;
+
+ u8 m_bsel;
+ u8 c_bsel = msr_get_fsb();
+
+ if (bist == 0)
+ enable_lapic();
+
+ ich7_enable_lpc();
+
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ setup_sio_gpio(c_bsel);
+
+ /* Set up the console */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected.\n");
+ boot_mode = 1;
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ i945_early_initialization();
+
+ m_bsel = MCHBAR32(CLKCFG) & 7;
+ printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel);
+ if (c_bsel != m_bsel) { /* Should not happen */
+ printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n");
+ outb(0xe, 0xcf9);
+ halt();
+ }
+
+ s3resume = southbridge_detect_s3_resume();
+
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+ dump_spd_registers();
+#endif
+ sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+
+ /* Perform some initialization that must run before stage2 */
+ early_ich7_init();
+
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+
+ /* Chipset Errata! */
+ fixup_i945_errata();
+
+ /* Initialize the internal PCIe links before we go into stage2 */
+ i945_late_initialization(s3resume);
+}
1
0
New patch to review for coreboot: aopen/dxplplusu: Switch to 2MiB flash
by Kyösti Mälkki 19 Dec '16
by Kyösti Mälkki 19 Dec '16
19 Dec '16
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17919
-gerrit
commit 89cd7df26e21b2a0d85a65409f316ee2103de843
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Dec 4 15:39:56 2016 +0200
aopen/dxplplusu: Switch to 2MiB flash
Change-Id: Iedc15823dc24b3211fe7954cdf4302934a517afb
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/aopen/dxplplusu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig
index b64ac1d..0823161 100644
--- a/src/mainboard/aopen/dxplplusu/Kconfig
+++ b/src/mainboard/aopen/dxplplusu/Kconfig
@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# select PIRQ_ROUTE
select UDELAY_TSC
select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
+ select BOARD_ROMSIZE_KB_2048
# select HW_SCRUBBER
config MAINBOARD_DIR
1
0
New patch to review for coreboot: intel/i82801dx: Support 2MiB FWH part
by Kyösti Mälkki 19 Dec '16
by Kyösti Mälkki 19 Dec '16
19 Dec '16
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17918
-gerrit
commit 98dab0a55cedf0e1895dfc847083fadcc54dc00c
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Dec 4 15:39:44 2016 +0200
intel/i82801dx: Support 2MiB FWH part
Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.
Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/southbridge/intel/i82801dx/Kconfig | 4 ++++
src/southbridge/intel/i82801dx/bootblock.c | 21 +++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index af8300e..82db1c3 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -29,4 +29,8 @@ config EHCI_BAR
hex
default 0xfef00000
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/intel/i82801dx/bootblock.c"
+
endif
diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c
new file mode 100644
index 0000000..8ae419d
--- /dev/null
+++ b/src/southbridge/intel/i82801dx/bootblock.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+static void bootblock_southbridge_init(void)
+{
+ /* Set FWH IDs for 2 MB flash part. */
+ if (CONFIG_ROM_SIZE == 0x200000)
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);
+}
1
0
Patch merged into coreboot/master: amd/gardenia: Add AHB bridge registers in ACPI
by gerritï¼ coreboot.org 19 Dec '16
by gerritï¼ coreboot.org 19 Dec '16
19 Dec '16
the following patch was just integrated into master:
commit cff3b095c2fdb7af7b6fb0a1e09c2a66c1ad1c67
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Wed Oct 19 19:28:15 2016 -0400
amd/gardenia: Add AHB bridge registers in ACPI
Add the region used by the A-Link to AHB configuration registers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705
and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b)
Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17848
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17848 for details.
-gerrit
1
0
Patch merged into coreboot/master: amd/gardenia: Add I2C devices to ACPI
by gerritï¼ coreboot.org 19 Dec '16
by gerritï¼ coreboot.org 19 Dec '16
19 Dec '16
the following patch was just integrated into master:
commit 0fc64ac441082c7ac3ee1916254a8637644f1ca5
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Wed Oct 19 18:32:27 2016 -0400
amd/gardenia: Add I2C devices to ACPI
Add the missing two I2C controllers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d)
Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17847 for details.
-gerrit
1
0
Patch merged into coreboot/master: amd/gardenia: Clean up GPIO ASL
by gerritï¼ coreboot.org 19 Dec '16
by gerritï¼ coreboot.org 19 Dec '16
19 Dec '16
the following patch was just integrated into master:
commit 3c6c299493a8fc01aac83990afef9793f1d6bdf5
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Thu Oct 20 12:43:15 2016 -0400
amd/gardenia: Clean up GPIO ASL
Remove the unused Name field. Its previous design generates an FWTS
error and a recommendation for changing it to Serialized.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0)
Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17846 for details.
-gerrit
1
0
Patch set updated for coreboot: Add/Combine Broadwell Chromebooks using variant board scheme
by Matt DeVillier 19 Dec '16
by Matt DeVillier 19 Dec '16
19 Dec '16
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17917
-gerrit
commit 7d70ace4cede6994c7e11b9377dbe211b42e1fd1
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Sun Dec 18 11:59:58 2016 -0600
Add/Combine Broadwell Chromebooks using variant board scheme
Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.
Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use level (vs edge) interrupt triggering
- HDA verb entries use simplified macro entry format
- correct FADT table header version
- remove unused ACPI device entries / .asl file(s)
- clean up ACPI code (e.g., trackpad on Lulu)
- adjust _CID for trackpad on Lulu in order to not load non-functional
Windows driver (does not affect Linux)
- remove unused header includes (multiple/various)
- correct I2C addresses used for SMBIOS device entries
- correct misc typos etc
The existing auron_paine samus boards are removed.
Variant setup modeled after google/slippy
Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/auron/Kconfig | 65 ++--
src/mainboard/google/auron/Kconfig.name | 21 +-
src/mainboard/google/auron/Makefile.inc | 19 +-
.../google/auron/acpi/haswell_pci_irqs.asl | 82 -----
src/mainboard/google/auron/acpi/mainboard.asl | 243 +-------------
src/mainboard/google/auron/acpi/platform.asl | 82 -----
src/mainboard/google/auron/acpi/thermal.asl | 5 +-
src/mainboard/google/auron/acpi_tables.c | 14 +-
src/mainboard/google/auron/devicetree.cb | 108 ------
src/mainboard/google/auron/ec.h | 4 +-
src/mainboard/google/auron/fadt.c | 2 +-
src/mainboard/google/auron/gpio.h | 120 -------
src/mainboard/google/auron/hda_verb.c | 107 +-----
src/mainboard/google/auron/mainboard.c | 55 +---
src/mainboard/google/auron/onboard.h | 37 ---
src/mainboard/google/auron/pei_data.c | 63 ----
src/mainboard/google/auron/romstage.c | 9 +-
src/mainboard/google/auron/smihandler.c | 29 +-
.../google/auron/spd/Elpida_EDJ4216EFBG.spd.hex | 17 -
.../google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 -
src/mainboard/google/auron/spd/Makefile.inc | 42 ---
.../google/auron/spd/Micron_4KTF25664HZ.spd.hex | 17 -
src/mainboard/google/auron/spd/empty.spd.hex | 16 -
src/mainboard/google/auron/spd/spd.c | 132 --------
src/mainboard/google/auron/spd/spd.h | 39 ---
src/mainboard/google/auron/thermal.h | 35 --
src/mainboard/google/auron/variant.h | 23 ++
.../auron/variants/auron_paine/devicetree.cb | 108 ++++++
.../auron_paine/include/variant/acpi/mainboard.asl | 64 ++++
.../variants/auron_paine/include/variant/gpio.h | 120 +++++++
.../auron_paine/include/variant/hda_verb.h | 112 +++++++
.../variants/auron_paine/include/variant/onboard.h | 29 ++
.../variants/auron_paine/include/variant/spd.h | 39 +++
.../variants/auron_paine/include/variant/thermal.h | 35 ++
.../google/auron/variants/auron_paine/pei_data.c | 63 ++++
.../auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 +
.../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 17 +
.../auron/variants/auron_paine/spd/Makefile.inc | 50 +++
.../auron_paine/spd/Micron_4KTF25664HZ.spd.hex | 17 +
.../auron/variants/auron_paine/spd/empty.spd.hex | 16 +
.../google/auron/variants/auron_paine/spd/spd.c | 132 ++++++++
.../google/auron/variants/auron_paine/variant.c | 39 +++
.../google/auron/variants/auron_yuna/devicetree.cb | 108 ++++++
.../auron_yuna/include/variant/acpi/mainboard.asl | 64 ++++
.../variants/auron_yuna/include/variant/gpio.h | 120 +++++++
.../variants/auron_yuna/include/variant/hda_verb.h | 133 ++++++++
.../variants/auron_yuna/include/variant/onboard.h | 29 ++
.../variants/auron_yuna/include/variant/spd.h | 39 +++
.../variants/auron_yuna/include/variant/thermal.h | 35 ++
.../google/auron/variants/auron_yuna/pei_data.c | 63 ++++
.../auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 +
.../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 17 +
.../auron/variants/auron_yuna/spd/Makefile.inc | 50 +++
.../auron_yuna/spd/Micron_4KTF25664HZ.spd.hex | 17 +
.../auron/variants/auron_yuna/spd/empty.spd.hex | 16 +
.../google/auron/variants/auron_yuna/spd/spd.c | 132 ++++++++
.../google/auron/variants/auron_yuna/variant.c | 39 +++
.../google/auron/variants/gandof/devicetree.cb | 108 ++++++
.../gandof/include/variant/acpi/mainboard.asl | 64 ++++
.../auron/variants/gandof/include/variant/gpio.h | 120 +++++++
.../variants/gandof/include/variant/hda_verb.h | 112 +++++++
.../variants/gandof/include/variant/onboard.h | 29 ++
.../auron/variants/gandof/include/variant/spd.h | 39 +++
.../variants/gandof/include/variant/thermal.h | 35 ++
.../google/auron/variants/gandof/pei_data.c | 63 ++++
.../gandof/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 +
.../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 17 +
.../google/auron/variants/gandof/spd/Makefile.inc | 42 +++
.../variants/gandof/spd/Micron_4KTF25664HZ.spd.hex | 17 +
.../gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex | 17 +
.../google/auron/variants/gandof/spd/empty.spd.hex | 16 +
.../google/auron/variants/gandof/spd/spd.c | 132 ++++++++
.../google/auron/variants/gandof/variant.c | 39 +++
.../google/auron/variants/lulu/devicetree.cb | 110 +++++++
.../lulu/include/variant/acpi/mainboard.asl | 138 ++++++++
.../auron/variants/lulu/include/variant/gpio.h | 121 +++++++
.../auron/variants/lulu/include/variant/hda_verb.h | 112 +++++++
.../auron/variants/lulu/include/variant/onboard.h | 35 ++
.../auron/variants/lulu/include/variant/spd.h | 41 +++
.../auron/variants/lulu/include/variant/thermal.h | 35 ++
.../google/auron/variants/lulu/pei_data.c | 63 ++++
.../google/auron/variants/lulu/spd/Makefile.inc | 51 +++
.../google/auron/variants/lulu/spd/empty.spd.hex | 16 +
.../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 ++
.../spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex | 33 ++
.../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 ++
.../micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex | 33 ++
.../spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex | 17 +
.../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 17 +
.../spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex | 17 +
src/mainboard/google/auron/variants/lulu/spd/spd.c | 139 ++++++++
src/mainboard/google/auron/variants/lulu/variant.c | 48 +++
.../google/auron/variants/samus/Makefile.inc | 15 +
.../google/auron/variants/samus/board_version.c | 33 ++
.../google/auron/variants/samus/devicetree.cb | 112 +++++++
.../samus/include/variant/acpi/mainboard.asl | 247 ++++++++++++++
.../variants/samus/include/variant/board_version.h | 26 ++
.../auron/variants/samus/include/variant/gpio.h | 120 +++++++
.../variants/samus/include/variant/hda_verb.h | 20 ++
.../auron/variants/samus/include/variant/onboard.h | 32 ++
.../auron/variants/samus/include/variant/spd.h | 40 +++
.../auron/variants/samus/include/variant/thermal.h | 30 ++
.../google/auron/variants/samus/pei_data.c | 77 +++++
.../google/auron/variants/samus/spd/Makefile.inc | 50 +++
.../auron/variants/samus/spd/elpida_16.spd.hex | 18 +
.../auron/variants/samus/spd/elpida_4.spd.hex | 16 +
.../auron/variants/samus/spd/elpida_8.spd.hex | 16 +
.../google/auron/variants/samus/spd/empty.spd.hex | 16 +
.../auron/variants/samus/spd/hynix_16.spd.hex | 18 +
.../auron/variants/samus/spd/hynix_4.spd.hex | 18 +
.../auron/variants/samus/spd/hynix_8.spd.hex | 18 +
.../auron/variants/samus/spd/samsung_4.spd.hex | 16 +
.../auron/variants/samus/spd/samsung_8.spd.hex | 16 +
.../google/auron/variants/samus/spd/spd.c | 127 +++++++
.../google/auron/variants/samus/variant.c | 51 +++
src/mainboard/google/auron_paine/Kconfig | 65 ----
src/mainboard/google/auron_paine/Kconfig.name | 2 -
src/mainboard/google/auron_paine/Makefile.inc | 27 --
src/mainboard/google/auron_paine/acpi/ec.asl | 20 --
.../google/auron_paine/acpi/haswell_pci_irqs.asl | 82 -----
.../google/auron_paine/acpi/mainboard.asl | 118 -------
src/mainboard/google/auron_paine/acpi/platform.asl | 82 -----
src/mainboard/google/auron_paine/acpi/superio.asl | 25 --
src/mainboard/google/auron_paine/acpi/thermal.asl | 201 ------------
src/mainboard/google/auron_paine/acpi/video.asl | 38 ---
src/mainboard/google/auron_paine/acpi_tables.c | 66 ----
src/mainboard/google/auron_paine/board_info.txt | 6 -
src/mainboard/google/auron_paine/chromeos.c | 53 ---
src/mainboard/google/auron_paine/chromeos.fmd | 38 ---
src/mainboard/google/auron_paine/cmos.layout | 110 -------
src/mainboard/google/auron_paine/devicetree.cb | 108 ------
src/mainboard/google/auron_paine/dsdt.asl | 57 ----
src/mainboard/google/auron_paine/ec.c | 49 ---
src/mainboard/google/auron_paine/ec.h | 58 ----
src/mainboard/google/auron_paine/fadt.c | 47 ---
src/mainboard/google/auron_paine/gpio.h | 120 -------
src/mainboard/google/auron_paine/hda_verb.c | 119 -------
src/mainboard/google/auron_paine/mainboard.c | 73 -----
src/mainboard/google/auron_paine/onboard.h | 26 --
src/mainboard/google/auron_paine/pei_data.c | 63 ----
src/mainboard/google/auron_paine/romstage.c | 48 ---
src/mainboard/google/auron_paine/smihandler.c | 134 --------
.../auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd | 16 -
.../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd | 16 -
src/mainboard/google/auron_paine/spd/Makefile.inc | 53 ---
.../auron_paine/spd/Micron_4KTF25664HZ.spd.xxd | 16 -
src/mainboard/google/auron_paine/spd/empty.spd.xxd | 16 -
src/mainboard/google/auron_paine/spd/spd.c | 132 --------
src/mainboard/google/auron_paine/spd/spd.h | 39 ---
src/mainboard/google/auron_paine/thermal.h | 35 --
src/mainboard/google/samus/Kconfig | 64 ----
src/mainboard/google/samus/Kconfig.name | 2 -
src/mainboard/google/samus/Makefile.inc | 29 --
src/mainboard/google/samus/acpi/ec.asl | 29 --
src/mainboard/google/samus/acpi/mainboard.asl | 363 ---------------------
src/mainboard/google/samus/acpi/superio.asl | 25 --
src/mainboard/google/samus/acpi/thermal.asl | 118 -------
src/mainboard/google/samus/acpi_tables.c | 57 ----
src/mainboard/google/samus/board_info.txt | 3 -
src/mainboard/google/samus/board_version.c | 33 --
src/mainboard/google/samus/board_version.h | 26 --
src/mainboard/google/samus/chromeos.c | 54 ---
src/mainboard/google/samus/chromeos.fmd | 38 ---
src/mainboard/google/samus/cmos.layout | 110 -------
src/mainboard/google/samus/devicetree.cb | 112 -------
src/mainboard/google/samus/dsdt.asl | 57 ----
src/mainboard/google/samus/ec.c | 47 ---
src/mainboard/google/samus/ec.h | 61 ----
src/mainboard/google/samus/fadt.c | 47 ---
src/mainboard/google/samus/gpio.h | 125 -------
src/mainboard/google/samus/hda_verb.c | 20 --
src/mainboard/google/samus/mainboard.c | 61 ----
src/mainboard/google/samus/pei_data.c | 77 -----
src/mainboard/google/samus/romstage.c | 67 ----
src/mainboard/google/samus/smihandler.c | 134 --------
src/mainboard/google/samus/spd/Makefile.inc | 50 ---
src/mainboard/google/samus/spd/elpida_16.spd.hex | 18 -
src/mainboard/google/samus/spd/elpida_4.spd.hex | 16 -
src/mainboard/google/samus/spd/elpida_8.spd.hex | 16 -
src/mainboard/google/samus/spd/empty.spd.hex | 16 -
src/mainboard/google/samus/spd/hynix_16.spd.hex | 18 -
src/mainboard/google/samus/spd/hynix_4.spd.hex | 18 -
src/mainboard/google/samus/spd/hynix_8.spd.hex | 18 -
src/mainboard/google/samus/spd/samsung_4.spd.hex | 16 -
src/mainboard/google/samus/spd/samsung_8.spd.hex | 16 -
src/mainboard/google/samus/spd/spd.c | 127 -------
src/mainboard/google/samus/spd/spd.h | 40 ---
src/mainboard/google/samus/thermal.h | 30 --
188 files changed, 4963 insertions(+), 5582 deletions(-)
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 9eda101..00b4be8 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -1,7 +1,6 @@
-if BOARD_GOOGLE_AURON
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
+config BOARD_GOOGLE_BASEBOARD_AURON
+ def_bool n
select SOC_INTEL_BROADWELL
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
@@ -13,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
+if BOARD_GOOGLE_BASEBOARD_AURON
+
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -25,13 +26,46 @@ config MAINBOARD_DIR
string
default google/auron
+config VARIANT_DIR
+ string
+ default "auron_paine" if BOARD_GOOGLE_AURON_PAINE
+ default "auron_yuna" if BOARD_GOOGLE_AURON_YUNA
+ default "gandof" if BOARD_GOOGLE_GANDOF
+ default "lulu" if BOARD_GOOGLE_LULU
+ default "samus" if BOARD_GOOGLE_SAMUS
+
config MAINBOARD_PART_NUMBER
string
- default "Auron"
+ default "Auron_Paine" if BOARD_GOOGLE_AURON_PAINE
+ default "Auron_Yuna" if BOARD_GOOGLE_AURON_YUNA
+ default "Gandof" if BOARD_GOOGLE_GANDOF
+ default "Lulu" if BOARD_GOOGLE_LULU
+ default "Samus" if BOARD_GOOGLE_SAMUS
-config IRQ_SLOT_COUNT
- int
- default 18
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "PAINE TEST A-A 8843" if BOARD_GOOGLE_AURON_PAINE
+ default "YUNA TEST A-A 3347" if BOARD_GOOGLE_AURON_YUNA
+ default "GANDOF TEST A-A 7705" if BOARD_GOOGLE_GANDOF
+ default "LULU TEST A-A 7705" if BOARD_GOOGLE_LULU
+ default "SAMUS TEST 8028" if BOARD_GOOGLE_SAMUS
+
+config DEVICETREE
+ string
+ default "variants/auron_paine/devicetree.cb" if BOARD_GOOGLE_AURON_PAINE
+ default "variants/auron_yuna/devicetree.cb" if BOARD_GOOGLE_AURON_YUNA
+ default "variants/gandof/devicetree.cb" if BOARD_GOOGLE_GANDOF
+ default "variants/lulu/devicetree.cb" if BOARD_GOOGLE_LULU
+ default "variants/samus/devicetree.cb" if BOARD_GOOGLE_SAMUS
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ string
+ default "auron" if BOARD_GOOGLE_AURON_PAINE
+ default "auron" if BOARD_GOOGLE_AURON_YUNA
+ default "" if BOARD_GOOGLE_GANDOF
+ default "" if BOARD_GOOGLE_LULU
+ default "samus" if BOARD_GOOGLE_SAMUS
config MAX_CPUS
int
@@ -39,7 +73,7 @@ config MAX_CPUS
config VGA_BIOS_FILE
string
- default "pci8086,0166.rom"
+ default "pci8086,0406.rom"
config HAVE_IFD_BIN
bool
@@ -49,19 +83,4 @@ config HAVE_ME_BIN
bool
default n
-
-config MAINBOARD_FAMILY
- string
- depends on GENERATE_SMBIOS_TABLES
- default "Google_Auron"
-
-config EC_GOOGLE_CHROMEEC_BOARDNAME
- string
- default "auron"
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "AURON TEST A-A 9944"
-
endif
diff --git a/src/mainboard/google/auron/Kconfig.name b/src/mainboard/google/auron/Kconfig.name
index e996627..45edff0 100644
--- a/src/mainboard/google/auron/Kconfig.name
+++ b/src/mainboard/google/auron/Kconfig.name
@@ -1,2 +1,19 @@
-config BOARD_GOOGLE_AURON
- bool "Auron"
+config BOARD_GOOGLE_AURON_PAINE
+ bool "Auron_Paine"
+ select BOARD_GOOGLE_BASEBOARD_AURON
+
+config BOARD_GOOGLE_AURON_YUNA
+ bool "Auron_Yuna"
+ select BOARD_GOOGLE_BASEBOARD_AURON
+
+config BOARD_GOOGLE_GANDOF
+ bool "Gandof"
+ select BOARD_GOOGLE_BASEBOARD_AURON
+
+config BOARD_GOOGLE_LULU
+ bool "Lulu"
+ select BOARD_GOOGLE_BASEBOARD_AURON
+
+config BOARD_GOOGLE_SAMUS
+ bool "Samus"
+ select BOARD_GOOGLE_BASEBOARD_AURON
diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc
index 3a2ab77..1773514 100644
--- a/src/mainboard/google/auron/Makefile.inc
+++ b/src/mainboard/google/auron/Makefile.inc
@@ -13,15 +13,20 @@
## GNU General Public License for more details.
##
-subdirs-y += spd
-
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-romstage-y += chromeos.c
-ramstage-y += chromeos.c
-
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += pei_data.c
-ramstage-y += pei_data.c
+romstage-y += variants/$(VARIANT_DIR)/pei_data.c
+ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
+
+romstage-y += variants/$(VARIANT_DIR)/variant.c
+ramstage-y += variants/$(VARIANT_DIR)/variant.c
+
+subdirs-y += variants/$(VARIANT_DIR)
+subdirs-y += variants/$(VARIANT_DIR)/spd
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
\ No newline at end of file
diff --git a/src/mainboard/google/auron/acpi/haswell_pci_irqs.asl b/src/mainboard/google/auron/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index 40658a9..0000000
--- a/src/mainboard/google/auron/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 18 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 22 },
- Package() { 0x001fffff, 1, 0, 18 },
- Package() { 0x001fffff, 2, 0, 17 },
- Package() { 0x001fffff, 3, 0, 16 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, 0, 20 },
- Package() { 0x0015ffff, 1, 0, 21 },
- Package() { 0x0015ffff, 2, 0, 21 },
- Package() { 0x0015ffff, 3, 0, 21 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, 0, 23 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl
index 2e4352e..c5b9a83 100644
--- a/src/mainboard/google/auron/acpi/mainboard.asl
+++ b/src/mainboard/google/auron/acpi/mainboard.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#include <mainboard/google/auron/onboard.h>
+#include <variant/onboard.h>
Scope (\_SB)
{
@@ -27,7 +27,6 @@ Scope (\_SB)
Return (\LIDS)
}
-
// There is no GPIO for LID, the EC pulses WAKE# pin instead.
// There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
@@ -43,236 +42,8 @@ Scope (\_SB)
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
- {
- #include <drivers/pc80/tpm/acpi/tpm.asl>
-}
-
-Scope (\_SB.PCI0.I2C0)
{
- Device (ETPA)
- {
- Name (_HID, "ELAN0000")
- Name (_DDN, "Elan Touchpad")
- Name (_UID, 1)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x15, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TRACKPAD_IRQ
- }
- })
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
- }
- }
-
- /* Allow device to power off in S0 */
- Name (_S0W, 4)
- }
-
- Device (CTPA)
- {
- Name (_HID, "CYAP0000")
- Name (_DDN, "Cypress Touchpad")
- Name (_UID, 3)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x67, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TRACKPAD_IRQ
- }
- })
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
- }
- }
-
- /* Allow device to power off in S0 */
- Name (_S0W, 4)
- }
-
- Device (CTPB)
- {
- Name (_HID, "CYAP0001")
- Name (_DDN, "Cypress Touchpad")
- Name (_UID, 3)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x24, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TRACKPAD_IRQ
- }
- })
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
- }
- }
-
- /* Allow device to power off in S0 */
- Name (_S0W, 4)
- }
-}
-Scope (\_SB.PCI0.I2C1)
-{
- Device (ATSA)
- {
- Name (_HID, "ATML0001")
- Name (_DDN, "Atmel Touchscreen")
- Name (_UID, 5)
- Name (_S0W, 4)
- Name (ISTP, 0) /* TouchScreen */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x4a, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C1", // ResourceSource
- )
-
- // GPIO54 (ball L3) is PIRQW: PIRQL_GSI + PIRQL - PIRQW = PIRQW_GSI
- // 27 + 3 - 14 = 38
- Interrupt (ResourceConsumer, Edge, ActiveLow) { 38 }
- })
-
- Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
- }
- }
-
- Method (_STA)
- {
- If (LEqual (\S2EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
-
- Device (ALSI)
- {
- /*
- * TODO(dlaurie): Need official HID.
- *
- * The current HID is created from the Intersil PNP
- * Vendor ID "LSD" and a shortened device identifier.
- */
- Name (_HID, EisaId ("LSD2918"))
- Name (_DDN, "Intersil 29018 Ambient Light Sensor")
- Name (_UID, 6)
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x44, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.I2C1", // ResourceSource
- )
-
- // On Auron/Peppy board, IRQ is hooked to GPIO 51.
- // Based on table 5-36, this is PIRQT. Then based on
- // table 5-12, this is IRQ #35.
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- 35
- }
- })
-
- Method (_STA)
- {
- If (LEqual (\S2EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
}
Scope (\_SB.PCI0.RP01)
@@ -281,17 +52,17 @@ Scope (\_SB.PCI0.RP01)
{
Name (_ADR, 0x00000000)
- /* GPIO10 is WLAN_WAKE_L_Q */
- Name (GPIO, 10)
-
- Name (_PRW, Package() { GPIO, 3 })
+ Name (_PRW, Package() { BOARD_WLAN_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
+ Store (BOARD_WLAN_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
}
}
+
+#include <variant/acpi/mainboard.asl>
diff --git a/src/mainboard/google/auron/acpi/platform.asl b/src/mainboard/google/auron/acpi/platform.asl
deleted file mode 100644
index 1bd054d..0000000
--- a/src/mainboard/google/auron/acpi/platform.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
- APMC, 8, // APM command
- APMS, 8 // APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
- DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) // SMI Function
- Store (0, TRP0) // Generate trap
- Return (SMIF) // Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
- // Remember the OS' IRQ routing choice.
- Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- /* Update AC status */
- Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
- if (LNotEqual (Local0, \PWRS)) {
- Store (Local0, \PWRS)
- Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
- }
-
- /* Update LID status */
- Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
- if (LNotEqual (Local0, \LIDS)) {
- Store (Local0, \LIDS)
- Notify (\_SB.LID0, 0x80)
- }
-
- Return(Package(){0,0})
-}
diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl
index 872f6af..8c05549 100644
--- a/src/mainboard/google/auron/acpi/thermal.asl
+++ b/src/mainboard/google/auron/acpi/thermal.asl
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include <mainboard/google/auron/thermal.h>
+#include <variant/thermal.h>
// Thermal Zone
@@ -116,7 +116,7 @@ Scope (\_TZ)
Return (Local0)
}
-
+#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_SAMUS)
/* CTDP Down */
Method (_AC0) {
If (LLessEqual (\FLVL, 0)) {
@@ -197,5 +197,6 @@ Scope (\_TZ)
Name (_UID, 1)
Name (_PR0, Package () { TNP1 })
}
+#endif
}
}
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c
index 9583d11..4bb0239 100644
--- a/src/mainboard/google/auron/acpi_tables.c
+++ b/src/mainboard/google/auron/acpi_tables.c
@@ -13,27 +13,15 @@
* GNU General Public License for more details.
*/
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
-#include "thermal.h"
-
-extern const unsigned char AmlCode[];
+#include <variant/thermal.h>
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->tmps = CTL_TDP_SENSOR_ID;
-
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tmax = MAX_TEMPERATURE;
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
deleted file mode 100644
index 77e71b8..0000000
--- a/src/mainboard/google/auron/devicetree.cb
+++ /dev/null
@@ -1,108 +0,0 @@
-chip soc/intel/broadwell
-
- # Enable eDP Hotplug with 6ms pulse
- register "gpu_dp_d_hotplug" = "0x06"
-
- # Disable DisplayPort C Hotplug
- register "gpu_dp_c_hotplug" = "0x00"
-
- # Enable HDMI Hotplug with 6ms pulse
- register "gpu_dp_b_hotplug" = "0x06"
-
- # Set backlight PWM values for eDP
- register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000000"
-
- # Enable Panel and configure power delays
- register "gpu_panel_port_select" = "1" # eDP
- register "gpu_panel_power_cycle_delay" = "5" # 400ms
- register "gpu_panel_power_up_delay" = "400" # 40ms
- register "gpu_panel_power_down_delay" = "150" # 15ms
- register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
- register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
-
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
-
- register "sata_port_map" = "0x1"
- register "sio_acpi_mode" = "1"
-
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
-
- # Force enable ASPM for PCIe Port1
- register "pcie_port_force_aspm" = "0x01"
-
- # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013c0000"
-
- register "s0ix_enable" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- device domain 0 on
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
- device pci 13.0 off end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 on end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
- end
- chip ec/google/chromeec
- device pnp 0c09.0 on end
- end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 off end # SMBus
- device pci 1f.6 on end # Thermal
- end
-end
diff --git a/src/mainboard/google/auron/ec.h b/src/mainboard/google/auron/ec.h
index 7290a9a..ef81d0c 100644
--- a/src/mainboard/google/auron/ec.h
+++ b/src/mainboard/google/auron/ec.h
@@ -36,6 +36,7 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
#define MAINBOARD_EC_SMI_EVENTS \
@@ -54,6 +55,7 @@
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#endif
diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c
index 11831bd..70fd2ce 100644
--- a/src/mainboard/google/auron/fadt.c
+++ b/src/mainboard/google/auron/fadt.c
@@ -24,7 +24,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
- header->revision = 5;
+ header->revision = 3;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
diff --git a/src/mainboard/google/auron/gpio.h b/src/mainboard/google/auron/gpio.h
deleted file mode 100644
index 09c0460..0000000
--- a/src/mainboard/google/auron/gpio.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AURON_GPIO_H
-#define AURON_GPIO_H
-
-#include <soc/gpio.h>
-
-static const struct gpio_config mainboard_gpio_config[] = {
- PCH_GPIO_UNUSED, /* 0: UNUSED */
- PCH_GPIO_UNUSED, /* 1: UNUSED */
- PCH_GPIO_UNUSED, /* 2: UNUSED */
- PCH_GPIO_UNUSED, /* 3: UNUSED */
- PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
- PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
- PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
- PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
- PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
- PCH_GPIO_INPUT, /* 9: RAM_ID1 */
- PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
- PCH_GPIO_UNUSED, /* 11: UNUSED */
- PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
- PCH_GPIO_INPUT, /* 13: RAM_ID0 */
- PCH_GPIO_INPUT, /* 14: EC_IN_RW */
- PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 16: UNUSED */
- PCH_GPIO_UNUSED, /* 17: UNUSED */
- PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
- PCH_GPIO_UNUSED, /* 19: UNUSED */
- PCH_GPIO_UNUSED, /* 20: UNUSED */
- PCH_GPIO_UNUSED, /* 21: UNUSED */
- PCH_GPIO_UNUSED, /* 22: UNUSED */
- PCH_GPIO_UNUSED, /* 23: UNUSED */
- PCH_GPIO_UNUSED, /* 24: UNUSED */
- PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
- PCH_GPIO_UNUSED, /* 26: UNUSED */
- PCH_GPIO_UNUSED, /* 27: UNUSED */
- PCH_GPIO_UNUSED, /* 28: UNUSED */
- PCH_GPIO_UNUSED, /* 29: UNUSED */
- PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
- PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
- PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
- PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
- PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
- PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
- PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
- PCH_GPIO_UNUSED, /* 37: UNUSED */
- PCH_GPIO_UNUSED, /* 38: UNUSED */
- PCH_GPIO_UNUSED, /* 39: UNUSED */
- PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
- PCH_GPIO_UNUSED, /* 41: UNUSED */
- PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
- PCH_GPIO_UNUSED, /* 43: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
- PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
- PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
- PCH_GPIO_INPUT, /* 47: RAM_ID2 */
- PCH_GPIO_UNUSED, /* 48: UNUSED */
- PCH_GPIO_UNUSED, /* 49: UNUSED */
- PCH_GPIO_UNUSED, /* 50: UNUSED */
- PCH_GPIO_INPUT, /* 51: ALS_INT_L */
- PCH_GPIO_INPUT, /* 52: SIM_DET */
- PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
- PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
- PCH_GPIO_UNUSED, /* 55: UNUSED */
- PCH_GPIO_UNUSED, /* 56: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
- PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
- PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
- PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
- PCH_GPIO_UNUSED, /* 61: UNUSED */
- PCH_GPIO_UNUSED, /* 62: UNUSED */
- PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- PCH_GPIO_UNUSED, /* 64: UNUSED */
- PCH_GPIO_UNUSED, /* 65: UNUSED */
- PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 67: UNUSED */
- PCH_GPIO_UNUSED, /* 68: UNUSED */
- PCH_GPIO_UNUSED, /* 69: UNUSED */
- PCH_GPIO_UNUSED, /* 70: UNUSED */
- PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
- PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
- PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
- PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
- PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
- PCH_GPIO_UNUSED, /* 76: UNUSED */
- PCH_GPIO_UNUSED, /* 77: UNUSED */
- PCH_GPIO_UNUSED, /* 78: UNUSED */
- PCH_GPIO_UNUSED, /* 79: UNUSED */
- PCH_GPIO_UNUSED, /* 80: UNUSED */
- PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
- PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
- PCH_GPIO_UNUSED, /* 83: UNUSED */
- PCH_GPIO_UNUSED, /* 84: UNUSED */
- PCH_GPIO_UNUSED, /* 85: UNUSED */
- PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 87: UNUSED */
- PCH_GPIO_UNUSED, /* 88: UNUSED */
- PCH_GPIO_UNUSED, /* 89: UNUSED */
- PCH_GPIO_UNUSED, /* 90: UNUSED */
- PCH_GPIO_UNUSED, /* 91: UNUSED */
- PCH_GPIO_UNUSED, /* 92: UNUSED */
- PCH_GPIO_UNUSED, /* 93: UNUSED */
- PCH_GPIO_UNUSED, /* 94: UNUSED */
- PCH_GPIO_END
-};
-
-#endif
diff --git a/src/mainboard/google/auron/hda_verb.c b/src/mainboard/google/auron/hda_verb.c
index 4ee9c09..d1241a0 100644
--- a/src/mainboard/google/auron/hda_verb.c
+++ b/src/mainboard/google/auron/hda_verb.c
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2014 Google Inc.
- *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
@@ -13,107 +11,4 @@
* GNU General Public License for more details.
*/
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
- 0x10ec0283, // Subsystem ID
- 0x0000000d, // Number of jacks (NID entries)
-
- 0x0017ff00, // Function Reset
- 0x0017ff00, // Double Function Reset
- 0x000F0000, // Pad - get vendor id
- 0x000F0002, // Pad - get revision id
-
- /* Bits 31:28 - Codec Address */
- /* Bits 27:20 - NID */
- /* Bits 19:8 - Verb ID */
- /* Bits 7:0 - Payload */
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
- 0x00172083,
- 0x00172102,
- 0x001722ec,
- 0x00172310,
-
- /* Pin Widget Verb Table */
-
- /* Pin Complex (NID 0x12) DMIC - Disabled */
- 0x01271cf0, //
- 0x01271d11, //
- 0x01271e11, //
- 0x01271f41, //
-
- /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
- 0x01471c10, // group 1, cap 0
- 0x01471d01, // no connector, no jack detect
- 0x01471e17, // speaker out, analog
- 0x01471f90, // fixed function, internal, Location N/A
-
- /* Pin Complex (NID 0x17) MONO Out - Disabled */
- 0x01771cf0, //
- 0x01771d11, //
- 0x01771e11, //
- 0x01771f41, //
-
- /* Pin Complex (NID 0x18) Disabled */
- 0x01871cf0, //
- 0x01871d11, //
- 0x01871e11, //
- 0x01871f41, //
-
- /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
- 0x01971c20, // group2, cap 0
- 0x01971d10, // black, jack detect
- 0x01971ea1, // Mic in, 3.5mm Jack
- 0x01971f03, // connector, External left panel
-
- /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
- 0x01a71c11, // group 1, cap 1
- 0x01a71d01, // no connector, no jack detect
- 0x01a71ea7, // mic in, analog connection
- 0x01a71f90, // Fixed function, internal, Location N/A
-
- /* Pin Complex (NID 0x1B) LINE2 - Disabled */
- 0x01b71cf0, //
- 0x01b71d11, //
- 0x01b71e11, //
- 0x01b71f41, //
-
- /* Pin Complex (NID 0x1D) PCBeep */
- 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
- 0x01d71d81, // mute spkr on hpout
- 0x01d71e15, // pcbeep en able, checksum
- 0x01d71f40, // no physical, Internal, Location N/A
-
- /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
- 0x01e71cf0, //
- 0x01e71d11, //
- 0x01e71e11, //
- 0x01e71f41, //
-
- /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
- 0x02171c21, // group2, cap 1
- 0x02171d10, // black, jack detect
- 0x02171e21, // HPOut, 3.5mm Jack
- 0x02171f03, // connector, left panel
-
- /* Undocumented settings from Realtek (needed for beep_gen) */
- /* Widget node 0x20 */
- 0x02050010,
- 0x02040c20,
- 0x0205001b,
- 0x0204081b,
-};
-
-const u32 pc_beep_verbs[] = {
- 0x00170500, /* power up everything (codec, dac, adc, mixers) */
- 0x01470740, /* enable speaker out */
- 0x01470c02, /* set speaker EAPD pin */
- 0x0143b01f, /* unmute speaker */
- 0x00c37100, /* unmute mixer nid 0xc input 1 */
- 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
-};
-
-AZALIA_ARRAY_SIZES;
+#include <variant/hda_verb.h>
diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c
index 188c16d..ca0c083 100644
--- a/src/mainboard/google/auron/mainboard.c
+++ b/src/mainboard/google/auron/mainboard.c
@@ -14,23 +14,10 @@
* GNU General Public License for more details.
*/
-#include <types.h>
-#include <string.h>
-#include <smbios.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
-#include "onboard.h"
+#include "variant.h"
static void mainboard_init(device_t dev)
@@ -41,45 +28,7 @@ static void mainboard_init(device_t dev)
static int mainboard_smbios_data(device_t dev, int *handle,
unsigned long *current)
{
- int len = 0;
-
- len += smbios_write_type41(
- current, handle,
- BOARD_LIGHTSENSOR_NAME, /* name */
- BOARD_LIGHTSENSOR_IRQ, /* instance */
- BOARD_LIGHTSENSOR_I2C_BUS, /* segment */
- BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- len += smbios_write_type41(
- current, handle,
- BOARD_TRACKPAD_NAME, /* name */
- BOARD_TRACKPAD_IRQ, /* instance */
- BOARD_TRACKPAD_I2C_BUS, /* segment */
- BOARD_TRACKPAD_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- len += smbios_write_type41(
- current, handle,
- BOARD_TRACKPAD_NAME, /* name */
- BOARD_TRACKPAD_IRQ, /* instance */
- BOARD_TRACKPAD_I2C_BUS, /* segment */
- BOARD_TRACKPAD_GEN5_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- len += smbios_write_type41(
- current, handle,
- BOARD_TOUCHSCREEN_NAME, /* name */
- BOARD_TOUCHSCREEN_IRQ, /* instance */
- BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
- BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- return len;
+ return variant_smbios_data(dev, handle, current);
}
// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h
deleted file mode 100644
index cf0e2be..0000000
--- a/src/mainboard/google/auron/onboard.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef ONBOARD_H
-#define ONBOARD_H
-
-#define BOARD_LIGHTSENSOR_NAME "lightsensor"
-#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */
-#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */
-#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44
-
-#define BOARD_TRACKPAD_NAME "trackpad"
-#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
-#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
-#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
-#define BOARD_TRACKPAD_I2C_ADDR 0x67
-#define BOARD_TRACKPAD_GEN5_I2C_ADDR 0x24
-
-#define BOARD_TOUCHSCREEN_NAME "touchscreen"
-#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */
-#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */
-#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
-#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
-
-#endif
diff --git a/src/mainboard/google/auron/pei_data.c b/src/mainboard/google/auron/pei_data.c
deleted file mode 100644
index a5b2384..0000000
--- a/src/mainboard/google/auron/pei_data.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-
-void mainboard_fill_pei_data(struct pei_data *pei_data)
-{
- pei_data->ec_present = 1;
-
- /* One installed DIMM per channel -- can be changed by SPD init */
- pei_data->dimm_channel0_disabled = 2;
- pei_data->dimm_channel1_disabled = 2;
-
- /* P0: LTE */
- pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
- USB_PORT_MINI_PCIE);
- /* P1: POrt A, CN10 */
- pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
- USB_PORT_BACK_PANEL);
- /* P2: CCD */
- pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
- /* P3: BT */
- pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_MINI_PCIE);
- /* P4: Port B, CN6 */
- pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
- USB_PORT_BACK_PANEL);
- /* P5: EMPTY */
- pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
- /* P6: SD Card */
- pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
- USB_PORT_FLEX);
- /* P7: EMPTY */
- pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
-
- /* P1: Port A, CN6 */
- pei_data_usb3_port(pei_data, 0, 1, 0, 0);
- /* P2: EMPTY */
- pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
- /* P3: EMPTY */
- pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
- /* P4: EMPTY */
- pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
-}
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c
index 7e5a8e3..22a070e 100644
--- a/src/mainboard/google/auron/romstage.c
+++ b/src/mainboard/google/auron/romstage.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <cbfs.h>
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
@@ -22,8 +21,9 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
-#include <mainboard/google/auron/spd/spd.h>
-#include "gpio.h"
+#include <variant/gpio.h>
+#include <variant/spd.h>
+#include "variant.h"
void mainboard_romstage_entry(struct romstage_params *rp)
{
@@ -45,4 +45,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
+
+ /* Do variant-specific (read: Samus) init */
+ variant_romstage_entry(rp);
}
diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index c962bb9..03d07b9 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -25,15 +25,8 @@
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/nvs.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
#include "ec.h"
-
-/* Codec enable: GPIO45 */
-#define GPIO_PP3300_CODEC_EN 45
-/* WLAN / BT enable: GPIO46 */
-#define GPIO_WLAN_DISABLE_L 46
-
+#include <variant/onboard.h>
static u8 mainboard_smi_ec(void)
{
@@ -70,6 +63,20 @@ void mainboard_smi_gpi(u32 gpi_sts)
}
}
+static void mainboard_disable_gpios(void)
+{
+#if IS_ENABLED(CONFIG_BOARD_GOOGLE_SAMUS)
+ /* Put SSD in reset to prevent leak */
+ set_gpio(BOARD_SSD_RESET_GPIO, 0);
+ /* Disable LTE */
+ set_gpio(BOARD_LTE_DISABLE_GPIO, 0);
+#else
+ set_gpio(BOARD_PP3300_CODEC_GPIO, 0);
+#endif
+ /* Prevent leak from standby rail to WLAN rail */
+ set_gpio(BOARD_WLAN_DISABLE_GPIO, 0);
+}
+
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
@@ -82,8 +89,7 @@ void mainboard_smi_sleep(u8 slp_typ)
1, USB_CHARGE_MODE_DISABLED);
}
- set_gpio(GPIO_PP3300_CODEC_EN, 0);
- set_gpio(GPIO_WLAN_DISABLE_L, 0);
+ mainboard_disable_gpios();
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
@@ -96,8 +102,7 @@ void mainboard_smi_sleep(u8 slp_typ)
1, USB_CHARGE_MODE_DISABLED);
}
- set_gpio(GPIO_PP3300_CODEC_EN, 0);
- set_gpio(GPIO_WLAN_DISABLE_L, 0);
+ mainboard_disable_gpios();
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
diff --git a/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex
deleted file mode 100644
index eb41f0b..0000000
--- a/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex
+++ /dev/null
@@ -1,17 +0,0 @@
-# Elpida EDJ4216EFBG-GN-F
-92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
-69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE
-45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46
-00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex
deleted file mode 100644
index 7b09327..0000000
--- a/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex
+++ /dev/null
@@ -1,17 +0,0 @@
-# Hynix HMT425S6AFR6A-PBA
-92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
-69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
-48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
-20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/spd/Makefile.inc b/src/mainboard/google/auron/spd/Makefile.inc
deleted file mode 100644
index bf9ce14..0000000
--- a/src/mainboard/google/auron/spd/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd.c
-
-SPD_BIN = $(obj)/spd.bin
-
-# { GPIO47, GPIO9, GPIO13 }
-SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
-SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0010
-SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
-SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
-SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0110
-SPD_SOURCES += empty # 0b0111
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do echo -e -n "\\x$$c"; \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex
deleted file mode 100644
index cbe9e4f..0000000
--- a/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex
+++ /dev/null
@@ -1,17 +0,0 @@
-# Micron 4KTF25664HZ-1G6E1
-92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
-69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
-34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
-31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/spd/empty.spd.hex b/src/mainboard/google/auron/spd/empty.spd.hex
deleted file mode 100644
index 9ec39f1..0000000
--- a/src/mainboard/google/auron/spd/empty.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/spd/spd.c b/src/mainboard/google/auron/spd/spd.c
deleted file mode 100644
index 541d8e1..0000000
--- a/src/mainboard/google/auron/spd/spd.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <endian.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron/ec.h>
-#include <mainboard/google/auron/gpio.h>
-#include <mainboard/google/auron/spd/spd.h>
-
-static void mainboard_print_spd_info(uint8_t spd[])
-{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[SPD_PART_LEN+1] = { 0 };
-
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
-
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
- case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- break;
- case SPD_DRAM_LPDDR3:
- printk(BIOS_INFO, "LPDDR3\n");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
- break;
- }
-
- /* Module Part Number */
- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
- spd_name[SPD_PART_LEN] = 0;
- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
-
- printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
- , banks, ranks, rows, cols);
- printk(BIOS_INFO, "density %d Mb\n", capmb);
-
- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
- devw, busw);
-
- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
- capmb / 8 * busw / devw * ranks);
- }
-}
-
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
-{
- int spd_bits[3] = {
- SPD_GPIO_BIT0,
- SPD_GPIO_BIT1,
- SPD_GPIO_BIT2
- };
- int spd_gpio[3];
- int spd_index;
- size_t spd_file_len;
- char *spd_file;
-
- spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
- spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
- spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
-
- spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
-
- printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
- spd_index,
- spd_bits[2], spd_gpio[2],
- spd_bits[1], spd_gpio[1],
- spd_bits[0], spd_gpio[0]);
-
- spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- memcpy(pei_data->spd_data[0][0],
- spd_file + (spd_index * SPD_LEN), SPD_LEN);
- /* Index 0-2 are 4GB config with both CH0 and CH1.
- * Index 4-6 are 2GB config with CH0 only. */
- if (spd_index > 3)
- pei_data->dimm_channel1_disabled = 3;
- else
- memcpy(pei_data->spd_data[1][0],
- spd_file + (spd_index * SPD_LEN), SPD_LEN);
-
- /* Make sure a valid SPD was found */
- if (pei_data->spd_data[0][0][0] == 0)
- die("Invalid SPD data.");
-
- mainboard_print_spd_info(pei_data->spd_data[0][0]);
-}
diff --git a/src/mainboard/google/auron/spd/spd.h b/src/mainboard/google/auron/spd/spd.h
deleted file mode 100644
index cbb463f..0000000
--- a/src/mainboard/google/auron/spd/spd.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 256
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-
-/* Auron board memory configuration GPIOs */
-#define SPD_GPIO_BIT0 13
-#define SPD_GPIO_BIT1 9
-#define SPD_GPIO_BIT2 47
-
-struct pei_data;
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
-#endif
diff --git a/src/mainboard/google/auron/thermal.h b/src/mainboard/google/auron/thermal.h
deleted file mode 100644
index 0b66c0b..0000000
--- a/src/mainboard/google/auron/thermal.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef THERMAL_H
-#define THERMAL_H
-
-/* Control TDP Settings */
-#define CTL_TDP_SENSOR_ID 0 /* PECI */
-#define CTL_TDP_POWER_LIMIT 12 /* 12W */
-#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
-#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
-#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 104
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 95
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 105
-
-#endif
diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h
new file mode 100644
index 0000000..d5c2347
--- /dev/null
+++ b/src/mainboard/google/auron/variant.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+#include <arch/io.h>
+#include <soc/romstage.h>
+
+int variant_smbios_data(device_t dev, int *handle, unsigned long *current);
+void variant_romstage_entry(struct romstage_params *rp);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
new file mode 100644
index 0000000..5872cf2
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
@@ -0,0 +1,108 @@
+chip soc/intel/broadwell
+
+ # Enable eDP Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Disable DisplayPort C Hotplug
+ register "gpu_dp_c_hotplug" = "0x00"
+
+ # Enable HDMI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000000"
+
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "400" # 40ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
+
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sio_acpi_mode" = "1"
+
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+
+ # Force enable ASPM for PCIe Port1
+ register "pcie_port_force_aspm" = "0x01"
+
+ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013c0000"
+
+ register "s0ix_enable" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
+ end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..1befc4b
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C0)
+{
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h
new file mode 100644
index 0000000..44b930a
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AURON_PAINE_GPIO_H
+#define AURON_PAINE_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
+ PCH_GPIO_INPUT, /* 9: RAM_ID1 */
+ PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
+ PCH_GPIO_UNUSED, /* 11: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
+ PCH_GPIO_INPUT, /* 13: RAM_ID0 */
+ PCH_GPIO_INPUT, /* 14: EC_IN_RW */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 16: UNUSED */
+ PCH_GPIO_UNUSED, /* 17: UNUSED */
+ PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_UNUSED, /* 20: UNUSED */
+ PCH_GPIO_UNUSED, /* 21: UNUSED */
+ PCH_GPIO_UNUSED, /* 22: UNUSED */
+ PCH_GPIO_UNUSED, /* 23: UNUSED */
+ PCH_GPIO_UNUSED, /* 24: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
+ PCH_GPIO_UNUSED, /* 26: UNUSED */
+ PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_UNUSED, /* 28: UNUSED */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
+ PCH_GPIO_UNUSED, /* 41: UNUSED */
+ PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
+ PCH_GPIO_UNUSED, /* 43: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
+ PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
+ PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
+ PCH_GPIO_INPUT, /* 47: RAM_ID2 */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_UNUSED, /* 49: UNUSED */
+ PCH_GPIO_UNUSED, /* 50: UNUSED */
+ PCH_GPIO_INPUT, /* 51: ALS_INT_L */
+ PCH_GPIO_INPUT, /* 52: SIM_DET */
+ PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
+ PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_UNUSED, /* 56: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
+ PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
+ PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
+ PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
+ PCH_GPIO_UNUSED, /* 61: UNUSED */
+ PCH_GPIO_UNUSED, /* 62: UNUSED */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
+ PCH_GPIO_UNUSED, /* 65: UNUSED */
+ PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 67: UNUSED */
+ PCH_GPIO_UNUSED, /* 68: UNUSED */
+ PCH_GPIO_UNUSED, /* 69: UNUSED */
+ PCH_GPIO_UNUSED, /* 70: UNUSED */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
+ PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
+ PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
+ PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_UNUSED, /* 83: UNUSED */
+ PCH_GPIO_UNUSED, /* 84: UNUSED */
+ PCH_GPIO_UNUSED, /* 85: UNUSED */
+ PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_UNUSED, /* 89: UNUSED */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_UNUSED, /* 91: UNUSED */
+ PCH_GPIO_UNUSED, /* 92: UNUSED */
+ PCH_GPIO_UNUSED, /* 93: UNUSED */
+ PCH_GPIO_UNUSED, /* 94: UNUSED */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h
new file mode 100644
index 0000000..f7cb248
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
+ 0x10ec0283, // Subsystem ID
+ 0x0000000e, // Number of jacks (NID entries)
+
+ 0x0017ff00, // Function Reset
+ 0x0017ff00, // Double Function Reset
+ 0x000F0000, // Pad - get vendor id
+ 0x000F0002, // Pad - get revision id
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table */
+ AZALIA_SUBVENDOR(0x0, 0x11790670),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) DMIC - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
+
+ /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
+ // group 1, cap 0
+ // no connector, no jack detect
+ // speaker out, analog
+ // fixed function, internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+ /* Pin Complex (NID 0x17) MONO Out - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+ /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
+ // group2, cap 0
+ // black, jack detect
+ // Mic in, 3.5mm Jack
+ // connector, External left panel
+ AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
+
+ /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
+ // group 1, cap 1
+ // no connector, no jack detect
+ // mic in, analog connection
+ // Fixed function, internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x90a70111),
+
+ /* Pin Complex (NID 0x1B) LINE2 - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) PCBeep */
+ // eapd low on ex-amp, laptop, custom enable
+ // mute spkr on hpout
+ // pcbeep en able, checksum
+ // no physical, Internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d),
+
+ /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
+ // group2, cap 1
+ // black, jack detect
+ // HPOut, 3.5mm Jack
+ // connector, left panel
+ AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
+
+ /* Undocumented settings from Realtek (needed for beep_gen) */
+ /* Widget node 0x20 */
+ 0x02050010,
+ 0x02040c20,
+ 0x0205001b,
+ 0x0204081b,
+
+ /* Tuned jack detection */
+ 0x02050043,
+ 0x0204A614,
+ 0x02050047,
+ 0x02049470,
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up everything (codec, dac, adc, mixers) */
+ 0x01470740, /* enable speaker out */
+ 0x01470c02, /* set speaker EAPD pin */
+ 0x0143b01f, /* unmute speaker */
+ 0x00c37100, /* unmute mixer nid 0xc input 1 */
+ 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h
new file mode 100644
index 0000000..97975a1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
+#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
+#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
+#define BOARD_TRACKPAD_I2C_ADDR 0x15
+
+#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
+#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
+#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h
new file mode 100644
index 0000000..0a37a70
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+/* Auron board memory configuration GPIOs */
+#define SPD_GPIO_BIT0 13
+#define SPD_GPIO_BIT1 9
+#define SPD_GPIO_BIT2 47
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h
new file mode 100644
index 0000000..0b66c0b
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID 0 /* PECI */
+#define CTL_TDP_POWER_LIMIT 12 /* 12W */
+#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
+#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
+#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 105
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
new file mode 100644
index 0000000..a5b2384
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel -- can be changed by SPD init */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ /* P0: LTE */
+ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P1: POrt A, CN10 */
+ pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P2: CCD */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P3: BT */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P4: Port B, CN6 */
+ pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+ USB_PORT_BACK_PANEL);
+ /* P5: EMPTY */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: SD Card */
+ pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FLEX);
+ /* P7: EMPTY */
+ pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+
+ /* P1: Port A, CN6 */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: EMPTY */
+ pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
+ /* P3: EMPTY */
+ pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+ /* P4: EMPTY */
+ pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex
new file mode 100644
index 0000000..7b09327
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6AFR6A-PBA
+92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
+48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
new file mode 100644
index 0000000..8ced790
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6CFR6A-PBA
+92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc
new file mode 100644
index 0000000..048be2d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc
@@ -0,0 +1,50 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO47, GPIO9, GPIO13 }
+SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0010
+SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
+SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0110
+SPD_SOURCES += empty # 0b0111
+SPD_SOURCES += empty # 0b1000
+SPD_SOURCES += empty # 0b1001
+SPD_SOURCES += empty # 0b1010
+SPD_SOURCES += empty # 0b1011
+SPD_SOURCES += empty # 0b1100
+SPD_SOURCES += empty # 0b1101
+SPD_SOURCES += empty # 0b1110
+SPD_SOURCES += empty # 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex
new file mode 100644
index 0000000..cbe9e4f
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex
@@ -0,0 +1,17 @@
+# Micron 4KTF25664HZ-1G6E1
+92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
+34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
+31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex b/src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex
new file mode 100644
index 0000000..9ec39f1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
new file mode 100644
index 0000000..12c876e
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
@@ -0,0 +1,132 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <variant/gpio.h>
+#include <variant/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+ , banks, ranks, rows, cols);
+ printk(BIOS_INFO, "density %d Mb\n", capmb);
+
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int spd_bits[3] = {
+ SPD_GPIO_BIT0,
+ SPD_GPIO_BIT1,
+ SPD_GPIO_BIT2
+ };
+ int spd_gpio[3];
+ int spd_index;
+ size_t spd_file_len;
+ char *spd_file;
+
+ spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+ spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+ spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+
+ spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
+
+ printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+ spd_index,
+ spd_bits[2], spd_gpio[2],
+ spd_bits[1], spd_gpio[1],
+ spd_bits[0], spd_gpio[0]);
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ memcpy(pei_data->spd_data[0][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+ /* Index 0-2 are 4GB config with both CH0 and CH1.
+ * Index 4-6 are 2GB config with CH0 only. */
+ if (spd_index > 3)
+ pei_data->dimm_channel1_disabled = 3;
+ else
+ memcpy(pei_data->spd_data[1][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+
+ /* Make sure a valid SPD was found */
+ if (pei_data->spd_data[0][0][0] == 0)
+ die("Invalid SPD data.");
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c
new file mode 100644
index 0000000..f1af14d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/variant.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <soc/romstage.h>
+#include <variant/onboard.h>
+#include <mainboard/google/auron/variant.h>
+
+int variant_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+void variant_romstage_entry(struct romstage_params *rp)
+{
+ /* N/A for boards other than SAMUS */
+}
diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
new file mode 100644
index 0000000..34051a7
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
@@ -0,0 +1,108 @@
+chip soc/intel/broadwell
+
+ # Enable eDP Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Disable DisplayPort C Hotplug
+ register "gpu_dp_c_hotplug" = "0x00"
+
+ # Enable HDMI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000000"
+
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "400" # 40ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
+
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sio_acpi_mode" = "1"
+
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x7"
+ register "sata_port1_gen3_dtle" = "0x5"
+
+ # Force enable ASPM for PCIe Port1
+ register "pcie_port_force_aspm" = "0x01"
+
+ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013c0000"
+
+ register "s0ix_enable" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
+ end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..1befc4b
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C0)
+{
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h
new file mode 100644
index 0000000..eca65d1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AURON_YUNA_GPIO_H
+#define AURON_YUNA_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
+ PCH_GPIO_INPUT, /* 9: RAM_ID1 */
+ PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
+ PCH_GPIO_UNUSED, /* 11: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
+ PCH_GPIO_INPUT, /* 13: RAM_ID0 */
+ PCH_GPIO_INPUT, /* 14: EC_IN_RW */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 16: UNUSED */
+ PCH_GPIO_UNUSED, /* 17: UNUSED */
+ PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_UNUSED, /* 20: UNUSED */
+ PCH_GPIO_UNUSED, /* 21: UNUSED */
+ PCH_GPIO_UNUSED, /* 22: UNUSED */
+ PCH_GPIO_UNUSED, /* 23: UNUSED */
+ PCH_GPIO_UNUSED, /* 24: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
+ PCH_GPIO_UNUSED, /* 26: UNUSED */
+ PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_UNUSED, /* 28: UNUSED */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
+ PCH_GPIO_UNUSED, /* 41: UNUSED */
+ PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
+ PCH_GPIO_UNUSED, /* 43: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
+ PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
+ PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
+ PCH_GPIO_INPUT, /* 47: RAM_ID2 */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_UNUSED, /* 49: UNUSED */
+ PCH_GPIO_UNUSED, /* 50: UNUSED */
+ PCH_GPIO_INPUT, /* 51: ALS_INT_L */
+ PCH_GPIO_INPUT, /* 52: SIM_DET */
+ PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
+ PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_UNUSED, /* 56: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
+ PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
+ PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
+ PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
+ PCH_GPIO_UNUSED, /* 61: UNUSED */
+ PCH_GPIO_UNUSED, /* 62: UNUSED */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
+ PCH_GPIO_UNUSED, /* 65: UNUSED */
+ PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 67: UNUSED */
+ PCH_GPIO_UNUSED, /* 68: UNUSED */
+ PCH_GPIO_UNUSED, /* 69: UNUSED */
+ PCH_GPIO_UNUSED, /* 70: UNUSED */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
+ PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
+ PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
+ PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_UNUSED, /* 83: UNUSED */
+ PCH_GPIO_UNUSED, /* 84: UNUSED */
+ PCH_GPIO_UNUSED, /* 85: UNUSED */
+ PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_UNUSED, /* 89: UNUSED */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_UNUSED, /* 91: UNUSED */
+ PCH_GPIO_UNUSED, /* 92: UNUSED */
+ PCH_GPIO_UNUSED, /* 93: UNUSED */
+ PCH_GPIO_UNUSED, /* 94: UNUSED */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h
new file mode 100644
index 0000000..e283e95
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
+ 0x10ec0283, // Subsystem ID
+ 0x00000013, // Number of jacks (NID entries)
+
+ 0x0017ff00, // Function Reset
+ 0x0017ff00, // Double Function Reset
+ 0x000F0000, // Pad - get vendor id
+ 0x000F0002, // Pad - get revision id
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table */
+ AZALIA_SUBVENDOR(0x0, 0x11790670),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) DMIC - Enabled */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
+
+ /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
+ // group 1, cap 0
+ // no connector, no jack detect
+ // speaker out, analog
+ // fixed function, internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+ /* Pin Complex (NID 0x17) MONO Out - Enabled */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x40000008),
+
+ /* Pin Complex (NID 0x18) Disabled */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
+ // group2, cap 0
+ // black, jack detect
+ // Mic in, 3.5mm Jack
+ // connector, External left panel
+ AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
+
+ /* Pin Complex (NID 0x1A) LINE1 - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) LINE2 - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) PCBeep */
+ // eapd low on ex-amp, laptop, custom enable
+ // mute spkr on hpout
+ // pcbeep en able, checksum
+ // no physical, Internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d),
+
+ /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
+ // group1
+ // black, jack detect
+ // HPOut, 3.5mm Jack
+ // connector, left panel
+ AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),
+
+ /* Undocumented settings from Realtek (needed for beep_gen) */
+ /* Widget node 0x20 */
+ 0x02050038,
+ 0x02046900,
+ 0x02050010,
+ 0x02040C20,
+ /* Widget node 0x20 - 1 */
+ 0x02050019,
+ 0x02041857,
+ 0x0205001A,
+ 0x02044001,
+ /* Widget node 0x20 - 2 */
+ 0x0205001B,
+ 0x0204140B,
+ 0x02050025,
+ 0x0204802A,
+ /* Widget node 0x20 - 3 */
+ 0x02050045,
+ 0x02045029,
+ 0x02050046,
+ 0x02040004,
+ /* Widget node 0x20 - 4 */
+ 0x02050043,
+ 0x0204A614,
+ 0x02050043,
+ 0x0204A614,
+ /* pc beep */
+ 0x02050010,
+ 0x02040c20,
+ 0x0205001b,
+ 0x0204081b,
+
+ /* Tuned jack detection */
+ 0x02050043,
+ 0x0204A614,
+ 0x02050047,
+ 0x02049470,
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up everything (codec, dac, adc, mixers) */
+ 0x01470740, /* enable speaker out */
+ 0x01470c02, /* set speaker EAPD pin */
+ 0x0143b01f, /* unmute speaker */
+ 0x00c37100, /* unmute mixer nid 0xc input 1 */
+ 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h
new file mode 100644
index 0000000..97975a1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
+#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
+#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
+#define BOARD_TRACKPAD_I2C_ADDR 0x15
+
+#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
+#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
+#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h
new file mode 100644
index 0000000..0a37a70
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+/* Auron board memory configuration GPIOs */
+#define SPD_GPIO_BIT0 13
+#define SPD_GPIO_BIT1 9
+#define SPD_GPIO_BIT2 47
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h
new file mode 100644
index 0000000..0b66c0b
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID 0 /* PECI */
+#define CTL_TDP_POWER_LIMIT 12 /* 12W */
+#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
+#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
+#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 105
+
+#endif
diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
new file mode 100644
index 0000000..a5b2384
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel -- can be changed by SPD init */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ /* P0: LTE */
+ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P1: POrt A, CN10 */
+ pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P2: CCD */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P3: BT */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P4: Port B, CN6 */
+ pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+ USB_PORT_BACK_PANEL);
+ /* P5: EMPTY */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: SD Card */
+ pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FLEX);
+ /* P7: EMPTY */
+ pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+
+ /* P1: Port A, CN6 */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: EMPTY */
+ pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
+ /* P3: EMPTY */
+ pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+ /* P4: EMPTY */
+ pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex
new file mode 100644
index 0000000..7b09327
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6AFR6A-PBA
+92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
+48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
new file mode 100644
index 0000000..8ced790
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6CFR6A-PBA
+92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc
new file mode 100644
index 0000000..048be2d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc
@@ -0,0 +1,50 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO47, GPIO9, GPIO13 }
+SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0010
+SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
+SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0110
+SPD_SOURCES += empty # 0b0111
+SPD_SOURCES += empty # 0b1000
+SPD_SOURCES += empty # 0b1001
+SPD_SOURCES += empty # 0b1010
+SPD_SOURCES += empty # 0b1011
+SPD_SOURCES += empty # 0b1100
+SPD_SOURCES += empty # 0b1101
+SPD_SOURCES += empty # 0b1110
+SPD_SOURCES += empty # 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex
new file mode 100644
index 0000000..cbe9e4f
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex
@@ -0,0 +1,17 @@
+# Micron 4KTF25664HZ-1G6E1
+92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
+34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
+31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex b/src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex
new file mode 100644
index 0000000..9ec39f1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
new file mode 100644
index 0000000..12c876e
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
@@ -0,0 +1,132 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <variant/gpio.h>
+#include <variant/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+ , banks, ranks, rows, cols);
+ printk(BIOS_INFO, "density %d Mb\n", capmb);
+
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int spd_bits[3] = {
+ SPD_GPIO_BIT0,
+ SPD_GPIO_BIT1,
+ SPD_GPIO_BIT2
+ };
+ int spd_gpio[3];
+ int spd_index;
+ size_t spd_file_len;
+ char *spd_file;
+
+ spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+ spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+ spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+
+ spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
+
+ printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+ spd_index,
+ spd_bits[2], spd_gpio[2],
+ spd_bits[1], spd_gpio[1],
+ spd_bits[0], spd_gpio[0]);
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ memcpy(pei_data->spd_data[0][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+ /* Index 0-2 are 4GB config with both CH0 and CH1.
+ * Index 4-6 are 2GB config with CH0 only. */
+ if (spd_index > 3)
+ pei_data->dimm_channel1_disabled = 3;
+ else
+ memcpy(pei_data->spd_data[1][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+
+ /* Make sure a valid SPD was found */
+ if (pei_data->spd_data[0][0][0] == 0)
+ die("Invalid SPD data.");
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c
new file mode 100644
index 0000000..f1af14d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <soc/romstage.h>
+#include <variant/onboard.h>
+#include <mainboard/google/auron/variant.h>
+
+int variant_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+void variant_romstage_entry(struct romstage_params *rp)
+{
+ /* N/A for boards other than SAMUS */
+}
diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb
new file mode 100644
index 0000000..06ff8ae
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb
@@ -0,0 +1,108 @@
+chip soc/intel/broadwell
+
+ # Enable eDP Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Disable DisplayPort C Hotplug
+ register "gpu_dp_c_hotplug" = "0x00"
+
+ # Enable HDMI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000000"
+
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "400" # 40ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "500" # 50ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
+
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sio_acpi_mode" = "1"
+
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+
+ # Force enable ASPM for PCIe Port1
+ register "pcie_port_force_aspm" = "0x01"
+
+ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013c0000"
+
+ register "s0ix_enable" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
+ end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..bfdf476
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C0)
+{
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h b/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h
new file mode 100644
index 0000000..68fe4a0
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef GANDOF_GPIO_H
+#define GANDOF_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_UNUSED, /* 8: UNUSED */
+ PCH_GPIO_INPUT, /* 9: RAM_ID1 */
+ PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
+ PCH_GPIO_UNUSED, /* 11: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
+ PCH_GPIO_INPUT, /* 13: RAM_ID0 */
+ PCH_GPIO_INPUT, /* 14: EC_IN_RW */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 16: UNUSED */
+ PCH_GPIO_UNUSED, /* 17: UNUSED */
+ PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_UNUSED, /* 20: UNUSED */
+ PCH_GPIO_UNUSED, /* 21: UNUSED */
+ PCH_GPIO_UNUSED, /* 22: UNUSED */
+ PCH_GPIO_UNUSED, /* 23: UNUSED */
+ PCH_GPIO_UNUSED, /* 24: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
+ PCH_GPIO_UNUSED, /* 26: UNUSED */
+ PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_UNUSED, /* 28: UNUSED */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
+ PCH_GPIO_UNUSED, /* 41: UNUSED */
+ PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
+ PCH_GPIO_UNUSED, /* 43: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
+ PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
+ PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
+ PCH_GPIO_INPUT, /* 47: RAM_ID2 */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_UNUSED, /* 49: UNUSED */
+ PCH_GPIO_UNUSED, /* 50: UNUSED */
+ PCH_GPIO_UNUSED, /* 51: UNUSED */
+ PCH_GPIO_UNUSED, /* 52: UNUSED */
+ PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
+ PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_UNUSED, /* 56: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
+ PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
+ PCH_GPIO_UNUSED, /* 59: UNUSED */
+ PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
+ PCH_GPIO_UNUSED, /* 61: UNUSED */
+ PCH_GPIO_UNUSED, /* 62: UNUSED */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
+ PCH_GPIO_UNUSED, /* 65: UNUSED */
+ PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 67: UNUSED */
+ PCH_GPIO_UNUSED, /* 68: UNUSED */
+ PCH_GPIO_UNUSED, /* 69: UNUSED */
+ PCH_GPIO_UNUSED, /* 70: UNUSED */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
+ PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
+ PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
+ PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_UNUSED, /* 83: UNUSED */
+ PCH_GPIO_UNUSED, /* 84: UNUSED */
+ PCH_GPIO_UNUSED, /* 85: UNUSED */
+ PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_UNUSED, /* 89: UNUSED */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_UNUSED, /* 91: UNUSED */
+ PCH_GPIO_UNUSED, /* 92: UNUSED */
+ PCH_GPIO_UNUSED, /* 93: UNUSED */
+ PCH_GPIO_UNUSED, /* 94: UNUSED */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h
new file mode 100644
index 0000000..dc2d534
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
+ 0x10ec0283, // Subsystem ID
+ 0x0000000e, // Number of jacks (NID entries)
+
+ 0x0017ff00, // Function Reset
+ 0x0017ff00, // Double Function Reset
+ 0x000F0000, // Pad - get vendor id
+ 0x000F0002, // Pad - get revision id
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table */
+ AZALIA_SUBVENDOR(0x0, 0x11790670),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) DMIC - Internal MIC */
+ // group 3, cap 0
+ // no connector, no jack detect
+ // mic in, digital
+ // fixed function, internal
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
+
+ /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
+ // group 1, cap 0
+ // no connector, no jack detect
+ // speaker out, analog
+ // fixed function, internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+ /* Pin Complex (NID 0x17) MONO Out - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+ /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
+ // group2, cap 0
+ // black, jack detect
+ // Mic in, 3.5mm Jack
+ // connector, External left panel
+ AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
+
+ /* Pin Complex (NID 0x1A) LINE1 - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) LINE2 - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) PCBeep */
+ // eapd low on ex-amp, laptop, custom enable
+ // mute spkr on hpout
+ // pcbeep en able, checksum
+ // no physical, Internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d),
+
+ /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack */
+ // group2, cap 1
+ // black, jack detect
+ // HPOut, 3.5mm Jack
+ // connector, left panel
+ AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
+
+ /* Undocumented settings from Realtek (needed for beep_gen) */
+ /* Widget node 0x20 */
+ 0x02050010,
+ 0x02040c20,
+ 0x0205001b,
+ 0x0204081b,
+
+ /* Tuned jack detection */
+ 0x02050043,
+ 0x0204A614,
+ 0x02050047,
+ 0x02049470,
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up everything (codec, dac, adc, mixers) */
+ 0x01470740, /* enable speaker out */
+ 0x01470c02, /* set speaker EAPD pin */
+ 0x0143b01f, /* unmute speaker */
+ 0x00c37100, /* unmute mixer nid 0xc input 1 */
+ 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h b/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h
new file mode 100644
index 0000000..97975a1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/include/variant/onboard.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
+#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
+#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
+#define BOARD_TRACKPAD_I2C_ADDR 0x15
+
+#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
+#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
+#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
+
+#endif
diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h
new file mode 100644
index 0000000..8720ab0
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+/* Gandof board memory configuration GPIOs */
+#define SPD_GPIO_BIT0 13
+#define SPD_GPIO_BIT1 9
+#define SPD_GPIO_BIT2 47
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h b/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h
new file mode 100644
index 0000000..cd0bacb
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/include/variant/thermal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID 0 /* PECI */
+#define CTL_TDP_POWER_LIMIT 9 /* 8W */
+#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
+#define CTL_TDP_THRESHOLD_OFF 66 /* Normal at 64C */
+#define CTL_TDP_THRESHOLD_ON 75 /* Limited at 76C */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 105
+
+#endif
diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c
new file mode 100644
index 0000000..ef2e336
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/pei_data.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel -- can be changed by SPD init */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ /* P0: LTE */
+ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P1: POrt A, CN10 */
+ pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P2: CCD */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P3: BT */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P4: Port B, CN6 */
+ pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+ USB_PORT_BACK_PANEL);
+ /* P5: EMPTY */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: SD Card */
+ pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FLEX);
+ /* P7: EMPTY */
+ pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+
+ /* P1: Port A, CN6 */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: EMPTY */
+ pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
+ /* P3: EMPTY */
+ pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+ /* P4: EMPTY */
+ pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex
new file mode 100644
index 0000000..459bc98
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6AFR6A-PBA
+92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
+48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
new file mode 100644
index 0000000..af74439
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6CFR6A-PBA
+92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc
new file mode 100644
index 0000000..0e05edb
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc
@@ -0,0 +1,42 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO47, GPIO9, GPIO13 }
+SPD_SOURCES = Samsung_M471B5674EB0-YK0 # 0b0000
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0001
+SPD_SOURCES += empty # 0b0010
+SPD_SOURCES += empty # 0b0011
+SPD_SOURCES += Samsung_M471B5674EB0-YK0 # 0b0100
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0101
+SPD_SOURCES += empty # 0b0110
+SPD_SOURCES += empty # 0b0111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex
new file mode 100644
index 0000000..75837e2
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex
@@ -0,0 +1,17 @@
+# Micron 4KTF25664HZ-1G6E1
+92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
+34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
+31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex b/src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex
new file mode 100644
index 0000000..0cdaae7
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung_M471B5674EB0-YK0
+92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F
+4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex b/src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex
new file mode 100644
index 0000000..e83f7e8
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c
new file mode 100644
index 0000000..12c876e
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c
@@ -0,0 +1,132 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <variant/gpio.h>
+#include <variant/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+ , banks, ranks, rows, cols);
+ printk(BIOS_INFO, "density %d Mb\n", capmb);
+
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int spd_bits[3] = {
+ SPD_GPIO_BIT0,
+ SPD_GPIO_BIT1,
+ SPD_GPIO_BIT2
+ };
+ int spd_gpio[3];
+ int spd_index;
+ size_t spd_file_len;
+ char *spd_file;
+
+ spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+ spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+ spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+
+ spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
+
+ printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+ spd_index,
+ spd_bits[2], spd_gpio[2],
+ spd_bits[1], spd_gpio[1],
+ spd_bits[0], spd_gpio[0]);
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ memcpy(pei_data->spd_data[0][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+ /* Index 0-2 are 4GB config with both CH0 and CH1.
+ * Index 4-6 are 2GB config with CH0 only. */
+ if (spd_index > 3)
+ pei_data->dimm_channel1_disabled = 3;
+ else
+ memcpy(pei_data->spd_data[1][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+
+ /* Make sure a valid SPD was found */
+ if (pei_data->spd_data[0][0][0] == 0)
+ die("Invalid SPD data.");
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c
new file mode 100644
index 0000000..f1af14d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/variant.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <soc/romstage.h>
+#include <variant/onboard.h>
+#include <mainboard/google/auron/variant.h>
+
+int variant_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+void variant_romstage_entry(struct romstage_params *rp)
+{
+ /* N/A for boards other than SAMUS */
+}
diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb
new file mode 100644
index 0000000..9f086a6
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb
@@ -0,0 +1,110 @@
+chip soc/intel/broadwell
+
+ # Enable eDP Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Disable DisplayPort C Hotplug
+ register "gpu_dp_c_hotplug" = "0x00"
+
+ # Enable HDMI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000000"
+
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "400" # 40ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
+
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "1"
+
+ register "sio_acpi_mode" = "1"
+
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+
+ # Force enable ASPM for PCIe Port1
+ register "pcie_port_force_aspm" = "0x01"
+
+ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013c0000"
+
+ register "s0ix_enable" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
+ end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..1f91456
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C0)
+{
+ Device (STPA)
+ {
+ Name (_HID, "SYNA0000")
+ Name (_CID, "ACPI0C50")
+ Name (_DDN, "Synaptics Touchpad")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+
+ Method(_CRS, 0x0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+ Return(RBUF)
+ }
+
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) /* I2C-HID UUID */
+ {
+ If (LEqual(Arg2, Zero)) /* DSM Function */
+ {
+ /* Function 0: Query function, return based on revision */
+ If (LEqual(Arg1, One)) /* Arg1 DSM Revision */
+ {
+ /* Revision 1: Function 0 supported */
+ Return(Buffer(One) { 0x03 })
+ }
+ } ElseIf (LEqual(Arg2, One)) /* Function 1 : HID Function */
+ {
+ Return(0x0020) /* HID Descriptor Address */
+ }
+ }
+
+ Return(Buffer(One) { 0x00 }) /* Not supported */
+ }
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+Scope (\_SB.PCI0.I2C1)
+{
+ Device (ETSA)
+ {
+ Name (_HID, "ELAN0001")
+ Name (_DDN, "Elan Touchscreen")
+ Name (_UID, 6)
+ Name (ISTP, 0) /* Touchscreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h b/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h
new file mode 100644
index 0000000..726dcc7
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Sage Electronic Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef LULU_GPIO_H
+#define LULU_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_INPUT, /* 8: RAM_ID4 */
+ PCH_GPIO_INPUT, /* 9: RAM_ID1 */
+ PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
+ PCH_GPIO_UNUSED, /* 11: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
+ PCH_GPIO_INPUT, /* 13: RAM_ID0 */
+ PCH_GPIO_INPUT, /* 14: EC_IN_RW */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 16: UNUSED */
+ PCH_GPIO_UNUSED, /* 17: UNUSED */
+ PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_UNUSED, /* 20: UNUSED */
+ PCH_GPIO_UNUSED, /* 21: UNUSED */
+ PCH_GPIO_UNUSED, /* 22: UNUSED */
+ PCH_GPIO_UNUSED, /* 23: UNUSED */
+ PCH_GPIO_UNUSED, /* 24: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
+ PCH_GPIO_UNUSED, /* 26: UNUSED */
+ PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_UNUSED, /* 28: UNUSED */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
+ PCH_GPIO_UNUSED, /* 41: UNUSED */
+ PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
+ PCH_GPIO_UNUSED, /* 43: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
+ PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
+ PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
+ PCH_GPIO_INPUT, /* 47: RAM_ID2 */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_UNUSED, /* 49: UNUSED */
+ PCH_GPIO_UNUSED, /* 50: UNUSED */
+ PCH_GPIO_UNUSED, /* 51: UNUSED */
+ PCH_GPIO_UNUSED, /* 52: UNUSED */
+ PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
+ PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_UNUSED, /* 56: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
+ PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
+ PCH_GPIO_UNUSED, /* 59: UNUSED */
+ PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
+ PCH_GPIO_UNUSED, /* 61: UNUSED */
+ PCH_GPIO_UNUSED, /* 62: UNUSED */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
+ PCH_GPIO_UNUSED, /* 65: UNUSED */
+ PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 67: UNUSED */
+ PCH_GPIO_UNUSED, /* 68: UNUSED */
+ PCH_GPIO_UNUSED, /* 69: UNUSED */
+ PCH_GPIO_UNUSED, /* 70: UNUSED */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
+ PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
+ PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
+ PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_UNUSED, /* 83: UNUSED */
+ PCH_GPIO_UNUSED, /* 84: UNUSED */
+ PCH_GPIO_UNUSED, /* 85: UNUSED */
+ PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_UNUSED, /* 89: UNUSED */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_UNUSED, /* 91: UNUSED */
+ PCH_GPIO_UNUSED, /* 92: UNUSED */
+ PCH_GPIO_UNUSED, /* 93: UNUSED */
+ PCH_GPIO_UNUSED, /* 94: UNUSED */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h
new file mode 100644
index 0000000..a214a50
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
+ 0x10ec0283, // Subsystem ID
+ 0x0000000e, // Number of jacks (NID entries)
+
+ 0x0017ff00, // Function Reset
+ 0x0017ff00, // Double Function Reset
+ 0x000F0000, // Pad - get vendor id
+ 0x000F0002, // Pad - get revision id
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table */
+ AZALIA_SUBVENDOR(0x0, 0x11790670),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) DMIC - Internal MIC */
+ // group 3, cap 0
+ // no connector, no jack detect
+ // mic in, digital
+ // fixed function, internal
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
+
+ /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
+ // group 1, cap 0
+ // no connector, no jack detect
+ // speaker out, analog
+ // fixed function, internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+ /* Pin Complex (NID 0x17) MONO Out - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+ /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
+ // group2, cap 0
+ // black, jack detect
+ // Mic in, 3.5mm Jack
+ // connector, External left panel
+ AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
+
+ /* Pin Complex (NID 0x1A) LINE1 - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) LINE2 - Disabled */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) PCBeep */
+ // eapd low on ex-amp, laptop, custom enable
+ // mute spkr on hpout
+ // pcbeep en able, checksum
+ // no physical, Internal, Location N/A
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
+
+ /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
+ // group2, cap 1
+ // black, jack detect
+ // HPOut, 3.5mm Jack
+ // connector, left panel
+ AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
+
+ /* Undocumented settings from Realtek (needed for beep_gen) */
+ /* Widget node 0x20 */
+ 0x02050010,
+ 0x02040c20,
+ 0x0205001b,
+ 0x0204081b,
+
+ /* Tuned jack detection */
+ 0x02050043,
+ 0x0204A614,
+ 0x02050047,
+ 0x02049470,
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up everything (codec, dac, adc, mixers) */
+ 0x01470740, /* enable speaker out */
+ 0x01470c02, /* set speaker EAPD pin */
+ 0x0143b01f, /* unmute speaker */
+ 0x00c37100, /* unmute mixer nid 0xc input 1 */
+ 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h
new file mode 100644
index 0000000..0adc589
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
+#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
+#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
+#define BOARD_TRACKPAD_I2C_ADDR 0x2C
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */
+#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */
+#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
+
+#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
+#define BOARD_PP3300_CODEC_GPIO 45 /* GPIO45 */
+#define BOARD_WLAN_DISABLE_GPIO 46 /* GPIO46 */
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h
new file mode 100644
index 0000000..a7df6f4
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Sage Electronic Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+/* Lulu board memory configuration GPIOs */
+#define SPD_GPIO_BIT0 13
+#define SPD_GPIO_BIT1 9
+#define SPD_GPIO_BIT2 47
+#define SPD_GPIO_BIT3 8
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h
new file mode 100644
index 0000000..0b66c0b
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID 0 /* PECI */
+#define CTL_TDP_POWER_LIMIT 12 /* 12W */
+#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
+#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
+#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 105
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c
new file mode 100644
index 0000000..be7626c
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/pei_data.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel -- can be changed by SPD init */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ /* P0: Port B, CN01 (IOBoard) */
+ pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P1: Port A, CN01 */
+ pei_data_usb2_port(pei_data, 1, 0x0040, 1, 2,
+ USB_PORT_BACK_PANEL);
+ /* P2: CCD */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P3: BT */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P4: Empty */
+ pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P5: EMPTY */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: SD Card */
+ pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FLEX);
+ /* P7: EMPTY */
+ pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+
+ /* P0: PORTB*/
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P1: PORTA */
+ pei_data_usb3_port(pei_data, 1, 1, 2, 0);
+ /* P2: EMPTY */
+ pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+ /* P3: EMPTY */
+ pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc
new file mode 100644
index 0000000..8429f9c
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc
@@ -0,0 +1,51 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Sage Electronic Engineering
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO47, GPIO9, GPIO13, GPIO8}
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 # 0b0000 2GB
+SPD_SOURCES += empty # 0b0001
+SPD_SOURCES += empty # 0b0010
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b0011 2GB
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 # 0b0100 2GB
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 # 0b0101 4GB
+SPD_SOURCES += empty # 0b0110
+SPD_SOURCES += empty # 0b0111
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 # 0b1000 4GB
+SPD_SOURCES += micron_4GiB_dimm_MT41K512M16TNA-125 # 0b1001 8GB
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA # 0b1010 2GB
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA # 0b1011 4GB
+SPD_SOURCES += hynix_4GiB_dimm_H5TC8G63CMR-PBA # 0b1100 8GB
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b1101 4GB
+SPD_SOURCES += samsung_4GiB_dimm_K4B8G1646Q-MYK0 # 0b1110 8GB
+SPD_SOURCES += empty # 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex
new file mode 100644
index 0000000..e83f7e8
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000..ebb10f3
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex
new file mode 100644
index 0000000..3239846
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex
@@ -0,0 +1,33 @@
+# H5TC8G63CMR-PBA
+92 13 0b 03 04 19 02 0a
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 80 00 00 00 00 00 00
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 1f 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 b2 a3
+48 4d 54 38 35 31 53 36
+43 4d 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
new file mode 100644
index 0000000..91d816d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+20 08 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 19 d2
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex
new file mode 100644
index 0000000..0a27768
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex
@@ -0,0 +1,33 @@
+# MT41K512M16TNA-125:E
+92 11 0b 03 04 19 02 0A
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 05
+00 80 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 7f c1
+38 4b 54 53 35 31 32 36
+34 48 44 5a 2d 31 47 36
+45 31 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
new file mode 100644
index 0000000..5937a88
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646E-BYK0
+92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F
+4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
new file mode 100644
index 0000000..d6b0770
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646Q-HYK0
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex
new file mode 100644
index 0000000..4e7d8e4
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B8G1646Q-MYK0
+92 12 0B 03 04 19 02 0A 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 80 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 1F 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00
+4D 34 37 31 42 35 31 37 34 51 4D 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c
new file mode 100644
index 0000000..ac99f5c
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Sage Electronic Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <variant/gpio.h>
+#include <variant/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+ , banks, ranks, rows, cols);
+ printk(BIOS_INFO, "density %d Mb\n", capmb);
+
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int spd_bits[4] = {
+ SPD_GPIO_BIT0,
+ SPD_GPIO_BIT1,
+ SPD_GPIO_BIT2,
+ SPD_GPIO_BIT3
+ };
+ int spd_gpio[4];
+ int spd_index;
+ size_t spd_file_len;
+ char *spd_file;
+
+ spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+ spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+ spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+ spd_gpio[3] = get_gpio(SPD_GPIO_BIT3);
+
+ spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) |
+ (spd_gpio[1] << 1) | spd_gpio[0];
+
+ printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+ spd_index,
+ spd_bits[3], spd_gpio[3],
+ spd_bits[2], spd_gpio[2],
+ spd_bits[1], spd_gpio[1],
+ spd_bits[0], spd_gpio[0]);
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+
+ /* CH0 */
+ memcpy(pei_data->spd_data[0][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+
+ /* CH1 not used in 2GB configurations */
+ if (!((spd_index == 0b0000) || (spd_index == 0b0011) ||
+ (spd_index == 0b1010))) {
+ memcpy(pei_data->spd_data[1][0],
+ spd_file + (spd_index * SPD_LEN), SPD_LEN);
+ }
+
+ /* Make sure a valid SPD was found */
+ if (pei_data->spd_data[0][0][0] == 0)
+ die("Invalid SPD data.");
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c
new file mode 100644
index 0000000..084d4d1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/variant.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <soc/romstage.h>
+#include <variant/onboard.h>
+#include <mainboard/google/auron/variant.h>
+
+int variant_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TOUCHSCREEN_NAME, /* name */
+ BOARD_TOUCHSCREEN_IRQ, /* instance */
+ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
+ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+void variant_romstage_entry(struct romstage_params *rp)
+{
+ /* N/A for boards other than SAMUS */
+}
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/samus/Makefile.inc b/src/mainboard/google/auron/variants/samus/Makefile.inc
new file mode 100644
index 0000000..6e776ff
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/Makefile.inc
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += board_version.c
+ramstage-y += board_version.c
diff --git a/src/mainboard/google/auron/variants/samus/board_version.c b/src/mainboard/google/auron/variants/samus/board_version.c
new file mode 100644
index 0000000..c45b84e
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/board_version.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include <variant/board_version.h>
+
+const char *samus_board_version(void)
+{
+ switch (google_chromeec_get_board_version()) {
+ case SAMUS_EC_BOARD_VERSION_EVT1:
+ return "EVT1";
+ case SAMUS_EC_BOARD_VERSION_EVT2:
+ return "EVT2";
+ case SAMUS_EC_BOARD_VERSION_EVT3:
+ return "EVT3";
+ case SAMUS_EC_BOARD_VERSION_EVT4:
+ return "EVT4";
+ default:
+ return "Unknown";
+ }
+}
diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb
new file mode 100644
index 0000000..d12762d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/devicetree.cb
@@ -0,0 +1,112 @@
+chip soc/intel/broadwell
+
+ # Enable eDP Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable DDI1 Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ # Enable DDI2 Hotplug with 6ms pulse
+ register "gpu_dp_c_hotplug" = "0x06"
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000200"
+ register "gpu_pch_backlight" = "0x04000200"
+
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "6" # 500ms
+ register "gpu_panel_power_up_delay" = "2000" # 200ms
+ register "gpu_panel_power_down_delay" = "500" # 50ms
+ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
+ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
+
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
+
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sata_port0_gen3_tx" = "0x72"
+ register "sio_acpi_mode" = "1"
+
+ # Set I2C0 to 1.8V
+ register "sio_i2c0_voltage" = "1"
+
+ # Force enable ASPM for PCIe Port 3
+ register "pcie_port_force_aspm" = "0x04"
+ register "pcie_port_coalesce" = "1"
+
+ # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013b0000"
+
+ # Disable S0ix for now
+ register "s0ix_enable" = "0"
+
+ register "vr_slow_ramp_rate_set" = "3"
+ register "vr_slow_ramp_rate_enable" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 on end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 on end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 off end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 off end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
+ end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..40a4df0
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl
@@ -0,0 +1,247 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#undef ENABLE_TOUCH_WAKE
+
+Scope (\_SB.PCI0.I2C0)
+{
+ Device (ATPA)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad")
+ Name (_UID, 2)
+ Name (_S0W, 4)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
+
+ // GPIO13 is PIRQL
+ Interrupt (ResourceConsumer, Level, ActiveLow) { 27 }
+ })
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+
+ Device (CODC)
+ {
+ /*
+ * TODO(kane): Need official HID.
+ *
+ */
+ Name (_HID, "RT5677CE")
+ Name (_DDN, "RT5667 Codec")
+ Name (_UID, 1)
+
+ Name (MB1, 1) /* MICBIAS1 = 2.970V */
+ Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */
+ Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
+ Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
+ Name (IN1, 1) /* IN1 differential */
+ Name (IN2, 0) /* IN2 not differential */
+ Name (OUT1, 1) /* LOUT1 differential */
+ Name (OUT2, 1) /* LOUT2 differential */
+ Name (OUT3, 0) /* LOUT3 differential */
+ Name (ASRC, 1) /* Enable I2S1 ASRC */
+ Name (JD1, 0) /* JackDetect1 is not used */
+ Name (JD2, 2) /* Use GPIO5 as JackDetect2 */
+ Name (JD3, 3) /* Use GPIO6 as JackDetect3 */
+
+ /* Add DT style bindings with _DSD */
+ Name (_DSD, Package () {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "realtek,micbias1", 1 },
+ Package () { "realtek,internal-dacref-en", 1 },
+ Package () { "realtek,in1-differential", 1 },
+ Package () { "realtek,in2-differential", 0 },
+ Package () { "realtek,lout1-differential", 1 },
+ Package () { "realtek,lout2-differential", 1 },
+ Package () { "realtek,lout3-differential", 0 },
+ Package () { "realtek,pdm_clk_div", 1 },
+ Package () { "realtek,dmic2_clk_pin", 0 },
+ Package () { "realtek,asrc-en", 1 },
+ Package () { "realtek,jd1-gpio", 0 },
+ Package () { "realtek,jd2-gpio", 2 },
+ Package () { "realtek,jd3-gpio", 3 },
+ Package () { "realtek,gpio-config",
+ Package () { 0, 0, 0, 0, 0, 2 } },
+ }
+ })
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_CODEC_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
+
+ /* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */
+ Interrupt (ResourceConsumer, Edge, ActiveHigh) { 30 }
+
+ /*
+ * Codec GPIOs are 1-based in the schematic
+ *
+ * [0] = Jack Detect (INPUT)
+ * [1] = Mic Present (INPUT)
+ * [2] = Interrupt to the host (OUTPUT)
+ * [3] = Interrupt to the host (OUTPUT)
+ * [4] = Headphone amp control (OUTPUT)
+ */
+
+ /* Index 0: Jack Detect - PLUG_DET is GPIO5 */
+ GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly,
+ "\\_SB.PCI0.I2C0.CODC") { 4 }
+
+ /* Index 1: Mic Present - MIC_PRESENT_L is GPIO6 */
+ GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly,
+ "\\_SB.PCI0.I2C0.CODC") { 5 }
+
+ /* Index 2: Codec IRQ - HOTWORD_DET_L is GPIO1 */
+ GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly,
+ "\\_SB.PCI0.I2C0.CODC") { 0 }
+
+ /* Index 3: Codec Wake - DSP_INT is GPIO4 */
+ GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly,
+ "\\_SB.PCI0.I2C0.CODC") { 3 }
+
+ /* Index 4: Headphone amp - HP_AMP_SHDN_L is GPIO2 */
+ GpioIo (Exclusive, PullDown, , , IoRestrictionOutputOnly,
+ "\\_SB.PCI0.I2C0.CODC") { 1 }
+ })
+
+ Name (_PRW, Package() { BOARD_CODEC_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_CODEC_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.PCI0.I2C1)
+{
+ Device (ATSA)
+ {
+ Name (_HID, "ATML0001")
+ Name (_DDN, "Atmel Touchscreen")
+ Name (_UID, 5)
+ Name (_S0W, 4)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C1", // ResourceSource
+ )
+
+ // GPIO14 is PIRQM
+ Interrupt (ResourceConsumer, Level, ActiveLow) { 28 }
+ })
+
+#ifdef ENABLE_TOUCH_WAKE
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_CODEC_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+#endif
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.PCI0.SPI0)
+{
+ Device (CODC)
+ {
+ // TODO: Need official HID.
+ Name (_HID, "RT5677AA")
+ Name (_UID, 1)
+ Name (_CRS, ResourceTemplate ()
+ {
+ SpiSerialBus (
+ 0, // DeviceSelection (CS0?)
+ PolarityLow, // DeviceSelectionPolarity
+ FourWireMode, // WireMode
+ 8, // DataBitLength
+ ControllerInitiated, // SlaveMode
+ 1000000, // ConnectionSpeed (1MHz)
+ ClockPolarityLow, // ClockPolarity
+ ClockPhaseFirst, // ClockPhase
+ "\\_SB.PCI0.SPI0", // ResourceSource
+ 0, // ResourceSourceIndex
+ ResourceConsumer, // ResourceUsage
+ )
+ })
+ }
+}
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/board_version.h b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h
new file mode 100644
index 0000000..f5371a1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SAMUS_BOARD_VERSION_H
+#define SAMUS_BOARD_VERSION_H
+
+#define SAMUS_EC_BOARD_VERSION_EVT1 3
+#define SAMUS_EC_BOARD_VERSION_EVT2 4
+#define SAMUS_EC_BOARD_VERSION_EVT3 5
+#define SAMUS_EC_BOARD_VERSION_EVT4 0
+
+const char *samus_board_version(void);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h b/src/mainboard/google/auron/variants/samus/include/variant/gpio.h
new file mode 100644
index 0000000..8362a4d
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SAMUS_GPIO_H
+#define SAMUS_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
+ PCH_GPIO_INPUT_INVERT, /* 9: TRACKPAD_INT_L (WAKE) */
+ PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
+ PCH_GPIO_UNUSED, /* 11: UNUSED */
+ PCH_GPIO_UNUSED, /* 12: UNUSED */
+ PCH_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */
+ PCH_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_INPUT, /* 16: PCH_WP */
+ PCH_GPIO_UNUSED, /* 17: UNUSED */
+ PCH_GPIO_UNUSED, /* 18: UNUSED */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */
+ PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */
+ PCH_GPIO_UNUSED, /* 22: UNUSED */
+ PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */
+ PCH_GPIO_UNUSED, /* 24: UNUSED */
+ PCH_GPIO_INPUT, /* 25: EC_IN_RW */
+ PCH_GPIO_UNUSED, /* 26: UNUSED */
+ PCH_GPIO_ACPI_SCI, /* 27: PCH_WAKE_L */
+ PCH_GPIO_UNUSED, /* 28: UNUSED */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */
+ PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
+ PCH_GPIO_UNUSED, /* 42: WLAN_DISABLE_L */
+ PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */
+ PCH_GPIO_UNUSED, /* 44: UNUSED */
+ PCH_GPIO_ACPI_SCI, /* 45: DSP_INT - Codec Wake */
+ PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L_3V3 (PIRQO) - Codec IRQ */
+ PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_UNUSED, /* 49: UNUSED */
+ PCH_GPIO_UNUSED, /* 50: UNUSED */
+ PCH_GPIO_UNUSED, /* 51: UNUSED */
+ PCH_GPIO_INPUT, /* 52: SIM_DET */
+ PCH_GPIO_UNUSED, /* 53: UNUSED */
+ PCH_GPIO_UNUSED, /* 54: UNUSED */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_UNUSED, /* 56: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */
+ PCH_GPIO_UNUSED, /* 58: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
+ PCH_GPIO_UNUSED, /* 60: UNUSED */
+ PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
+ PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
+ PCH_GPIO_INPUT, /* 65: RAM_ID3 */
+ PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */
+ PCH_GPIO_INPUT, /* 67: RAM_ID0 */
+ PCH_GPIO_INPUT, /* 68: RAM_ID1 */
+ PCH_GPIO_INPUT, /* 69: RAM_ID2 */
+ PCH_GPIO_UNUSED, /* 70: UNUSED */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_UNUSED, /* 72: UNUSED */
+ PCH_GPIO_UNUSED, /* 73: UNUSED */
+ PCH_GPIO_UNUSED, /* 74: UNUSED */
+ PCH_GPIO_UNUSED, /* 75: UNUSED */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_UNUSED, /* 81: UNUSED */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_NATIVE, /* 83: GSPI0_CS */
+ PCH_GPIO_NATIVE, /* 84: GSPI0_CLK */
+ PCH_GPIO_NATIVE, /* 85: GSPI0_MISO */
+ PCH_GPIO_NATIVE, /* 86: GSPI0_MOSI (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_UNUSED, /* 91: UNUSED */
+ PCH_GPIO_UNUSED, /* 92: UNUSED */
+ PCH_GPIO_UNUSED, /* 93: UNUSED */
+ PCH_GPIO_UNUSED, /* 94: UNUSED */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h
new file mode 100644
index 0000000..5d08879
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/onboard.h b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h
new file mode 100644
index 0000000..dcbfc6e
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define BOARD_TRACKPAD_I2C_ADDR 0x4a
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4b
+#define BOARD_CODEC_I2C_ADDR 0x2c
+
+#define BOARD_TRACKPAD_WAKE_GPIO 9 /* GPIO9 */
+#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */
+#define BOARD_TOUCHSCREEN_WAKE_GPIO 14 /* GPIO14 */
+#define BOARD_PP3300_AUTOBAHN_GPIO 23 /* GPIO23 */
+#define BOARD_WLAN_DISABLE_GPIO 42 /* GPIO42 */
+#define BOARD_CODEC_WAKE_GPIO 45 /* GPIO45 */
+#define BOARD_SSD_RESET_GPIO 47 /* GPIO47 */
+#define BOARD_LTE_DISABLE_GPIO 59 /* GPIO59 */
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h
new file mode 100644
index 0000000..da48521
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/spd.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+/* Samus board memory configuration GPIOs */
+#define SPD_GPIO_BIT0 69
+#define SPD_GPIO_BIT1 68
+#define SPD_GPIO_BIT2 67
+#define SPD_GPIO_BIT3 65
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/thermal.h b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h
new file mode 100644
index 0000000..7168d93
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+#define CTL_TDP_SENSOR_ID 0 /* PECI */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 105
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c
new file mode 100644
index 0000000..051653f
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/pei_data.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* DQ byte map for Samus board */
+ const u8 dq_map[2][6][2] = {
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+ /* DQS CPU<>DRAM map for Samus board */
+ const u8 dqs_map[2][8] = {
+ { 2, 0, 1, 3, 6, 4, 7, 5 },
+ { 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+ /* P0: HOST PORT */
+ pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P1: HOST PORT */
+ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+ USB_PORT_BACK_PANEL);
+ /* P2: RAIDEN */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_BACK_PANEL);
+ /* P3: SD CARD */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P4: RAIDEN */
+ pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_BACK_PANEL);
+ /* P5: WWAN (Disabled) */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: CAMERA */
+ pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P7: BT */
+ pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+
+ /* P1: HOST PORT */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: HOST PORT */
+ pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+ /* P3: RAIDEN */
+ pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+ /* P4: RAIDEN */
+ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc
new file mode 100644
index 0000000..07c7f01
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc
@@ -0,0 +1,50 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO65, GPIO67, GPIO68, GPIO69 }
+SPD_SOURCES = empty # 0b0000
+SPD_SOURCES += empty # 0b0001
+SPD_SOURCES += empty # 0b0010
+SPD_SOURCES += empty # 0b0011
+SPD_SOURCES += empty # 0b0100
+SPD_SOURCES += empty # 0b0101
+SPD_SOURCES += samsung_4 # 0b0110
+SPD_SOURCES += empty # 0b0111
+SPD_SOURCES += hynix_4 # 0b1000
+SPD_SOURCES += empty # 0b1001
+SPD_SOURCES += samsung_8 # 0b1010
+SPD_SOURCES += empty # 0b1011
+SPD_SOURCES += hynix_8 # 0b1100
+SPD_SOURCES += hynix_16 # 0b1101
+SPD_SOURCES += empty # 0b1110
+SPD_SOURCES += elpida_16 # 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex b/src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex
new file mode 100644
index 0000000..5594164
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex
@@ -0,0 +1,18 @@
+# Elpida EDFB232A1MA
+# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16
+91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00
+45 44 46 42 32 33 32 41 31 4D 41 2D 47 44 2D 46
+00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex b/src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex
new file mode 100644
index 0000000..e73ba62
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex
@@ -0,0 +1,16 @@
+92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00
+45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46
+20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex b/src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex
new file mode 100644
index 0000000..b790943
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex
@@ -0,0 +1,16 @@
+92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00
+45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46
+20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/empty.spd.hex b/src/mainboard/google/auron/variants/samus/spd/empty.spd.hex
new file mode 100644
index 0000000..9ec39f1
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex b/src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex
new file mode 100644
index 0000000..a03d4ed
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex
@@ -0,0 +1,18 @@
+# Hynix H9CCNNNCLTMLAR LPDDR3
+# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16
+91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00
+00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex b/src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex
new file mode 100644
index 0000000..93e65a7
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex
@@ -0,0 +1,18 @@
+# Hynix H9CCNNNBLTMLAR-NTM LPDDR3
+# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32
+91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
+54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex b/src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex
new file mode 100644
index 0000000..15737e4
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex
@@ -0,0 +1,18 @@
+# Hynix H9CCNNNBLTMLAR-NTM LPDDR3
+# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16
+91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
+54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex b/src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex
new file mode 100644
index 0000000..4b82a3a
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
+4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex b/src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex
new file mode 100644
index 0000000..c0a8fca
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
+4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c
new file mode 100644
index 0000000..dd632f3
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/spd/spd.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <variant/gpio.h>
+#include <variant/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+ "density %d Mb\n", banks, ranks, rows, cols, capmb);
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int spd_bits[4] = {
+ SPD_GPIO_BIT0,
+ SPD_GPIO_BIT1,
+ SPD_GPIO_BIT2,
+ SPD_GPIO_BIT3
+ };
+ int spd_gpio[4];
+ int spd_index;
+ size_t spd_file_len;
+ char *spd_file;
+
+ spd_gpio[0] = get_gpio(spd_bits[0]);
+ spd_gpio[1] = get_gpio(spd_bits[1]);
+ spd_gpio[2] = get_gpio(spd_bits[2]);
+ spd_gpio[3] = get_gpio(spd_bits[3]);
+
+ spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) |
+ (spd_gpio[1] << 1) | spd_gpio[0];
+
+ printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d "
+ "GPIO%d=%d GPIO%d=%d)\n", spd_index,
+ spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2],
+ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]);
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ /* Assume same memory in both channels */
+ spd_index *= SPD_LEN;
+ memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
+ memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
+
+ /* Make sure a valid SPD was found */
+ if (pei_data->spd_data[0][0][0] == 0)
+ die("Invalid SPD data.");
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c
new file mode 100644
index 0000000..e711b60
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/variant.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <smbios.h>
+#include <variant/board_version.h>
+#include <variant/onboard.h>
+#include <mainboard/google/auron/variant.h>
+
+const char *smbios_mainboard_version(void)
+{
+ return samus_board_version();
+}
+
+int variant_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ /* N/A for SAMUS */
+ return 0;
+}
+
+void variant_romstage_entry(struct romstage_params *rp)
+{
+ if (rp->power_state->prev_sleep_state != ACPI_S3)
+ google_chromeec_kbbacklight(100);
+
+ printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
+
+ /* Bring SSD out of reset */
+ set_gpio(BOARD_SSD_RESET_GPIO, GPIO_OUT_HIGH);
+
+ /*
+ * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
+ * to prevent possible brownout.
+ */
+ set_gpio(BOARD_PP3300_AUTOBAHN_GPIO, GPIO_OUT_HIGH);
+}
\ No newline at end of file
diff --git a/src/mainboard/google/auron_paine/Kconfig b/src/mainboard/google/auron_paine/Kconfig
deleted file mode 100644
index 147f37d..0000000
--- a/src/mainboard/google/auron_paine/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-if BOARD_GOOGLE_AURON_PAINE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select SOC_INTEL_BROADWELL
- select BOARD_ROMSIZE_KB_8192
- select EC_GOOGLE_CHROMEEC
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_RESUME
- select HAVE_SMI_HANDLER
- select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_LPC_TPM
- select INTEL_INT15
-
-config CHROMEOS
- select EC_GOOGLE_CHROMEEC_SWITCHES
- select EC_SOFTWARE_SYNC
- select CHROMEOS_RAMOOPS_DYNAMIC
- select LID_SWITCH
- select VBOOT_VBNV_CMOS
- select VIRTUAL_DEV_SWITCH
-
-config VBOOT_RAMSTAGE_INDEX
- hex
- default 0x2
-
-config VBOOT_REFCODE_INDEX
- hex
- default 0x3
-
-config MAINBOARD_DIR
- string
- default google/auron_paine
-
-config MAINBOARD_PART_NUMBER
- string
- default "Auron Paine"
-
-config IRQ_SLOT_COUNT
- int
- default 18
-
-config MAX_CPUS
- int
- default 8
-
-config VGA_BIOS_FILE
- string
- default "pci8086,0166.rom"
-
-config HAVE_IFD_BIN
- bool
- default n
-
-config HAVE_ME_BIN
- bool
- default n
-
-
-config MAINBOARD_FAMILY
- string
- depends on GENERATE_SMBIOS_TABLES
- default "Google_Auron"
-endif
diff --git a/src/mainboard/google/auron_paine/Kconfig.name b/src/mainboard/google/auron_paine/Kconfig.name
deleted file mode 100644
index 664315d..0000000
--- a/src/mainboard/google/auron_paine/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_AURON_PAINE
- bool "Auron_Paine"
diff --git a/src/mainboard/google/auron_paine/Makefile.inc b/src/mainboard/google/auron_paine/Makefile.inc
deleted file mode 100644
index c54c85e..0000000
--- a/src/mainboard/google/auron_paine/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-subdirs-y += spd
-
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-romstage-y += pei_data.c
-ramstage-y += pei_data.c
diff --git a/src/mainboard/google/auron_paine/acpi/ec.asl b/src/mainboard/google/auron_paine/acpi/ec.asl
deleted file mode 100644
index f7c8e27..0000000
--- a/src/mainboard/google/auron_paine/acpi/ec.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/auron_paine/ec.h>
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl b/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index 40658a9..0000000
--- a/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 18 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 22 },
- Package() { 0x001fffff, 1, 0, 18 },
- Package() { 0x001fffff, 2, 0, 17 },
- Package() { 0x001fffff, 3, 0, 16 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, 0, 20 },
- Package() { 0x0015ffff, 1, 0, 21 },
- Package() { 0x0015ffff, 2, 0, 21 },
- Package() { 0x0015ffff, 3, 0, 21 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, 0, 23 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/auron_paine/acpi/mainboard.asl b/src/mainboard/google/auron_paine/acpi/mainboard.asl
deleted file mode 100644
index fe68e30..0000000
--- a/src/mainboard/google/auron_paine/acpi/mainboard.asl
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <mainboard/google/auron_paine/onboard.h>
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name(_HID, EisaId("PNP0C0D"))
- Method(_LID, 0)
- {
- Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
- Return (\LIDS)
- }
-
-
- // There is no GPIO for LID, the EC pulses WAKE# pin instead.
- // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
- Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-}
-
-/*
- * LPC Trusted Platform Module
- */
-Scope (\_SB.PCI0.LPCB)
- {
- #include <drivers/pc80/tpm/acpi/tpm.asl>
-}
-
-Scope (\_SB.PCI0.I2C0)
-{
- Device (ETPA)
- {
- Name (_HID, "ELAN0000")
- Name (_DDN, "Elan Touchpad")
- Name (_UID, 1)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x15, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TRACKPAD_IRQ
- }
- })
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
- }
- }
-
- /* Allow device to power off in S0 */
- Name (_S0W, 4)
- }
-}
-
-Scope (\_SB.PCI0.RP01)
-{
- Device (WLAN)
- {
- Name (_ADR, 0x00000000)
-
- /* GPIO10 is WLAN_WAKE_L_Q */
- Name (GPIO, 10)
-
- Name (_PRW, Package() { GPIO, 3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
- }
- }
- }
-}
diff --git a/src/mainboard/google/auron_paine/acpi/platform.asl b/src/mainboard/google/auron_paine/acpi/platform.asl
deleted file mode 100644
index 1bd054d..0000000
--- a/src/mainboard/google/auron_paine/acpi/platform.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
- APMC, 8, // APM command
- APMS, 8 // APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
- DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) // SMI Function
- Store (0, TRP0) // Generate trap
- Return (SMIF) // Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
- // Remember the OS' IRQ routing choice.
- Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- /* Update AC status */
- Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
- if (LNotEqual (Local0, \PWRS)) {
- Store (Local0, \PWRS)
- Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
- }
-
- /* Update LID status */
- Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
- if (LNotEqual (Local0, \LIDS)) {
- Store (Local0, \LIDS)
- Notify (\_SB.LID0, 0x80)
- }
-
- Return(Package(){0,0})
-}
diff --git a/src/mainboard/google/auron_paine/acpi/superio.asl b/src/mainboard/google/auron_paine/acpi/superio.asl
deleted file mode 100644
index 07d6b23..0000000
--- a/src/mainboard/google/auron_paine/acpi/superio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/auron_paine/ec.h>
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/auron_paine/acpi/thermal.asl b/src/mainboard/google/auron_paine/acpi/thermal.asl
deleted file mode 100644
index 2221abc..0000000
--- a/src/mainboard/google/auron_paine/acpi/thermal.asl
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <mainboard/google/auron_paine/thermal.h>
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
- ThermalZone (THRM)
- {
- Name (_TC1, 0x02)
- Name (_TC2, 0x05)
-
- // Thermal zone polling frequency: 10 seconds
- Name (_TZP, 100)
-
- // Thermal sampling period for passive cooling: 2 seconds
- Name (_TSP, 20)
-
- // Convert from Degrees C to 1/10 Kelvin for ACPI
- Method (CTOK, 1) {
- // 10th of Degrees C
- Multiply (Arg0, 10, Local0)
-
- // Convert to Kelvin
- Add (Local0, 2732, Local0)
-
- Return (Local0)
- }
-
- // Threshold for OS to shutdown
- Method (_CRT, 0, Serialized)
- {
- Return (CTOK (\TCRT))
- }
-
- // Threshold for passive cooling
- Method (_PSV, 0, Serialized)
- {
- Return (CTOK (\TPSV))
- }
-
- // Processors used for passive cooling
- Method (_PSL, 0, Serialized)
- {
- Return (\PPKG ())
- }
-
- Method (TCHK, 0, Serialized)
- {
- // Get Temperature from TIN# set in NVS
- Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
-
- // Check for sensor not calibrated
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not present
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not powered
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
- Return (CTOK(0))
- }
-
- // Check for sensor bad reading
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
- Return (CTOK(0))
- }
-
- // Adjust by offset to get Kelvin
- Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
-
- // Convert to 1/10 Kelvin
- Multiply (Local0, 10, Local0)
- Return (Local0)
- }
-
- Method (_TMP, 0, Serialized)
- {
- // Get temperature from EC in deci-kelvin
- Store (TCHK (), Local0)
-
- // Critical temperature in deci-kelvin
- Store (CTOK (\TCRT), Local1)
-
- If (LGreaterEqual (Local0, Local1)) {
- Store ("CRITICAL TEMPERATURE", Debug)
- Store (Local0, Debug)
-
- // Wait 1 second for EC to re-poll
- Sleep (1000)
-
- // Re-read temperature from EC
- Store (TCHK (), Local0)
-
- Store ("RE-READ TEMPERATURE", Debug)
- Store (Local0, Debug)
- }
-
- Return (Local0)
- }
-
- /* CTDP Down */
- Method (_AC0) {
- If (LLessEqual (\FLVL, 0)) {
- Return (CTOK (CTL_TDP_THRESHOLD_OFF))
- } Else {
- Return (CTOK (CTL_TDP_THRESHOLD_ON))
- }
- }
-
- /* CTDP Nominal */
- Method (_AC1) {
- If (LLessEqual (\FLVL, 1)) {
- Return (CTOK (CTL_TDP_THRESHILD_NORMAL))
- } Else {
- Return (CTOK (CTL_TDP_THRESHILD_NORMAL))
- }
- }
-
- Name (_AL0, Package () { TDP0 })
- Name (_AL1, Package () { TDP1 })
-
- PowerResource (TNP0, 0, 0)
- {
- Method (_STA) {
- If (LLessEqual (\FLVL, 0)) {
- Return (One)
- } Else {
- Return (Zero)
- }
- }
- Method (_ON) {
- Store (0, \FLVL)
-
- /* Enable Power Limit */
- \_SB.PCI0.MCHC.CTLE (CTL_TDP_POWER_LIMIT)
-
- Notify (\_TZ.THRM, 0x81)
- }
- Method (_OFF) {
- Store (1, \FLVL)
-
- /* Disable Power Limit */
- \_SB.PCI0.MCHC.CTLD ()
-
- Notify (\_TZ.THRM, 0x81)
- }
- }
-
- PowerResource (TNP1, 0, 0)
- {
- Method (_STA) {
- If (LLessEqual (\FLVL, 1)) {
- Return (One)
- } Else {
- Return (Zero)
- }
- }
- Method (_ON) {
- Store (1, \FLVL)
- Notify (\_TZ.THRM, 0x81)
- }
- Method (_OFF) {
- Store (1, \FLVL)
- Notify (\_TZ.THRM, 0x81)
- }
- }
-
- Device (TDP0)
- {
- Name (_HID, EISAID ("PNP0C0B"))
- Name (_UID, 0)
- Name (_PR0, Package () { TNP0 })
- }
-
- Device (TDP1)
- {
- Name (_HID, EISAID ("PNP0C0B"))
- Name (_UID, 1)
- Name (_PR0, Package () { TNP1 })
- }
- }
-}
diff --git a/src/mainboard/google/auron_paine/acpi/video.asl b/src/mainboard/google/auron_paine/acpi/video.asl
deleted file mode 100644
index 6894655..0000000
--- a/src/mainboard/google/auron_paine/acpi/video.asl
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/google/auron_paine/acpi_tables.c b/src/mainboard/google/auron_paine/acpi_tables.c
deleted file mode 100644
index f6fc3fd..0000000
--- a/src/mainboard/google/auron_paine/acpi_tables.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include "thermal.h"
-
-const unsigned char *AmlCode;
-
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
- gnvs->tmps = CTL_TDP_SENSOR_ID;
-
- gnvs->tcrt = CRITICAL_TEMPERATURE;
- gnvs->tpsv = PASSIVE_TEMPERATURE;
- gnvs->tmax = MAX_TEMPERATURE;
- gnvs->flvl = 1;
-}
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- acpi_init_gnvs(gnvs);
-
- /* Enable USB ports in S3 */
- gnvs->s3u0 = 1;
-
- /* Disable USB ports in S5 */
- gnvs->s5u0 = 0;
-
- acpi_update_thermal_table(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- return acpi_madt_irq_overrides(current);
-}
diff --git a/src/mainboard/google/auron_paine/board_info.txt b/src/mainboard/google/auron_paine/board_info.txt
deleted file mode 100644
index 2c6971b..0000000
--- a/src/mainboard/google/auron_paine/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Auron Paine Broadwell chromebook
-Category: laptop
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/auron_paine/chromeos.c b/src/mainboard/google/auron_paine/chromeos.c
deleted file mode 100644
index 61b3e4e..0000000
--- a/src/mainboard/google/auron_paine/chromeos.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/gpio.h>
-
-/* SPI Write protect is GPIO 16 */
-#define CROS_WP_GPIO 58
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"},
- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-#endif
-
-int get_write_protect_state(void)
-{
- return get_gpio(CROS_WP_GPIO);
-}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
-}
diff --git a/src/mainboard/google/auron_paine/chromeos.fmd b/src/mainboard/google/auron_paine/chromeos.fmd
deleted file mode 100644
index 113fba6..0000000
--- a/src/mainboard/google/auron_paine/chromeos.fmd
+++ /dev/null
@@ -1,38 +0,0 @@
-FLASH@0xff800000 0x800000 {
- SI_ALL@0x0 0x200000 {
- SI_DESC@0x0 0x1000
- SI_ME@0x1000 0x1ff000
- }
- SI_BIOS@0x200000 0x600000 {
- RW_SECTION_A@0x0 0xf0000 {
- VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0xdffc0
- RW_FWID_A@0xeffc0 0x40
- }
- RW_SECTION_B@0xf0000 0xf0000 {
- VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0xdffc0
- RW_FWID_B@0xeffc0 0x40
- }
- RW_MRC_CACHE@0x1e0000 0x10000
- RW_ELOG@0x1f0000 0x4000
- RW_SHARED@0x1f4000 0x4000 {
- SHARED_DATA@0x0 0x2000
- VBLOCK_DEV@0x2000 0x2000
- }
- RW_VPD@0x1f8000 0x2000
- RW_UNUSED@0x1fa000 0x6000
- RW_LEGACY(CBFS)@0x200000 0x200000
- WP_RO@0x400000 0x200000 {
- RO_VPD@0x0 0x4000
- RO_UNUSED@0x4000 0xc000
- RO_SECTION@0x10000 0x1f0000 {
- FMAP@0x0 0x800
- RO_FRID@0x800 0x40
- RO_FRID_PAD@0x840 0x7c0
- GBB@0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x100000
- }
- }
- }
-}
diff --git a/src/mainboard/google/auron_paine/cmos.layout b/src/mainboard/google/auron_paine/cmos.layout
deleted file mode 100644
index b575e02..0000000
--- a/src/mainboard/google/auron_paine/cmos.layout
+++ /dev/null
@@ -1,110 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392 3 e 5 baud_rate
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: cpu
-400 1 e 2 hyper_threading
-#401 7 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416 128 r 0 vbnv
-#544 440 r 0 unused
-
-# SandyBridge MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 1 Emergency
-6 2 Alert
-6 3 Critical
-6 4 Error
-6 5 Warning
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/google/auron_paine/devicetree.cb b/src/mainboard/google/auron_paine/devicetree.cb
deleted file mode 100644
index 5872cf2..0000000
--- a/src/mainboard/google/auron_paine/devicetree.cb
+++ /dev/null
@@ -1,108 +0,0 @@
-chip soc/intel/broadwell
-
- # Enable eDP Hotplug with 6ms pulse
- register "gpu_dp_d_hotplug" = "0x06"
-
- # Disable DisplayPort C Hotplug
- register "gpu_dp_c_hotplug" = "0x00"
-
- # Enable HDMI Hotplug with 6ms pulse
- register "gpu_dp_b_hotplug" = "0x06"
-
- # Set backlight PWM values for eDP
- register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000000"
-
- # Enable Panel and configure power delays
- register "gpu_panel_port_select" = "1" # eDP
- register "gpu_panel_power_cycle_delay" = "5" # 400ms
- register "gpu_panel_power_up_delay" = "400" # 40ms
- register "gpu_panel_power_down_delay" = "150" # 15ms
- register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
- register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
-
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
-
- register "sata_port_map" = "0x1"
- register "sio_acpi_mode" = "1"
-
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
-
- # Force enable ASPM for PCIe Port1
- register "pcie_port_force_aspm" = "0x01"
-
- # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013c0000"
-
- register "s0ix_enable" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- device domain 0 on
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
- device pci 13.0 off end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 on end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
- end
- chip ec/google/chromeec
- device pnp 0c09.0 on end
- end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 off end # SMBus
- device pci 1f.6 on end # Thermal
- end
-end
diff --git a/src/mainboard/google/auron_paine/dsdt.asl b/src/mainboard/google/auron_paine/dsdt.asl
deleted file mode 100644
index 531d6a7..0000000
--- a/src/mainboard/google/auron_paine/dsdt.asl
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0
- "COREv4", // OEM id
- "COREBOOT", // OEM table id
- 0x20110725 // OEM revision
-)
-{
- // Some generic macros
- #include <soc/intel/broadwell/acpi/platform.asl>
-
- // global NVS and variables
- #include <soc/intel/broadwell/acpi/globalnvs.asl>
-
- // General Purpose Events
- //#include "acpi/gpe.asl"
-
- // CPU
- #include <soc/intel/broadwell/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/broadwell/acpi/systemagent.asl>
- #include <soc/intel/broadwell/acpi/pch.asl>
- }
- }
-
- // Thermal handler
- #include "acpi/thermal.asl"
-
- // Chrome OS specific
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
- // Chipset specific sleep states
- #include <soc/intel/broadwell/acpi/sleepstates.asl>
-
- // Mainboard specific
- #include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/google/auron_paine/ec.c b/src/mainboard/google/auron_paine/ec.c
deleted file mode 100644
index 5feafb8..0000000
--- a/src/mainboard/google/auron_paine/ec.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <types.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-void mainboard_ec_init(void)
-{
- printk(BIOS_DEBUG, "mainboard_ec_init\n");
- post_code(0xf0);
-
- /* Restore SCI event mask on resume. */
- if (acpi_is_wakeup_s3()) {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S3_WAKE_EVENTS);
-
- /* Disable SMI and wake events */
- google_chromeec_set_smi_mask(0);
-
- /* Clear pending events */
- while (google_chromeec_get_event() != 0)
- ;
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- } else {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S5_WAKE_EVENTS);
- }
-
- /* Clear wake events, these are enabled on entry to sleep */
- google_chromeec_set_wake_mask(0);
-
- post_code(0xf1);
-}
diff --git a/src/mainboard/google/auron_paine/ec.h b/src/mainboard/google/auron_paine/ec.h
deleted file mode 100644
index 9bfb555..0000000
--- a/src/mainboard/google/auron_paine/ec.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-
-#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
-#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
-
-#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* EC can wake from S3 with lid or power button or key press */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
- (MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
-
-#endif
diff --git a/src/mainboard/google/auron_paine/fadt.c b/src/mainboard/google/auron_paine/fadt.c
deleted file mode 100644
index 570689b..0000000
--- a/src/mainboard/google/auron_paine/fadt.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- memset((void *) fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 5;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 1;
-
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
- fadt->model = 1;
- fadt->preferred_pm_profile = PM_MOBILE;
-
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- acpi_fill_in_fadt(fadt);
-
- header->checksum =
- acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/google/auron_paine/gpio.h b/src/mainboard/google/auron_paine/gpio.h
deleted file mode 100644
index 667f977..0000000
--- a/src/mainboard/google/auron_paine/gpio.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AURON_PAINE_GPIO_H
-#define AURON_PAINE_GPIO_H
-
-#include <soc/gpio.h>
-
-static const struct gpio_config mainboard_gpio_config[] = {
- PCH_GPIO_UNUSED, /* 0: UNUSED */
- PCH_GPIO_UNUSED, /* 1: UNUSED */
- PCH_GPIO_UNUSED, /* 2: UNUSED */
- PCH_GPIO_UNUSED, /* 3: UNUSED */
- PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
- PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
- PCH_GPIO_UNUSED, /* 6: UNUSED */
- PCH_GPIO_UNUSED, /* 7: UNUSED */
- PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
- PCH_GPIO_INPUT, /* 9: RAM_ID1 */
- PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
- PCH_GPIO_UNUSED, /* 11: UNUSED */
- PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
- PCH_GPIO_INPUT, /* 13: RAM_ID0 */
- PCH_GPIO_INPUT, /* 14: EC_IN_RW */
- PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 16: UNUSED */
- PCH_GPIO_UNUSED, /* 17: UNUSED */
- PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
- PCH_GPIO_UNUSED, /* 19: UNUSED */
- PCH_GPIO_UNUSED, /* 20: UNUSED */
- PCH_GPIO_UNUSED, /* 21: UNUSED */
- PCH_GPIO_UNUSED, /* 22: UNUSED */
- PCH_GPIO_UNUSED, /* 23: UNUSED */
- PCH_GPIO_UNUSED, /* 24: UNUSED */
- PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
- PCH_GPIO_UNUSED, /* 26: UNUSED */
- PCH_GPIO_UNUSED, /* 27: UNUSED */
- PCH_GPIO_UNUSED, /* 28: UNUSED */
- PCH_GPIO_UNUSED, /* 29: UNUSED */
- PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
- PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
- PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
- PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
- PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
- PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
- PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
- PCH_GPIO_UNUSED, /* 37: UNUSED */
- PCH_GPIO_UNUSED, /* 38: UNUSED */
- PCH_GPIO_UNUSED, /* 39: UNUSED */
- PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
- PCH_GPIO_UNUSED, /* 41: UNUSED */
- PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
- PCH_GPIO_UNUSED, /* 43: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
- PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
- PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
- PCH_GPIO_INPUT, /* 47: RAM_ID2 */
- PCH_GPIO_UNUSED, /* 48: UNUSED */
- PCH_GPIO_UNUSED, /* 49: UNUSED */
- PCH_GPIO_UNUSED, /* 50: UNUSED */
- PCH_GPIO_INPUT, /* 51: ALS_INT_L */
- PCH_GPIO_INPUT, /* 52: SIM_DET */
- PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
- PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
- PCH_GPIO_UNUSED, /* 55: UNUSED */
- PCH_GPIO_UNUSED, /* 56: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
- PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
- PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
- PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
- PCH_GPIO_UNUSED, /* 61: UNUSED */
- PCH_GPIO_UNUSED, /* 62: UNUSED */
- PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- PCH_GPIO_UNUSED, /* 64: UNUSED */
- PCH_GPIO_UNUSED, /* 65: UNUSED */
- PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 67: UNUSED */
- PCH_GPIO_UNUSED, /* 68: UNUSED */
- PCH_GPIO_UNUSED, /* 69: UNUSED */
- PCH_GPIO_UNUSED, /* 70: UNUSED */
- PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
- PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
- PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
- PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
- PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
- PCH_GPIO_UNUSED, /* 76: UNUSED */
- PCH_GPIO_UNUSED, /* 77: UNUSED */
- PCH_GPIO_UNUSED, /* 78: UNUSED */
- PCH_GPIO_UNUSED, /* 79: UNUSED */
- PCH_GPIO_UNUSED, /* 80: UNUSED */
- PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
- PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
- PCH_GPIO_UNUSED, /* 83: UNUSED */
- PCH_GPIO_UNUSED, /* 84: UNUSED */
- PCH_GPIO_UNUSED, /* 85: UNUSED */
- PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 87: UNUSED */
- PCH_GPIO_UNUSED, /* 88: UNUSED */
- PCH_GPIO_UNUSED, /* 89: UNUSED */
- PCH_GPIO_UNUSED, /* 90: UNUSED */
- PCH_GPIO_UNUSED, /* 91: UNUSED */
- PCH_GPIO_UNUSED, /* 92: UNUSED */
- PCH_GPIO_UNUSED, /* 93: UNUSED */
- PCH_GPIO_UNUSED, /* 94: UNUSED */
- PCH_GPIO_END
-};
-
-#endif
diff --git a/src/mainboard/google/auron_paine/hda_verb.c b/src/mainboard/google/auron_paine/hda_verb.c
deleted file mode 100644
index 4ee9c09..0000000
--- a/src/mainboard/google/auron_paine/hda_verb.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
- 0x10ec0283, // Subsystem ID
- 0x0000000d, // Number of jacks (NID entries)
-
- 0x0017ff00, // Function Reset
- 0x0017ff00, // Double Function Reset
- 0x000F0000, // Pad - get vendor id
- 0x000F0002, // Pad - get revision id
-
- /* Bits 31:28 - Codec Address */
- /* Bits 27:20 - NID */
- /* Bits 19:8 - Verb ID */
- /* Bits 7:0 - Payload */
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
- 0x00172083,
- 0x00172102,
- 0x001722ec,
- 0x00172310,
-
- /* Pin Widget Verb Table */
-
- /* Pin Complex (NID 0x12) DMIC - Disabled */
- 0x01271cf0, //
- 0x01271d11, //
- 0x01271e11, //
- 0x01271f41, //
-
- /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
- 0x01471c10, // group 1, cap 0
- 0x01471d01, // no connector, no jack detect
- 0x01471e17, // speaker out, analog
- 0x01471f90, // fixed function, internal, Location N/A
-
- /* Pin Complex (NID 0x17) MONO Out - Disabled */
- 0x01771cf0, //
- 0x01771d11, //
- 0x01771e11, //
- 0x01771f41, //
-
- /* Pin Complex (NID 0x18) Disabled */
- 0x01871cf0, //
- 0x01871d11, //
- 0x01871e11, //
- 0x01871f41, //
-
- /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
- 0x01971c20, // group2, cap 0
- 0x01971d10, // black, jack detect
- 0x01971ea1, // Mic in, 3.5mm Jack
- 0x01971f03, // connector, External left panel
-
- /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
- 0x01a71c11, // group 1, cap 1
- 0x01a71d01, // no connector, no jack detect
- 0x01a71ea7, // mic in, analog connection
- 0x01a71f90, // Fixed function, internal, Location N/A
-
- /* Pin Complex (NID 0x1B) LINE2 - Disabled */
- 0x01b71cf0, //
- 0x01b71d11, //
- 0x01b71e11, //
- 0x01b71f41, //
-
- /* Pin Complex (NID 0x1D) PCBeep */
- 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
- 0x01d71d81, // mute spkr on hpout
- 0x01d71e15, // pcbeep en able, checksum
- 0x01d71f40, // no physical, Internal, Location N/A
-
- /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
- 0x01e71cf0, //
- 0x01e71d11, //
- 0x01e71e11, //
- 0x01e71f41, //
-
- /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
- 0x02171c21, // group2, cap 1
- 0x02171d10, // black, jack detect
- 0x02171e21, // HPOut, 3.5mm Jack
- 0x02171f03, // connector, left panel
-
- /* Undocumented settings from Realtek (needed for beep_gen) */
- /* Widget node 0x20 */
- 0x02050010,
- 0x02040c20,
- 0x0205001b,
- 0x0204081b,
-};
-
-const u32 pc_beep_verbs[] = {
- 0x00170500, /* power up everything (codec, dac, adc, mixers) */
- 0x01470740, /* enable speaker out */
- 0x01470c02, /* set speaker EAPD pin */
- 0x0143b01f, /* unmute speaker */
- 0x00c37100, /* unmute mixer nid 0xc input 1 */
- 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
-};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron_paine/mainboard.c b/src/mainboard/google/auron_paine/mainboard.c
deleted file mode 100644
index 81ca9cf..0000000
--- a/src/mainboard/google/auron_paine/mainboard.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <smbios.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include "ec.h"
-#include "onboard.h"
-
-
-static void mainboard_init(device_t dev)
-{
- mainboard_ec_init();
-}
-
-static int mainboard_smbios_data(device_t dev, int *handle,
- unsigned long *current)
-{
- int len = 0;
-
- len += smbios_write_type41(
- current, handle,
- BOARD_TRACKPAD_NAME, /* name */
- BOARD_TRACKPAD_IRQ, /* instance */
- BOARD_TRACKPAD_I2C_BUS, /* segment */
- BOARD_TRACKPAD_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- return len;
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
- dev->ops->get_smbios_data = mainboard_smbios_data;
- dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
- GMA_INT15_PANEL_FIT_CENTERING,
- GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/auron_paine/onboard.h b/src/mainboard/google/auron_paine/onboard.h
deleted file mode 100644
index 0314cc7..0000000
--- a/src/mainboard/google/auron_paine/onboard.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef ONBOARD_H
-#define ONBOARD_H
-
-#define BOARD_TRACKPAD_NAME "trackpad"
-#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
-#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
-#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
-#define BOARD_TRACKPAD_I2C_ADDR 0x67
-#define BOARD_TRACKPAD_GEN5_I2C_ADDR 0x24
-
-#endif
diff --git a/src/mainboard/google/auron_paine/pei_data.c b/src/mainboard/google/auron_paine/pei_data.c
deleted file mode 100644
index a5b2384..0000000
--- a/src/mainboard/google/auron_paine/pei_data.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-
-void mainboard_fill_pei_data(struct pei_data *pei_data)
-{
- pei_data->ec_present = 1;
-
- /* One installed DIMM per channel -- can be changed by SPD init */
- pei_data->dimm_channel0_disabled = 2;
- pei_data->dimm_channel1_disabled = 2;
-
- /* P0: LTE */
- pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
- USB_PORT_MINI_PCIE);
- /* P1: POrt A, CN10 */
- pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
- USB_PORT_BACK_PANEL);
- /* P2: CCD */
- pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
- /* P3: BT */
- pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_MINI_PCIE);
- /* P4: Port B, CN6 */
- pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
- USB_PORT_BACK_PANEL);
- /* P5: EMPTY */
- pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
- /* P6: SD Card */
- pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
- USB_PORT_FLEX);
- /* P7: EMPTY */
- pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
-
- /* P1: Port A, CN6 */
- pei_data_usb3_port(pei_data, 0, 1, 0, 0);
- /* P2: EMPTY */
- pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
- /* P3: EMPTY */
- pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
- /* P4: EMPTY */
- pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
-}
diff --git a/src/mainboard/google/auron_paine/romstage.c b/src/mainboard/google/auron_paine/romstage.c
deleted file mode 100644
index ce4af5e..0000000
--- a/src/mainboard/google/auron_paine/romstage.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <string.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
-#include <mainboard/google/auron_paine/spd/spd.h>
-#include "gpio.h"
-
-void mainboard_romstage_entry(struct romstage_params *rp)
-{
- struct pei_data pei_data;
-
- post_code(0x32);
-
- /* Ensure the EC is in the right mode for recovery */
- google_chromeec_early_init();
-
- /* Initialize GPIOs */
- init_gpios(mainboard_gpio_config);
-
- /* Fill out PEI DATA */
- memset(&pei_data, 0, sizeof(pei_data));
- mainboard_fill_pei_data(&pei_data);
- mainboard_fill_spd_data(&pei_data);
- rp->pei_data = &pei_data;
-
- /* Call into the real romstage main with this board's attributes. */
- romstage_common(rp);
-}
diff --git a/src/mainboard/google/auron_paine/smihandler.c b/src/mainboard/google/auron_paine/smihandler.c
deleted file mode 100644
index b34a69a..0000000
--- a/src/mainboard/google/auron_paine/smihandler.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-#include <elog.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
-#include <soc/nvs.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-#include "ec.h"
-
-/* Codec enable: GPIO45 */
-#define GPIO_PP3300_CODEC_EN 45
-/* WLAN / BT enable: GPIO46 */
-#define GPIO_WLAN_DISABLE_L 46
-
-
-static u8 mainboard_smi_ec(void)
-{
- u8 cmd = google_chromeec_get_event();
- u32 pm1_cnt;
-
-#if CONFIG_ELOG_GSMI
- /* Log this event */
- if (cmd)
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
-#endif
-
- switch (cmd) {
- case EC_HOST_EVENT_LID_CLOSED:
- printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
- /* Go to S5 */
- pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
- break;
- }
-
- return cmd;
-}
-
-/* gpi_sts is GPIO 47:32 */
-void mainboard_smi_gpi(u32 gpi_sts)
-{
- if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
- /* Process all pending events */
- while (mainboard_smi_ec() != 0)
- ;
- }
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- /* Disable USB charging if required */
- switch (slp_typ) {
- case ACPI_S3:
- if (smm_get_gnvs()->s3u0 == 0) {
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- }
-
- set_gpio(GPIO_PP3300_CODEC_EN, 0);
-
- /* Enable wake events */
- google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
- break;
- case ACPI_S5:
- if (smm_get_gnvs()->s5u0 == 0) {
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- }
-
- set_gpio(GPIO_PP3300_CODEC_EN, 0);
- set_gpio(GPIO_WLAN_DISABLE_L, 0);
-
- /* Enable wake events */
- google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
- break;
- }
-
- /* Disable SCI and SMI events */
- google_chromeec_set_smi_mask(0);
- google_chromeec_set_sci_mask(0);
-
- /* Clear pending events that may trigger immediate wake */
- while (google_chromeec_get_event() != 0)
- ;
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APM_CNT_ACPI_ENABLE:
- google_chromeec_set_smi_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0)
- ;
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- break;
- case APM_CNT_ACPI_DISABLE:
- google_chromeec_set_sci_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0)
- ;
- google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd
deleted file mode 100644
index 7457006..0000000
--- a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 92 12 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 .........R......
-0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 01 ixi<i... .<<.@..
-0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 62 00 ..............b.
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 80 ad 01 00 00 00 00 00 00 ff ab ................
-0000080: 48 4d 54 34 32 35 53 36 41 46 52 36 41 2d 50 42 HMT425S6AFR6A-PB
-0000090: 20 20 4e 30 80 ad 00 00 00 00 00 00 00 00 00 00 N0............
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
diff --git a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd
deleted file mode 100644
index f432106..0000000
--- a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 92 13 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 .........R......
-0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 01 ixi<i... .<<.@..
-0000020: 00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 62 00 ..............b.
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 80 ad 01 00 00 00 00 00 00 c9 c0 ................
-0000080: 48 4d 54 34 32 35 53 36 43 46 52 36 41 2d 50 42 HMT425S6CFR6A-PB
-0000090: 20 20 4e 30 80 ad 00 00 00 00 00 00 00 00 00 00 N0............
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
diff --git a/src/mainboard/google/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron_paine/spd/Makefile.inc
deleted file mode 100644
index ae790c1..0000000
--- a/src/mainboard/google/auron_paine/spd/Makefile.inc
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Google Inc.
-## Copyright (C) 2015 CrowdStrike Inc. <georg(a)crowdstrike.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd.c
-
-SPD_BIN = $(obj)/spd.bin
-
-# { GPIO47, GPIO9, GPIO13 }
-SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
-# ^ Hynix HMT425S6AFR6A-PBA
-SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0010
-# ^ Hynix HMT425S6CFR6A-PBA
-SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
-# ^ # Micron 4KTF25664HZ-1G6E1
-SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
-# ^ # Micron 4KTF25664HZ-1G6E1
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
-SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0110
-SPD_SOURCES += empty # 0b0111
-SPD_SOURCES += empty # 0b1000
-SPD_SOURCES += empty # 0b1001
-SPD_SOURCES += empty # 0b1010
-SPD_SOURCES += empty # 0b1011
-SPD_SOURCES += empty # 0b1100
-SPD_SOURCES += empty # 0b1101
-SPD_SOURCES += empty # 0b1110
-SPD_SOURCES += empty # 0b1111
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.xxd)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do xxd -rg1 $$f; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd b/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd
deleted file mode 100644
index 0099da2..0000000
--- a/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 ................
-0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 05 ixi<i... .<<.@..
-0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 01 02 00 ................
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 80 2c 00 00 00 00 00 00 00 ad 75 ......,........u
-0000080: 34 4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45 4KTF25664HZ-1G6E
-0000090: 31 20 45 31 80 2c 00 00 00 00 00 00 00 00 00 00 1 E1.,..........
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
diff --git a/src/mainboard/google/auron_paine/spd/empty.spd.xxd b/src/mainboard/google/auron_paine/spd/empty.spd.xxd
deleted file mode 100644
index 1628923..0000000
--- a/src/mainboard/google/auron_paine/spd/empty.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000020: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
diff --git a/src/mainboard/google/auron_paine/spd/spd.c b/src/mainboard/google/auron_paine/spd/spd.c
deleted file mode 100644
index 7b33e66..0000000
--- a/src/mainboard/google/auron_paine/spd/spd.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <endian.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron_paine/ec.h>
-#include <mainboard/google/auron_paine/gpio.h>
-#include <mainboard/google/auron_paine/spd/spd.h>
-
-static void mainboard_print_spd_info(uint8_t spd[])
-{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[SPD_PART_LEN+1] = { 0 };
-
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
-
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
- case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- break;
- case SPD_DRAM_LPDDR3:
- printk(BIOS_INFO, "LPDDR3\n");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
- break;
- }
-
- /* Module Part Number */
- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
- spd_name[SPD_PART_LEN] = 0;
- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
-
- printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
- , banks, ranks, rows, cols);
- printk(BIOS_INFO, "density %d Mb\n", capmb);
-
- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
- devw, busw);
-
- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
- capmb / 8 * busw / devw * ranks);
- }
-}
-
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
-{
- int spd_bits[3] = {
- SPD_GPIO_BIT0,
- SPD_GPIO_BIT1,
- SPD_GPIO_BIT2
- };
- int spd_gpio[3];
- int spd_index;
- size_t spd_file_len;
- char *spd_file;
-
- spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
- spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
- spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
-
- spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
-
- printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
- spd_index,
- spd_bits[2], spd_gpio[2],
- spd_bits[1], spd_gpio[1],
- spd_bits[0], spd_gpio[0]);
-
- spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- memcpy(pei_data->spd_data[0][0],
- spd_file + (spd_index * SPD_LEN), SPD_LEN);
- /* Index 0-2 are 4GB config with both CH0 and CH1.
- * Index 4-6 are 2GB config with CH0 only. */
- if (spd_index > 3)
- pei_data->dimm_channel1_disabled = 3;
- else
- memcpy(pei_data->spd_data[1][0],
- spd_file + (spd_index * SPD_LEN), SPD_LEN);
-
- /* Make sure a valid SPD was found */
- if (pei_data->spd_data[0][0][0] == 0)
- die("Invalid SPD data.");
-
- mainboard_print_spd_info(pei_data->spd_data[0][0]);
-}
diff --git a/src/mainboard/google/auron_paine/spd/spd.h b/src/mainboard/google/auron_paine/spd/spd.h
deleted file mode 100644
index 09a48fd..0000000
--- a/src/mainboard/google/auron_paine/spd/spd.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 256
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-
-/* Auron_paine board memory configuration GPIOs */
-#define SPD_GPIO_BIT0 13
-#define SPD_GPIO_BIT1 9
-#define SPD_GPIO_BIT2 47
-
-struct pei_data;
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
-#endif
diff --git a/src/mainboard/google/auron_paine/thermal.h b/src/mainboard/google/auron_paine/thermal.h
deleted file mode 100644
index 0b66c0b..0000000
--- a/src/mainboard/google/auron_paine/thermal.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef THERMAL_H
-#define THERMAL_H
-
-/* Control TDP Settings */
-#define CTL_TDP_SENSOR_ID 0 /* PECI */
-#define CTL_TDP_POWER_LIMIT 12 /* 12W */
-#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
-#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
-#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 104
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 95
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 105
-
-#endif
diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig
deleted file mode 100644
index 528a5eb..0000000
--- a/src/mainboard/google/samus/Kconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-if BOARD_GOOGLE_SAMUS
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select SOC_INTEL_BROADWELL
- select BOARD_ROMSIZE_KB_8192
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_PD
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_RESUME
- select HAVE_SMI_HANDLER
- select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_LPC_TPM
- select INTEL_INT15
-
-config CHROMEOS
- select CHROMEOS_RAMOOPS_DYNAMIC
- select EC_GOOGLE_CHROMEEC_SWITCHES
- select EC_SOFTWARE_SYNC
- select LID_SWITCH
- select VBOOT_EC_SLOW_UPDATE
- select VBOOT_OPROM_MATTERS
- select VBOOT_VBNV_CMOS
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/samus
-
-config MAINBOARD_PART_NUMBER
- string
- default "Samus"
-
-
-config MAX_CPUS
- int
- default 8
-
-config VGA_BIOS_FILE
- string
- default "pci8086,0166.rom"
-
-config HAVE_IFD_BIN
- bool
- default n
-
-config HAVE_ME_BIN
- bool
- default n
-
-config EC_GOOGLE_CHROMEEC_BOARDNAME
- string
- default "samus"
-
-config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
- string
- default "samus_pd"
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "SAMUS TEST 8028"
-endif
diff --git a/src/mainboard/google/samus/Kconfig.name b/src/mainboard/google/samus/Kconfig.name
deleted file mode 100644
index 6765d16..0000000
--- a/src/mainboard/google/samus/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_SAMUS
- bool "Samus"
diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc
deleted file mode 100644
index cc2151c..0000000
--- a/src/mainboard/google/samus/Makefile.inc
+++ /dev/null
@@ -1,29 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-subdirs-y += spd
-
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-romstage-y += chromeos.c
-ramstage-y += chromeos.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-romstage-y += pei_data.c
-ramstage-y += pei_data.c
-
-romstage-y += board_version.c
-ramstage-y += board_version.c
diff --git a/src/mainboard/google/samus/acpi/ec.asl b/src/mainboard/google/samus/acpi/ec.asl
deleted file mode 100644
index a7e499a..0000000
--- a/src/mainboard/google/samus/acpi/ec.asl
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/samus/ec.h>
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed Keyboard Backlight in ACPI */
-#define EC_ENABLE_KEYBOARD_BACKLIGHT
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
deleted file mode 100644
index 17f6257..0000000
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#undef ENABLE_TOUCH_WAKE
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name (_HID, EisaId("PNP0C0D"))
- Method (_LID, 0)
- {
- Return (\_SB.PCI0.LPCB.EC0.LIDS)
- }
-
- // EC wake is GPIO27 which is a special DeepSX wake pin
- Name (_PRW, Package(){ 0x70, 5 }) // GP27_EN
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-}
-
-/*
- * LPC Trusted Platform Module
- */
-Scope (\_SB.PCI0.LPCB)
-{
- #include <drivers/pc80/tpm/acpi/tpm.asl>
-}
-
-/*
- * WLAN connected to Root Port 3, becomes Root Port 1 after coalesce
- */
-Scope (\_SB.PCI0.RP01)
-{
- Device (WLAN)
- {
- Name (_ADR, 0x00000000)
-
- /* GPIO10 is PCH_WLAN_WAKE_L */
- Name (GPIO, 10)
-
- Name (_PRW, Package() { GPIO, 3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
- }
- }
- }
-}
-
-Scope (\_SB.PCI0.I2C0)
-{
- Device (ATPB)
- {
- Name (_HID, "ATML0000")
- Name (_DDN, "Atmel Touchpad Bootloader")
- Name (_UID, 1)
- Name (_S0W, 4)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x26, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
-
- // GPIO13 is PIRQL
- Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 }
- })
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
-
- Device (ATPA)
- {
- Name (_HID, "ATML0000")
- Name (_DDN, "Atmel Touchpad")
- Name (_UID, 2)
- Name (_S0W, 4)
- Name (ISTP, 1) /* Touchpad */
- Name (GPIO, 9) /* TRACKPAD_INT_L (WAKE) */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x4a, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
-
- // GPIO13 is PIRQL
- Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 }
- })
-
- Name (_PRW, Package() { GPIO, 3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
- }
- }
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
-
- Device (CODC)
- {
- /*
- * TODO(kane): Need official HID.
- *
- */
- Name (_HID, "RT5677CE")
- Name (_DDN, "RT5667 Codec")
- Name (_UID, 1)
- Name (WAKE, 45) /* DSP_INT (use as codec wake) */
-
- Name (MB1, 1) /* MICBIAS1 = 2.970V */
- Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */
- Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
- Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
- Name (IN1, 1) /* IN1 differential */
- Name (IN2, 0) /* IN2 not differential */
- Name (OUT1, 1) /* LOUT1 differential */
- Name (OUT2, 1) /* LOUT2 differential */
- Name (OUT3, 0) /* LOUT3 differential */
- Name (ASRC, 1) /* Enable I2S1 ASRC */
- Name (JD1, 0) /* JackDetect1 is not used */
- Name (JD2, 2) /* Use GPIO5 as JackDetect2 */
- Name (JD3, 3) /* Use GPIO6 as JackDetect3 */
-
- /* Add DT style bindings with _DSD */
- Name (_DSD, Package () {
- ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () { "realtek,micbias1", 1 },
- Package () { "realtek,internal-dacref-en", 1 },
- Package () { "realtek,in1-differential", 1 },
- Package () { "realtek,in2-differential", 0 },
- Package () { "realtek,lout1-differential", 1 },
- Package () { "realtek,lout2-differential", 1 },
- Package () { "realtek,lout3-differential", 0 },
- Package () { "realtek,pdm_clk_div", 1 },
- Package () { "realtek,dmic2_clk_pin", 0 },
- Package () { "realtek,asrc-en", 1 },
- Package () { "realtek,jd1-gpio", 0 },
- Package () { "realtek,jd2-gpio", 2 },
- Package () { "realtek,jd3-gpio", 3 },
- Package () { "realtek,gpio-config",
- Package () { 0, 0, 0, 0, 0, 2 } },
- }
- })
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x2c, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
-
- /* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */
- Interrupt (ResourceConsumer, Edge, ActiveHigh) { 30 }
-
- /*
- * Codec GPIOs are 1-based in the schematic
- *
- * [0] = Jack Detect (INPUT)
- * [1] = Mic Present (INPUT)
- * [2] = Interrupt to the host (OUTPUT)
- * [3] = Interrupt to the host (OUTPUT)
- * [4] = Headphone amp control (OUTPUT)
- */
-
- /* Index 0: Jack Detect - PLUG_DET is GPIO5 */
- GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly,
- "\\_SB.PCI0.I2C0.CODC") { 4 }
-
- /* Index 1: Mic Present - MIC_PRESENT_L is GPIO6 */
- GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly,
- "\\_SB.PCI0.I2C0.CODC") { 5 }
-
- /* Index 2: Codec IRQ - HOTWORD_DET_L is GPIO1 */
- GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly,
- "\\_SB.PCI0.I2C0.CODC") { 0 }
-
- /* Index 3: Codec Wake - DSP_INT is GPIO4 */
- GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly,
- "\\_SB.PCI0.I2C0.CODC") { 3 }
-
- /* Index 4: Headphone amp - HP_AMP_SHDN_L is GPIO2 */
- GpioIo (Exclusive, PullDown, , , IoRestrictionOutputOnly,
- "\\_SB.PCI0.I2C0.CODC") { 1 }
- })
-
- Name (_PRW, Package() { WAKE, 3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (^WAKE)
- }
- }
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
-}
-
-Scope (\_SB.PCI0.I2C1)
-{
- Device (ATSB)
- {
- Name (_HID, "ATML0001")
- Name (_DDN, "Atmel Touchscreen Bootloader")
- Name (_UID, 4)
- Name (_S0W, 4)
- Name (ISTP, 0) /* TouchScreen */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x27, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C1", // ResourceSource
- )
-
- // GPIO14 is PIRQM
- Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 }
- })
-
- Method (_STA)
- {
- If (LEqual (\S2EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
-
- Device (ATSA)
- {
- Name (_HID, "ATML0001")
- Name (_DDN, "Atmel Touchscreen")
- Name (_UID, 5)
- Name (_S0W, 4)
- Name (ISTP, 0) /* TouchScreen */
- Name (GPIO, 14) /* TOUCH_INT_L */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x4b, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C1", // ResourceSource
- )
-
- // GPIO14 is PIRQM
- Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 }
- })
-
-#ifdef ENABLE_TOUCH_WAKE
- Name (_PRW, Package() { GPIO, 3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
- }
- }
-#endif
-
- Method (_STA)
- {
- If (LEqual (\S2EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
-}
-
-Scope (\_SB.PCI0.SPI0)
-{
- Device (CODC)
- {
- // TODO: Need official HID.
- Name (_HID, "RT5677AA")
- Name (_UID, 1)
- Name (_CRS, ResourceTemplate ()
- {
- SpiSerialBus (
- 0, // DeviceSelection (CS0?)
- PolarityLow, // DeviceSelectionPolarity
- FourWireMode, // WireMode
- 8, // DataBitLength
- ControllerInitiated, // SlaveMode
- 1000000, // ConnectionSpeed (1MHz)
- ClockPolarityLow, // ClockPolarity
- ClockPhaseFirst, // ClockPhase
- "\\_SB.PCI0.SPI0", // ResourceSource
- 0, // ResourceSourceIndex
- ResourceConsumer, // ResourceUsage
- )
- })
- }
-}
diff --git a/src/mainboard/google/samus/acpi/superio.asl b/src/mainboard/google/samus/acpi/superio.asl
deleted file mode 100644
index 0504d9f..0000000
--- a/src/mainboard/google/samus/acpi/superio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/samus/ec.h>
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/samus/acpi/thermal.asl b/src/mainboard/google/samus/acpi/thermal.asl
deleted file mode 100644
index 9d494cb..0000000
--- a/src/mainboard/google/samus/acpi/thermal.asl
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
- ThermalZone (THRM)
- {
- Name (_TC1, 0x02)
- Name (_TC2, 0x05)
-
- // Thermal zone polling frequency: 10 seconds
- Name (_TZP, 100)
-
- // Thermal sampling period for passive cooling: 2 seconds
- Name (_TSP, 20)
-
- // Convert from Degrees C to 1/10 Kelvin for ACPI
- Method (CTOK, 1) {
- // 10th of Degrees C
- Multiply (Arg0, 10, Local0)
-
- // Convert to Kelvin
- Add (Local0, 2732, Local0)
-
- Return (Local0)
- }
-
- // Threshold for OS to shutdown
- Method (_CRT, 0, Serialized)
- {
- Return (CTOK (\TCRT))
- }
-
- // Threshold for passive cooling
- Method (_PSV, 0, Serialized)
- {
- Return (CTOK (\TPSV))
- }
-
- // Processors used for passive cooling
- Method (_PSL, 0, Serialized)
- {
- Return (\PPKG ())
- }
-
- Method (TCHK, 0, Serialized)
- {
- // Get Temperature from TIN# set in NVS
- Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
-
- // Check for sensor not calibrated
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not present
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not powered
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
- Return (CTOK(0))
- }
-
- // Check for sensor bad reading
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
- Return (CTOK(0))
- }
-
- // Adjust by offset to get Kelvin
- Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
-
- // Convert to 1/10 Kelvin
- Multiply (Local0, 10, Local0)
- Return (Local0)
- }
-
- Method (_TMP, 0, Serialized)
- {
- // Get temperature from EC in deci-kelvin
- Store (TCHK (), Local0)
-
- // Critical temperature in deci-kelvin
- Store (CTOK (\TCRT), Local1)
-
- If (LGreaterEqual (Local0, Local1)) {
- Store ("CRITICAL TEMPERATURE", Debug)
- Store (Local0, Debug)
-
- // Wait 1 second for EC to re-poll
- Sleep (1000)
-
- // Re-read temperature from EC
- Store (TCHK (), Local0)
-
- Store ("RE-READ TEMPERATURE", Debug)
- Store (Local0, Debug)
- }
-
- Return (Local0)
- }
- }
-}
diff --git a/src/mainboard/google/samus/acpi_tables.c b/src/mainboard/google/samus/acpi_tables.c
deleted file mode 100644
index ccca999..0000000
--- a/src/mainboard/google/samus/acpi_tables.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include "thermal.h"
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- acpi_init_gnvs(gnvs);
-
- /* Enable USB ports in S3 */
- gnvs->s3u0 = 1;
-
- /* Disable USB ports in S5 */
- gnvs->s5u0 = 0;
-
- gnvs->tmps = TEMPERATURE_SENSOR_ID;
- gnvs->tcrt = CRITICAL_TEMPERATURE;
- gnvs->tpsv = PASSIVE_TEMPERATURE;
- gnvs->tmax = MAX_TEMPERATURE;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- return acpi_madt_irq_overrides(current);
-}
diff --git a/src/mainboard/google/samus/board_info.txt b/src/mainboard/google/samus/board_info.txt
deleted file mode 100644
index 3e630d3..0000000
--- a/src/mainboard/google/samus/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: laptop
-ROM protocol: SPI
-Flashrom support: y
diff --git a/src/mainboard/google/samus/board_version.c b/src/mainboard/google/samus/board_version.c
deleted file mode 100644
index 550ad79..0000000
--- a/src/mainboard/google/samus/board_version.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <ec/google/chromeec/ec.h>
-#include "board_version.h"
-
-const char *samus_board_version(void)
-{
- switch (google_chromeec_get_board_version()) {
- case SAMUS_EC_BOARD_VERSION_EVT1:
- return "EVT1";
- case SAMUS_EC_BOARD_VERSION_EVT2:
- return "EVT2";
- case SAMUS_EC_BOARD_VERSION_EVT3:
- return "EVT3";
- case SAMUS_EC_BOARD_VERSION_EVT4:
- return "EVT4";
- default:
- return "Unknown";
- }
-}
diff --git a/src/mainboard/google/samus/board_version.h b/src/mainboard/google/samus/board_version.h
deleted file mode 100644
index f5371a1..0000000
--- a/src/mainboard/google/samus/board_version.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SAMUS_BOARD_VERSION_H
-#define SAMUS_BOARD_VERSION_H
-
-#define SAMUS_EC_BOARD_VERSION_EVT1 3
-#define SAMUS_EC_BOARD_VERSION_EVT2 4
-#define SAMUS_EC_BOARD_VERSION_EVT3 5
-#define SAMUS_EC_BOARD_VERSION_EVT4 0
-
-const char *samus_board_version(void);
-
-#endif
diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c
deleted file mode 100644
index ea099f5..0000000
--- a/src/mainboard/google/samus/chromeos.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <bootmode.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/gpio.h>
-
-/* SPI Write protect is GPIO 16 */
-#define CROS_WP_GPIO 16
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"},
- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-#endif
-
-int get_write_protect_state(void)
-{
- return get_gpio(CROS_WP_GPIO);
-}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_ACPI_DEVICE_NAME),
- CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_ACPI_DEVICE_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
-}
diff --git a/src/mainboard/google/samus/chromeos.fmd b/src/mainboard/google/samus/chromeos.fmd
deleted file mode 100644
index 0c05ce9..0000000
--- a/src/mainboard/google/samus/chromeos.fmd
+++ /dev/null
@@ -1,38 +0,0 @@
-FLASH@0xff800000 0x800000 {
- SI_ALL@0x0 0x200000 {
- SI_DESC@0x0 0x1000
- SI_ME@0x1000 0x1ff000
- }
- SI_BIOS@0x200000 0x600000 {
- RW_SECTION_A@0x0 0xf0000 {
- VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0xdffc0
- RW_FWID_A@0xeffc0 0x40
- }
- RW_SECTION_B@0xf0000 0xf0000 {
- VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0xdffc0
- RW_FWID_B@0xeffc0 0x40
- }
- RW_MRC_CACHE@0x1e0000 0x10000
- RW_ELOG@0x1f0000 0x4000
- RW_SHARED@0x1f4000 0x4000 {
- SHARED_DATA@0x0 0x2000
- VBLOCK_DEV@0x2000 0x2000
- }
- RW_VPD@0x1f8000 0x2000
- RW_UNUSED@0x1fa000 0x6000
- RW_LEGACY(CBFS)@0x200000 0x200000
- WP_RO@0x400000 0x200000 {
- RO_VPD@0x0 0x4000
- RO_UNUSED@0x4000 0xc000
- RO_SECTION@0x10000 0x1f0000 {
- FMAP@0x0 0x800
- RO_FRID@0x800 0x40
- RO_FRID_PAD@0x840 0x7c0
- GBB@0x1000 0x6f000
- COREBOOT(CBFS)@0x70000 0x180000
- }
- }
- }
-}
diff --git a/src/mainboard/google/samus/cmos.layout b/src/mainboard/google/samus/cmos.layout
deleted file mode 100644
index b575e02..0000000
--- a/src/mainboard/google/samus/cmos.layout
+++ /dev/null
@@ -1,110 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392 3 e 5 baud_rate
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: cpu
-400 1 e 2 hyper_threading
-#401 7 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416 128 r 0 vbnv
-#544 440 r 0 unused
-
-# SandyBridge MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 1 Emergency
-6 2 Alert
-6 3 Critical
-6 4 Error
-6 5 Warning
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
deleted file mode 100644
index d12762d..0000000
--- a/src/mainboard/google/samus/devicetree.cb
+++ /dev/null
@@ -1,112 +0,0 @@
-chip soc/intel/broadwell
-
- # Enable eDP Hotplug with 6ms pulse
- register "gpu_dp_d_hotplug" = "0x06"
-
- # Enable DDI1 Hotplug with 6ms pulse
- register "gpu_dp_b_hotplug" = "0x06"
-
- # Enable DDI2 Hotplug with 6ms pulse
- register "gpu_dp_c_hotplug" = "0x06"
-
- # Set backlight PWM values for eDP
- register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000200"
-
- # Enable Panel and configure power delays
- register "gpu_panel_port_select" = "1" # eDP
- register "gpu_panel_power_cycle_delay" = "6" # 500ms
- register "gpu_panel_power_up_delay" = "2000" # 200ms
- register "gpu_panel_power_down_delay" = "500" # 50ms
- register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
- register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
-
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
-
- register "sata_port_map" = "0x1"
- register "sata_port0_gen3_tx" = "0x72"
- register "sio_acpi_mode" = "1"
-
- # Set I2C0 to 1.8V
- register "sio_i2c0_voltage" = "1"
-
- # Force enable ASPM for PCIe Port 3
- register "pcie_port_force_aspm" = "0x04"
- register "pcie_port_coalesce" = "1"
-
- # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013b0000"
-
- # Disable S0ix for now
- register "s0ix_enable" = "0"
-
- register "vr_slow_ramp_rate_set" = "3"
- register "vr_slow_ramp_rate_enable" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
- device pci 13.0 on end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 on end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 off end # High Definition Audio
- device pci 1c.0 off end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 on end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 off end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
- end
- chip ec/google/chromeec
- device pnp 0c09.0 on end
- end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 off end # SMBus
- device pci 1f.6 on end # Thermal
- end
-end
diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl
deleted file mode 100644
index 02e6363..0000000
--- a/src/mainboard/google/samus/dsdt.asl
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0
- "COREv4", // OEM id
- "COREBOOT", // OEM table id
- 0x20110725 // OEM revision
-)
-{
- // Some generic macros
- #include <soc/intel/broadwell/acpi/platform.asl>
-
- // global NVS and variables
- #include <soc/intel/broadwell/acpi/globalnvs.asl>
-
- // General Purpose Events
- //#include "acpi/gpe.asl"
-
- // CPU
- #include <soc/intel/broadwell/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/broadwell/acpi/systemagent.asl>
- #include <soc/intel/broadwell/acpi/pch.asl>
- }
- }
-
- // Thermal handler
- #include "acpi/thermal.asl"
-
- // Chrome OS specific
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
- // Chipset specific sleep states
- #include <soc/intel/broadwell/acpi/sleepstates.asl>
-
- // Mainboard specific
- #include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/google/samus/ec.c b/src/mainboard/google/samus/ec.c
deleted file mode 100644
index 2f516b1..0000000
--- a/src/mainboard/google/samus/ec.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <types.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-void mainboard_ec_init(void)
-{
- printk(BIOS_DEBUG, "mainboard_ec_init\n");
- post_code(0xf0);
-
- /* Restore SCI event mask on resume. */
- if (acpi_is_wakeup_s3()) {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S3_WAKE_EVENTS);
-
- /* Disable SMI and wake events */
- google_chromeec_set_smi_mask(0);
-
- /* Clear pending events */
- while (google_chromeec_get_event() != 0);
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- } else {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S5_WAKE_EVENTS);
- }
-
- /* Clear wake events, these are enabled on entry to sleep */
- google_chromeec_set_wake_mask(0);
-
- post_code(0xf1);
-}
diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h
deleted file mode 100644
index bfcdfb3..0000000
--- a/src/mainboard/google/samus/ec.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-
-#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
-#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
-
-#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* EC can wake from S3 with lid or power button or key press */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
- (MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
-
-#endif
diff --git a/src/mainboard/google/samus/fadt.c b/src/mainboard/google/samus/fadt.c
deleted file mode 100644
index 11831bd..0000000
--- a/src/mainboard/google/samus/fadt.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- memset((void *) fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 5;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 1;
-
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
- fadt->model = 1;
- fadt->preferred_pm_profile = PM_MOBILE;
-
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- acpi_fill_in_fadt(fadt);
-
- header->checksum =
- acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h
deleted file mode 100644
index 82af0e4..0000000
--- a/src/mainboard/google/samus/gpio.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SAMUS_GPIO_H
-#define SAMUS_GPIO_H
-
-#include <soc/gpio.h>
-
-#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23
-#define SAMUS_GPIO_SSD_RESET_L 47
-#define SAMUS_GPIO_WLAN_DISABLE_L 42
-#define SAMUS_GPIO_LTE_DISABLE_L 59
-
-static const struct gpio_config mainboard_gpio_config[] = {
- PCH_GPIO_UNUSED, /* 0: UNUSED */
- PCH_GPIO_UNUSED, /* 1: UNUSED */
- PCH_GPIO_UNUSED, /* 2: UNUSED */
- PCH_GPIO_UNUSED, /* 3: UNUSED */
- PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
- PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
- PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
- PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
- PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
- PCH_GPIO_INPUT_INVERT, /* 9: TRACKPAD_INT_L (WAKE) */
- PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
- PCH_GPIO_UNUSED, /* 11: UNUSED */
- PCH_GPIO_UNUSED, /* 12: UNUSED */
- PCH_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */
- PCH_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */
- PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
- PCH_GPIO_INPUT, /* 16: PCH_WP */
- PCH_GPIO_UNUSED, /* 17: UNUSED */
- PCH_GPIO_UNUSED, /* 18: UNUSED */
- PCH_GPIO_UNUSED, /* 19: UNUSED */
- PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */
- PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */
- PCH_GPIO_UNUSED, /* 22: UNUSED */
- PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */
- PCH_GPIO_UNUSED, /* 24: UNUSED */
- PCH_GPIO_INPUT, /* 25: EC_IN_RW */
- PCH_GPIO_UNUSED, /* 26: UNUSED */
- PCH_GPIO_ACPI_SCI, /* 27: PCH_WAKE_L */
- PCH_GPIO_UNUSED, /* 28: UNUSED */
- PCH_GPIO_UNUSED, /* 29: UNUSED */
- PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
- PCH_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
- PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
- PCH_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */
- PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
- PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
- PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
- PCH_GPIO_UNUSED, /* 37: UNUSED */
- PCH_GPIO_UNUSED, /* 38: UNUSED */
- PCH_GPIO_UNUSED, /* 39: UNUSED */
- PCH_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */
- PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
- PCH_GPIO_UNUSED, /* 42: WLAN_DISABLE_L */
- PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */
- PCH_GPIO_UNUSED, /* 44: UNUSED */
- PCH_GPIO_ACPI_SCI, /* 45: DSP_INT - Codec Wake */
- PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L_3V3 (PIRQO) - Codec IRQ */
- PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */
- PCH_GPIO_UNUSED, /* 48: UNUSED */
- PCH_GPIO_UNUSED, /* 49: UNUSED */
- PCH_GPIO_UNUSED, /* 50: UNUSED */
- PCH_GPIO_UNUSED, /* 51: UNUSED */
- PCH_GPIO_INPUT, /* 52: SIM_DET */
- PCH_GPIO_UNUSED, /* 53: UNUSED */
- PCH_GPIO_UNUSED, /* 54: UNUSED */
- PCH_GPIO_UNUSED, /* 55: UNUSED */
- PCH_GPIO_UNUSED, /* 56: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */
- PCH_GPIO_UNUSED, /* 58: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
- PCH_GPIO_UNUSED, /* 60: UNUSED */
- PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
- PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
- PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- PCH_GPIO_UNUSED, /* 64: UNUSED */
- PCH_GPIO_INPUT, /* 65: RAM_ID3 */
- PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */
- PCH_GPIO_INPUT, /* 67: RAM_ID0 */
- PCH_GPIO_INPUT, /* 68: RAM_ID1 */
- PCH_GPIO_INPUT, /* 69: RAM_ID2 */
- PCH_GPIO_UNUSED, /* 70: UNUSED */
- PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
- PCH_GPIO_UNUSED, /* 72: UNUSED */
- PCH_GPIO_UNUSED, /* 73: UNUSED */
- PCH_GPIO_UNUSED, /* 74: UNUSED */
- PCH_GPIO_UNUSED, /* 75: UNUSED */
- PCH_GPIO_UNUSED, /* 76: UNUSED */
- PCH_GPIO_UNUSED, /* 77: UNUSED */
- PCH_GPIO_UNUSED, /* 78: UNUSED */
- PCH_GPIO_UNUSED, /* 79: UNUSED */
- PCH_GPIO_UNUSED, /* 80: UNUSED */
- PCH_GPIO_UNUSED, /* 81: UNUSED */
- PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
- PCH_GPIO_NATIVE, /* 83: GSPI0_CS */
- PCH_GPIO_NATIVE, /* 84: GSPI0_CLK */
- PCH_GPIO_NATIVE, /* 85: GSPI0_MISO */
- PCH_GPIO_NATIVE, /* 86: GSPI0_MOSI (STRAP) */
- PCH_GPIO_UNUSED, /* 87: UNUSED */
- PCH_GPIO_UNUSED, /* 88: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */
- PCH_GPIO_UNUSED, /* 90: UNUSED */
- PCH_GPIO_UNUSED, /* 91: UNUSED */
- PCH_GPIO_UNUSED, /* 92: UNUSED */
- PCH_GPIO_UNUSED, /* 93: UNUSED */
- PCH_GPIO_UNUSED, /* 94: UNUSED */
- PCH_GPIO_END
-};
-
-#endif
diff --git a/src/mainboard/google/samus/hda_verb.c b/src/mainboard/google/samus/hda_verb.c
deleted file mode 100644
index 5d08879..0000000
--- a/src/mainboard/google/samus/hda_verb.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c
deleted file mode 100644
index 9fa9c57..0000000
--- a/src/mainboard/google/samus/mainboard.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <smbios.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include "board_version.h"
-#include "ec.h"
-
-void mainboard_suspend_resume(void)
-{
-}
-
-const char *smbios_mainboard_version(void)
-{
- return samus_board_version();
-}
-
-static void mainboard_init(device_t dev)
-{
- mainboard_ec_init();
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
- dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c
deleted file mode 100644
index 051653f..0000000
--- a/src/mainboard/google/samus/pei_data.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-
-void mainboard_fill_pei_data(struct pei_data *pei_data)
-{
- /* DQ byte map for Samus board */
- const u8 dq_map[2][6][2] = {
- { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
- { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
- { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
- { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
- /* DQS CPU<>DRAM map for Samus board */
- const u8 dqs_map[2][8] = {
- { 2, 0, 1, 3, 6, 4, 7, 5 },
- { 2, 1, 0, 3, 6, 5, 4, 7 } };
-
- pei_data->ec_present = 1;
-
- /* One installed DIMM per channel */
- pei_data->dimm_channel0_disabled = 2;
- pei_data->dimm_channel1_disabled = 2;
-
- memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
- memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
-
- /* P0: HOST PORT */
- pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
- USB_PORT_BACK_PANEL);
- /* P1: HOST PORT */
- pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
- USB_PORT_BACK_PANEL);
- /* P2: RAIDEN */
- pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
- USB_PORT_BACK_PANEL);
- /* P3: SD CARD */
- pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
- /* P4: RAIDEN */
- pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
- USB_PORT_BACK_PANEL);
- /* P5: WWAN (Disabled) */
- pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
- /* P6: CAMERA */
- pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
- /* P7: BT */
- pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
-
- /* P1: HOST PORT */
- pei_data_usb3_port(pei_data, 0, 1, 0, 0);
- /* P2: HOST PORT */
- pei_data_usb3_port(pei_data, 1, 1, 1, 0);
- /* P3: RAIDEN */
- pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
- /* P4: RAIDEN */
- pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
-}
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
deleted file mode 100644
index 2306a29..0000000
--- a/src/mainboard/google/samus/romstage.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <string.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/cpu.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/pm.h>
-#include <soc/romstage.h>
-#include <mainboard/google/samus/spd/spd.h>
-#include <mainboard/google/samus/gpio.h>
-#include <ec/google/chromeec/ec.h>
-#include "board_version.h"
-
-void mainboard_romstage_entry(struct romstage_params *rp)
-{
- struct pei_data pei_data;
-
- post_code(0x31);
-
- if (rp->power_state->prev_sleep_state != ACPI_S3)
- google_chromeec_kbbacklight(100);
-
- printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
-
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
- /* Initialize GPIOs */
- init_gpios(mainboard_gpio_config);
-
- /* Fill out PEI DATA */
- memset(&pei_data, 0, sizeof(pei_data));
- mainboard_fill_pei_data(&pei_data);
- mainboard_fill_spd_data(&pei_data);
- rp->pei_data = &pei_data;
-
- /* Initalize memory */
- romstage_common(rp);
-
- /* Bring SSD out of reset */
- set_gpio(SAMUS_GPIO_SSD_RESET_L, GPIO_OUT_HIGH);
-
- /*
- * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
- * to prevent possible brownout.
- */
- set_gpio(SAMUS_GPIO_PP3300_AUTOBAHN_EN, GPIO_OUT_HIGH);
-}
diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c
deleted file mode 100644
index b0595cc..0000000
--- a/src/mainboard/google/samus/smihandler.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-#include <elog.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
-#include <soc/nvs.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-#include "ec.h"
-#include "gpio.h"
-
-static u8 mainboard_smi_ec(void)
-{
- u8 cmd = google_chromeec_get_event();
- u32 pm1_cnt;
-
-#if CONFIG_ELOG_GSMI
- /* Log this event */
- if (cmd)
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
-#endif
-
- switch (cmd) {
- case EC_HOST_EVENT_LID_CLOSED:
- printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
- /* Go to S5 */
- pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
- break;
- }
-
- return cmd;
-}
-
-/* gpi_sts is GPIO 47:32 */
-void mainboard_smi_gpi(u32 gpi_sts)
-{
- if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
- /* Process all pending events */
- while (mainboard_smi_ec() != 0);
- }
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- /* Disable USB charging if required */
- switch (slp_typ) {
- case ACPI_S3:
- if (smm_get_gnvs()->s3u0 == 0) {
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- }
-
- /* Put SSD in reset to prevent leak. */
- set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
- /* Prevent leak from standby rail to WLAN rail in S3. */
- set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
- /* Disable LTE */
- set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
-
- /* Enable wake events */
- google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
- break;
- case ACPI_S5:
- if (smm_get_gnvs()->s5u0 == 0) {
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- }
-
- /* Put SSD in reset to prevent leak. */
- set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
- /* Prevent leak from standby rail to WLAN rail in S5. */
- set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
- /* Disable LTE */
- set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
-
- /* Enable wake events */
- google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
- break;
- }
-
- /* Disable SCI and SMI events */
- google_chromeec_set_smi_mask(0);
- google_chromeec_set_sci_mask(0);
-
- /* Clear pending events that may trigger immediate wake */
- while (google_chromeec_get_event() != 0);
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APM_CNT_ACPI_ENABLE:
- google_chromeec_set_smi_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0);
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- break;
- case APM_CNT_ACPI_DISABLE:
- google_chromeec_set_sci_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0);
- google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc
deleted file mode 100644
index c7c8a75..0000000
--- a/src/mainboard/google/samus/spd/Makefile.inc
+++ /dev/null
@@ -1,50 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd.c
-
-SPD_BIN = $(obj)/spd.bin
-
-# { GPIO65, GPIO67, GPIO68, GPIO69 }
-SPD_SOURCES = empty # 0b0000
-SPD_SOURCES += empty # 0b0001
-SPD_SOURCES += empty # 0b0010
-SPD_SOURCES += empty # 0b0011
-SPD_SOURCES += empty # 0b0100
-SPD_SOURCES += empty # 0b0101
-SPD_SOURCES += samsung_4 # 0b0110
-SPD_SOURCES += empty # 0b0111
-SPD_SOURCES += hynix_4 # 0b1000
-SPD_SOURCES += empty # 0b1001
-SPD_SOURCES += samsung_8 # 0b1010
-SPD_SOURCES += empty # 0b1011
-SPD_SOURCES += hynix_8 # 0b1100
-SPD_SOURCES += hynix_16 # 0b1101
-SPD_SOURCES += empty # 0b1110
-SPD_SOURCES += elpida_16 # 0b1111
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do printf $$(printf '\%o' 0x$$c); \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/samus/spd/elpida_16.spd.hex b/src/mainboard/google/samus/spd/elpida_16.spd.hex
deleted file mode 100644
index 5594164..0000000
--- a/src/mainboard/google/samus/spd/elpida_16.spd.hex
+++ /dev/null
@@ -1,18 +0,0 @@
-# Elpida EDFB232A1MA
-# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16
-91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00
-45 44 46 42 32 33 32 41 31 4D 41 2D 47 44 2D 46
-00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/elpida_4.spd.hex b/src/mainboard/google/samus/spd/elpida_4.spd.hex
deleted file mode 100644
index e73ba62..0000000
--- a/src/mainboard/google/samus/spd/elpida_4.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00
-69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00
-45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46
-20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/elpida_8.spd.hex b/src/mainboard/google/samus/spd/elpida_8.spd.hex
deleted file mode 100644
index b790943..0000000
--- a/src/mainboard/google/samus/spd/elpida_8.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00
-69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00
-45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46
-20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/empty.spd.hex b/src/mainboard/google/samus/spd/empty.spd.hex
deleted file mode 100644
index 9ec39f1..0000000
--- a/src/mainboard/google/samus/spd/empty.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/hynix_16.spd.hex b/src/mainboard/google/samus/spd/hynix_16.spd.hex
deleted file mode 100644
index a03d4ed..0000000
--- a/src/mainboard/google/samus/spd/hynix_16.spd.hex
+++ /dev/null
@@ -1,18 +0,0 @@
-# Hynix H9CCNNNCLTMLAR LPDDR3
-# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16
-91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
-48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00
-00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/hynix_4.spd.hex b/src/mainboard/google/samus/spd/hynix_4.spd.hex
deleted file mode 100644
index 93e65a7..0000000
--- a/src/mainboard/google/samus/spd/hynix_4.spd.hex
+++ /dev/null
@@ -1,18 +0,0 @@
-# Hynix H9CCNNNBLTMLAR-NTM LPDDR3
-# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32
-91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01
-78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
-00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
-48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
-54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/hynix_8.spd.hex b/src/mainboard/google/samus/spd/hynix_8.spd.hex
deleted file mode 100644
index 15737e4..0000000
--- a/src/mainboard/google/samus/spd/hynix_8.spd.hex
+++ /dev/null
@@ -1,18 +0,0 @@
-# Hynix H9CCNNNBLTMLAR-NTM LPDDR3
-# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16
-91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01
-78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
-00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
-48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
-54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/samsung_4.spd.hex b/src/mainboard/google/samus/spd/samsung_4.spd.hex
deleted file mode 100644
index 4b82a3a..0000000
--- a/src/mainboard/google/samus/spd/samsung_4.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01
-78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
-00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
-4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20
-20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/samsung_8.spd.hex b/src/mainboard/google/samus/spd/samsung_8.spd.hex
deleted file mode 100644
index c0a8fca..0000000
--- a/src/mainboard/google/samus/spd/samsung_8.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01
-78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
-00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
-4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20
-20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c
deleted file mode 100644
index 4b5e7a6..0000000
--- a/src/mainboard/google/samus/spd/spd.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <endian.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/samus/ec.h>
-#include <mainboard/google/samus/gpio.h>
-#include <mainboard/google/samus/spd/spd.h>
-
-static void mainboard_print_spd_info(uint8_t spd[])
-{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[SPD_PART_LEN+1] = { 0 };
-
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
-
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
- case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- break;
- case SPD_DRAM_LPDDR3:
- printk(BIOS_INFO, "LPDDR3\n");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
- break;
- }
-
- /* Module Part Number */
- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
- spd_name[SPD_PART_LEN] = 0;
- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
-
- printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
- "density %d Mb\n", banks, ranks, rows, cols, capmb);
- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
- devw, busw);
-
- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
- capmb / 8 * busw / devw * ranks);
- }
-}
-
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
-{
- int spd_bits[4] = {
- SPD_GPIO_BIT0,
- SPD_GPIO_BIT1,
- SPD_GPIO_BIT2,
- SPD_GPIO_BIT3
- };
- int spd_gpio[4];
- int spd_index;
- size_t spd_file_len;
- char *spd_file;
-
- spd_gpio[0] = get_gpio(spd_bits[0]);
- spd_gpio[1] = get_gpio(spd_bits[1]);
- spd_gpio[2] = get_gpio(spd_bits[2]);
- spd_gpio[3] = get_gpio(spd_bits[3]);
-
- spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) |
- (spd_gpio[1] << 1) | spd_gpio[0];
-
- printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d "
- "GPIO%d=%d GPIO%d=%d)\n", spd_index,
- spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2],
- spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]);
-
- spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- /* Assume same memory in both channels */
- spd_index *= SPD_LEN;
- memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
- memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
-
- /* Make sure a valid SPD was found */
- if (pei_data->spd_data[0][0][0] == 0)
- die("Invalid SPD data.");
-
- mainboard_print_spd_info(pei_data->spd_data[0][0]);
-}
diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h
deleted file mode 100644
index dbfd6a0..0000000
--- a/src/mainboard/google/samus/spd/spd.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 256
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-
-/* Samus board memory configuration GPIOs */
-#define SPD_GPIO_BIT0 69
-#define SPD_GPIO_BIT1 68
-#define SPD_GPIO_BIT2 67
-#define SPD_GPIO_BIT3 65
-
-struct pei_data;
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
-#endif
diff --git a/src/mainboard/google/samus/thermal.h b/src/mainboard/google/samus/thermal.h
deleted file mode 100644
index 0908c4c..0000000
--- a/src/mainboard/google/samus/thermal.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef THERMAL_H
-#define THERMAL_H
-
-#define TEMPERATURE_SENSOR_ID 0 /* PECI */
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 104
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 95
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 105
-
-#endif
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