coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/google/chell: Set TCC activation offset to 10 degree C
by Sumeet R Pawnikar 22 Dec '16

22 Dec '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17921 -gerrit commit 7e45c8be0bb17b3da161279d902e346eb627b7d6 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Thu Dec 22 13:53:16 2016 +0530 mainboard/google/chell: Set TCC activation offset to 10 degree C With the default TCC activation offset value as 0 and Tjmax temperature value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature. This patch sets TCC activation offset value to 10 degree C for thermal throttle action to prevent this kind of shutdown. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built, booted on skylake and verified target offset value. Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/mainboard/google/chell/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 34250d3..2ffaec6 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -183,6 +183,8 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + register "tcc_offset" = "10" # TCC of 90C + # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1"

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Patch set updated for coreboot: soc/intel/skylake: set TCC activation by BSP only
by Sumeet R Pawnikar 22 Dec '16

22 Dec '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17889 -gerrit commit d4e437821b1f74401ed2360e2272b38c690c8fbc Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Thu Dec 22 13:48:46 2016 +0530 soc/intel/skylake: set TCC activation by BSP only TCC activation functionality has package scope. It was set for all CPU in the system which is unnecessary. In this patch TCC activation is being set by the BSP only. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the TCC activation value before and after S3. Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/skylake/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3ec8d2c..e8616f0 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -197,7 +197,7 @@ static void configure_thermal_target(void) config_t *conf = dev->chip_info; msr_t msr; - /* Set TCC activaiton offset if supported */ + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); @@ -366,9 +366,6 @@ static void cpu_core_init(device_t cpu) /* Configure Intel Speed Shift */ configure_isst(); - /* Thermal throttle activation offset */ - configure_thermal_target(); - /* Enable Direct Cache Access */ configure_dca_cap(); @@ -484,6 +481,9 @@ void soc_init_cpus(device_t dev) if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); } + + /* Thermal throttle activation offset */ + configure_thermal_target(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)

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Patch set updated for coreboot: spi: Get rid of SPI_ATOMIC_SEQUENCING
by Furquan Shaikh 21 Dec '16

21 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17681 -gerrit commit c6408eee5f485243667c070879733a78650dc337 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Nov 29 22:07:42 2016 -0800 spi: Get rid of SPI_ATOMIC_SEQUENCING SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/Kconfig | 10 ---- src/drivers/spi/spi-generic.c | 99 ++++++++++++++++++++++++++++++++ src/drivers/spi/spi_flash.c | 47 +++++---------- src/include/spi-generic.h | 62 +++++++++++++++++++- src/mainboard/google/purin/Kconfig | 1 - src/soc/broadcom/cygnus/spi.c | 1 + src/soc/imgtec/pistachio/Kconfig | 1 - src/soc/imgtec/pistachio/spi.c | 7 +-- src/soc/intel/baytrail/spi.c | 1 + src/soc/intel/braswell/spi.c | 1 + src/soc/intel/broadwell/spi.c | 1 + src/soc/intel/fsp_baytrail/spi.c | 1 + src/soc/intel/fsp_broadwell_de/spi.c | 1 + src/soc/mediatek/mt8173/Kconfig | 1 - src/soc/mediatek/mt8173/spi.c | 1 + src/soc/qualcomm/ipq40xx/Kconfig | 1 - src/soc/qualcomm/ipq806x/Kconfig | 1 - src/southbridge/amd/agesa/hudson/spi.c | 1 + src/southbridge/amd/cimx/sb800/spi.c | 1 + src/southbridge/amd/sb700/spi.c | 1 + src/southbridge/intel/common/spi.c | 1 + src/southbridge/intel/fsp_rangeley/spi.c | 1 + 22 files changed, 188 insertions(+), 54 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b55de58..c8d86ff 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -61,16 +61,6 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS default n if COMMON_CBFS_SPI_WRAPPER default y -config SPI_ATOMIC_SEQUENCING - bool - default y if ARCH_X86 - default n if !ARCH_X86 - help - Select this option if the SPI controller uses "atomic sequencing." - Atomic sequencing is when the sequence of commands is pre-programmed - in the SPI controller. Hardware manages the transaction instead of - software. This is common on x86 platforms. - config SPI_FLASH_SMM bool "SPI flash driver support in SMM" default n diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 4fcd04c..805e17a 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <spi-generic.h> #include <string.h> @@ -32,10 +33,55 @@ void spi_release_bus(const struct spi_slave *slave) ctrlr->release_bus(slave); } +static int spi_xfer_single_op(const struct spi_slave *slave, + struct spi_op *op) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + int ret; + + if (!ctrlr || !ctrlr->xfer) + return -1; + + ret = ctrlr->xfer(slave, op->dout, op->bytesout, op->din, op->bytesin); + if (ret) + op->status = SPI_OP_FAILURE; + else + op->status = SPI_OP_SUCCESS; + + return ret; +} + +static int spi_xfer_vector_default(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + size_t i; + int ret; + + for (i = 0; i < count; i++) { + ret = spi_xfer_single_op(slave, &vectors[i]); + if (ret) + return ret; + } + + return 0; +} + +int spi_xfer_vector(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + + if (ctrlr && ctrlr->xfer_vector) + return ctrlr->xfer_vector(slave, vectors, count); + + return spi_xfer_vector_default(slave, vectors, count); +} + int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { const struct spi_ctrlr *ctrlr = slave->ctrlr; + if (ctrlr && ctrlr->xfer) return ctrlr->xfer(slave, dout, bytesout, din, bytesin); @@ -76,3 +122,56 @@ int __attribute__((weak)) spi_setup_slave(unsigned int bus, unsigned int cs, return 0; } + +static int spi_xfer_combine_two_vectors(const struct spi_slave *slave, + struct spi_op *v1, struct spi_op *v2) +{ + struct spi_op op = { + .dout = v1->dout, .bytesout = v1->bytesout, + .din = v2->din, .bytesin = v2->bytesin, + }; + int ret; + + /* + * Combine two vectors only if: + * v1 has non-NULL dout and NULL din and + * v2 has non-NULL din and NULL dout and + * + * In all other cases, do not combine the two vectors. + */ + if ((!v1->dout || v1->din) || (v2->dout || !v2->din)) + return -1; + + ret = spi_xfer_single_op(slave, &op); + v1->status = v2->status = op.status; + + return ret; +} + +/* + * Helper function to allow chipsets to combine two vectors if possible. This + * function can only handle upto 2 vectors. + * + * Two vectors are combined if first vector has a non-NULL dout and NULL din and + * second vector has a non-NULL din and NULL dout. Otherwise, each vector is + * operated upon one at a time. + * + * Returns 0 on success and non-zero on failure. + */ +int spi_xfer_two_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + int ret; + + assert (count <= 2); + + if (count == 2) { + ret = spi_xfer_combine_two_vectors(slave, &vectors[0], + &vectors[1]); + + if (!ret || (vectors[0].status != SPI_OP_NOT_EXECUTED)) + return ret; + } + + return spi_xfer_vector_default(slave, vectors, count); +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3b4272b..a0e3105 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -32,47 +32,30 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -/* - * If atomic sequencing is used, the cycle type is known to the SPI - * controller so that it can perform consecutive transfers and arbitrate - * automatically. Otherwise the SPI controller transfers whatever the - * user requests immediately, without regard to sequence. Atomic - * sequencing is commonly used on x86 platforms. - * - * SPI flash commands are simple two-step sequences. The command byte is - * always written first and may be followed by an address. Then data is - * either read or written. For atomic sequencing we'll pass everything into - * spi_xfer() at once and let the controller handle the details. Otherwise - * we will write all output bytes first and then read if necessary. - * - * FIXME: This really should be abstracted better, but that will - * require overhauling the entire SPI infrastructure. - */ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { int ret = 1; + /* + * SPI flash requires command-response kind of behavior. Thus, two + * separate SPI vectors are required -- first to transmit dout and other + * to receive in din. If some specialized SPI flash controllers + * (e.g. x86) can perform both command and response together, it should + * be handled at SPI flash controller driver level. + */ + struct spi_op vectors[] = { + [0] = { .dout = dout, .bytesout = bytes_out, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = NULL, .bytesout = 0, + .din = din, .bytesin = bytes_in }, + }; if (spi_claim_bus(spi)) return ret; -#if CONFIG_SPI_ATOMIC_SEQUENCING == 1 - if (spi_xfer(spi, dout, bytes_out, din, bytes_in) < 0) - goto done; -#else - if (dout && bytes_out) { - if (spi_xfer(spi, dout, bytes_out, NULL, 0) < 0) - goto done; - } - - if (din && bytes_in) { - if (spi_xfer(spi, NULL, 0, din, bytes_in) < 0) - goto done; - } -#endif + if (spi_xfer_vector(spi, vectors, ARRAY_SIZE(vectors)) == 0) + ret = 0; - ret = 0; -done: spi_release_bus(spi); return ret; } diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index d28fefd..7eb18a6 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -36,20 +36,46 @@ struct spi_slave { const struct spi_ctrlr *ctrlr; }; +/* Representation of SPI operation status. */ +enum spi_op_status { + SPI_OP_NOT_EXECUTED = 0, + SPI_OP_SUCCESS = 1, + SPI_OP_FAILURE = 2, +}; + +/* + * Representation of a SPI operation. + * + * dout: Pointer to data to send. + * bytesout: Count of data in bytes to send. + * din: Pointer to store received data. + * bytesin: Count of data in bytes to receive. + */ +struct spi_op { + const void *dout; + size_t bytesout; + void *din; + size_t bytesin; + enum spi_op_status status; +}; + /*----------------------------------------------------------------------- * Representation of a SPI contoller. * * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. - * xfer: SPI transfer * setup: Setup given SPI device bus. + * xfer: Perform one SPI transfer operation. + * xfer_vector: Vector of SPI transfer operations. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); + int (*setup)(const struct spi_slave *slave); int (*xfer)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); - int (*setup)(const struct spi_slave *slave); + int (*xfer_vector)(const struct spi_slave *slave, + struct spi_op vectors[], size_t count); }; /*----------------------------------------------------------------------- @@ -134,6 +160,19 @@ void spi_release_bus(const struct spi_slave *slave); int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); +/*----------------------------------------------------------------------- + * Vector of SPI transfer operations + * + * spi_xfer_vector() interface: + * slave: The SPI slave which will be sending/receiving the data. + * vectors: Array of SPI op structures. + * count: Number of SPI op vectors. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer_vector(const struct spi_slave *slave, + struct spi_op vectors[], size_t count); + unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len); /*----------------------------------------------------------------------- @@ -158,4 +197,23 @@ static inline int spi_w8r8(const struct spi_slave *slave, unsigned char byte) return ret < 0 ? ret : din[1]; } +/* + * Helper function to allow chipsets to combine two vectors if possible. It can + * only handle upto 2 vectors. + * + * This function is provided to support command-response kind of transactions + * expected by users like flash. Some special SPI flash controllers can handle + * such command-response operations in a single transaction. For these special + * controllers, separate command and response vectors can be combined into a + * single operation. + * + * Two vectors are combined if first vector has a non-NULL dout and NULL din and + * second vector has a non-NULL din and NULL dout. Otherwise, each vector is + * operated upon one at a time. + * + * Returns 0 on success and non-zero on failure. + */ +int spi_xfer_two_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count); + #endif /* _SPI_GENERIC_H_ */ diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index eabab2b..ca0909b 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO # required for the reference board BCM958305K - select SPI_ATOMIC_SEQUENCING config CHROMEOS select VBOOT_VBNV_FLASH diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index e597efc..f03d453 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -279,6 +279,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index da33cc5..1ce488c 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -22,7 +22,6 @@ config CPU_IMGTEC_PISTACHIO select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_HARD_RESET select UART_OVERRIDE_REFCLK diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index e956e46..2b706f0 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -22,10 +22,6 @@ #include <string.h> #include <timer.h> -#if !CONFIG_SPI_ATOMIC_SEQUENCING -#error "Unsupported SPI driver API" -#endif - /* Imgtec controller uses 16 bit packet length. */ #define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) @@ -496,7 +492,7 @@ static int do_spi_xfer(const struct spi_slave *slave, const void *dout, } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) + size_t bytesout, void *din, size_t bytesin) { unsigned int in_sz, out_sz; int ret; @@ -541,6 +537,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; /* Set up communications parameters for a SPI slave. */ diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 0f7b0c6..639954b 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -612,6 +612,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 2a0ddf8..86b3351 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -596,6 +596,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index d2ae943..7a7eaf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -646,6 +646,7 @@ int spi_flash_protect(u32 start, u32 size) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 997bd13..dee7440 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -592,6 +592,7 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 5848966..a6b6f35 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -609,6 +609,7 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index ec3481e..7a6ad87 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8173 select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING if SPI_FLASH select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select GENERIC_GPIO_LIB diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 53d5b8c..415764a 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -293,6 +293,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index f738622..05f29e4 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ40XX select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 7ba5df5..32b61bc 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB if SOC_QC_IPQ806X diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 8a4adfb..00f6b29 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -167,6 +167,7 @@ int chipset_volatile_group_end(const struct spi_flash *flash) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index edf192a..1e84743 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -158,6 +158,7 @@ int chipset_volatile_group_end(const struct spi_flash *flash) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 2e16ca8..5d56415 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -120,6 +120,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 093017e..ee94937 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -659,6 +659,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 8026698..0bffeb5 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -724,6 +724,7 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

1 0

New patch to review for coreboot: amd/hudson/agesa: Fix position of hudson_fwm
by Ricardo Ribalda Delgado 21 Dec '16

21 Dec '16

Ricardo Ribalda Delgado (ricardo.ribalda(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17934 -gerrit commit abe58c1afd7370742368ab700bcdf350c7a72a8f Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Wed Dec 21 20:57:13 2016 +0100 amd/hudson/agesa: Fix position of hudson_fwm AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. On this patch we force the position of HUDSON_FWM_POSITION to the position calculated by amdfwrom. Tested on a Bettong board with a 16MiB flash. Change-Id: I3ce69f77174327c18ff97e551c0665c9f633991e Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 23 ----------------------- src/southbridge/amd/agesa/hudson/Makefile.inc | 3 +-- 2 files changed, 1 insertion(+), 25 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index eed83ae..91ebe03 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -101,29 +101,6 @@ config HUDSON_FWM default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM default n -if HUDSON_FWM - -config HUDSON_FWM_POSITION - hex "Hudson Firmware ROM Position" - default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 - default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 - default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 - default 0xFF820000 if BOARD_ROMSIZE_KB_8192 - default 0xFF020000 if BOARD_ROMSIZE_KB_16384 - help - Hudson requires the firmware MUST be located at - a specific address (ROM start address + 0x20000), otherwise - xhci host Controller can not find or load the xhci firmware. - - The firmware start address is dependent on the ROM chip size. - The default offset is 0x20000 from the ROM start address, namely - 0xFFF20000 if flash chip size is 1M - 0xFFE20000 if flash chip size is 2M - 0xFFC20000 if flash chip size is 4M - 0xFF820000 if flash chip size is 8M - 0xFF020000 if flash chip size is 16M -endif # HUDSON_FWM - config HUDSON_SATA_MODE int "SATA Mode" default 0 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 2e8b13b..7595889 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -35,8 +35,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # +-----------+---------------+----------------+------------+ # EC ROM should be 64K aligned. -HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-multiply, $(CONFIG_COREBOOT_ROMSIZE_KB) 1024)) 0x20000 1) -HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID))

1 0

Patch set updated for coreboot: amd/hudson/pi: Fix position of hudson_fwm
by Ricardo Ribalda Delgado 21 Dec '16

21 Dec '16

Ricardo Ribalda Delgado (ricardo.ribalda(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17925 -gerrit commit 596a25ccb78f0a457c01c9be5bacb860507007ae Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Tue Dec 20 10:51:08 2016 +0100 amd/hudson/pi: Fix position of hudson_fwm AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. On this patch we force the position of HUDSON_FWM_POSITION to the position calculated by amdfwrom. Tested on a Bettong board with a 16MiB flash. Change-Id: Id2ee96ee076293d48ade84fd6e976ca994dcf491 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- src/southbridge/amd/pi/hudson/Kconfig | 23 ----------------------- src/southbridge/amd/pi/hudson/Makefile.inc | 3 +-- 2 files changed, 1 insertion(+), 25 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index afa03aa..f6e3355 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -103,29 +103,6 @@ config HUDSON_FWM default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM || HUDSON_PSP default n -if HUDSON_FWM - -config HUDSON_FWM_POSITION - hex "Hudson Firmware ROM Position" - default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 - default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 - default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 - default 0xFF820000 if BOARD_ROMSIZE_KB_8192 - default 0xFF020000 if BOARD_ROMSIZE_KB_16384 - help - Hudson requires the firmware MUST be located at - a specific address (ROM start address + 0x20000), otherwise - xhci host Controller can not find or load the xhci firmware. - - The firmware start address is dependent on the ROM chip size. - The default offset is 0x20000 from the ROM start address, namely - 0xFFF20000 if flash chip size is 1M - 0xFFE20000 if flash chip size is 2M - 0xFFC20000 if flash chip size is 4M - 0xFF820000 if flash chip size is 8M - 0xFF020000 if flash chip size is 16M -endif # HUDSON_FWM - config AMD_PUBKEY_FILE depends on HUDSON_PSP string "AMD public Key" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 292da76..24a757c 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -67,8 +67,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # # EC ROM should be 64K aligned. -HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-multiply, $(CONFIG_COREBOOT_ROMSIZE_KB) 1024)) 0x20000 1) -HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) ## ifeq ($(CONFIG_HUDSON_PSP), y)

1 0

Patch merged into coreboot/master: libpayload: Get current tick from high register in generic timer
by gerrit＠coreboot.org 21 Dec '16

21 Dec '16

the following patch was just integrated into master: commit 35562d8b6477058e6bca31b5cedd9d4897124fc7 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Dec 19 19:22:39 2016 +0100 libpayload: Get current tick from high register in generic timer This fixes the generic timer driver to get the current tick from the high register, so that comparison with the high count value (obtained previously from the same register) has a chance to succeed. Change-Id: I5ce02bfa15a91ad34641b8e24813a5b7ca790ec3 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/17929 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17929 for details. -gerrit

1 0

New patch to review for coreboot: soc/intel/skylake: Use the new SPI driver interface
by Furquan Shaikh 21 Dec '16

21 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17933 -gerrit commit 6d784a219239a4c6b9dea4c10c69c26b4181619c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Dec 21 10:58:26 2016 -0800 soc/intel/skylake: Use the new SPI driver interface 1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles succesfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 5 ++ src/soc/intel/skylake/flash_controller.c | 74 +++++++++------------- .../intel/skylake/include/soc/flash_controller.h | 5 +- src/soc/intel/skylake/romstage/spi.c | 2 +- src/soc/intel/skylake/smihandler.c | 3 +- src/soc/intel/skylake/spi.c | 41 ++++++++++++ 6 files changed, 83 insertions(+), 47 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 56cfdee..3a474e7 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -25,6 +25,7 @@ bootblock-y += monotonic_timer.c bootblock-y += pch.c bootblock-y += pcr.c bootblock-y += pmutil.c +bootblock-y += spi.c bootblock-y += tsc_freq.c verstage-y += flash_controller.c @@ -33,6 +34,7 @@ verstage-y += pch.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-y += pmutil.c verstage-y += bootblock/i2c.c +verstage-y += spi.c romstage-y += flash_controller.c romstage-y += gpio.c @@ -46,6 +48,7 @@ romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += smbus_common.c romstage-y += early_smbus.c +romstage-y += spi.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c @@ -80,6 +83,7 @@ ramstage-y += smbus.c ramstage-y += smbus_common.c ramstage-y += smi.c ramstage-y += smmrelocate.c +ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += tsc_freq.c ramstage-y += uart.c @@ -95,6 +99,7 @@ smm-y += pch.c smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c +smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-y += tsc_freq.c smm-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 501f80f..476a08c 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -25,23 +25,23 @@ #include <soc/spi.h> #include <spi-generic.h> -static inline uint16_t spi_read_hsfs(pch_spi_regs * const regs) +static inline uint16_t spi_flash_read_hsfs(pch_spi_flash_regs * const regs) { return readw_(&regs->hsfs); } -static inline void spi_clear_status(pch_spi_regs * const regs) +static inline void spi_flash_clear_status(pch_spi_flash_regs * const regs) { /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(spi_read_hsfs(regs), &regs->hsfs); + writew_(spi_flash_read_hsfs(regs), &regs->hsfs); } -static inline uint16_t spi_read_hsfc(pch_spi_regs * const regs) +static inline uint16_t spi_flash_read_hsfc(pch_spi_flash_regs * const regs) { return readw_(&regs->hsfc); } -static inline uint32_t spi_read_faddr(pch_spi_regs * const regs) +static inline uint32_t spi_flash_read_faddr(pch_spi_flash_regs * const regs) { return readl_(&regs->faddr) & SPIBAR_FADDR_MASK; } @@ -52,7 +52,7 @@ static inline uint32_t spi_read_faddr(pch_spi_regs * const regs) * Returns 0 if the cycle completes successfully without errors within * timeout, 1 on errors. */ -static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, +static int wait_for_completion(pch_spi_flash_regs * const regs, int timeout_ms, size_t len) { uint16_t hsfs; @@ -64,15 +64,15 @@ static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, stopwatch_init_msecs_expire(&sw, timeout_ms); do { - hsfs = spi_read_hsfs(regs); + hsfs = spi_flash_read_hsfs(regs); if ((hsfs & (HSFS_FDONE | HSFS_FCERR))) break; } while (!(timeout = stopwatch_expired(&sw))); if (timeout) { - addr = spi_read_faddr(regs); - hsfc = spi_read_hsfc(regs); + addr = spi_flash_read_faddr(regs); + hsfc = spi_flash_read_hsfc(regs); printk(BIOS_ERR, "%ld ms Transaction timeout between offset " "0x%08x and 0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", stopwatch_duration_msecs(&sw), addr, addr + len - 1, @@ -81,8 +81,8 @@ static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, } if (hsfs & HSFS_FCERR) { - addr = spi_read_faddr(regs); - hsfc = spi_read_hsfc(regs); + addr = spi_flash_read_faddr(regs); + hsfc = spi_flash_read_hsfc(regs); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " "0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -94,13 +94,14 @@ static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, } /* Start operation returning 0 on success, non-zero on error or timeout. */ -static int spi_do_operation(int op, size_t offset, size_t size, int timeout_ms) +static int spi_flash_do_operation(int op, size_t offset, size_t size, + int timeout_ms) { uint16_t hsfc; - pch_spi_regs * const regs = get_spi_bar(); + pch_spi_flash_regs * const regs = get_spi_bar(); /* Clear status prior to operation. */ - spi_clear_status(regs); + spi_flash_clear_status(regs); /* Set the FADDR */ writel_(offset & SPIBAR_FADDR_MASK, &regs->faddr); @@ -126,7 +127,7 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(SPI_FDATA_BYTES, buf_len); } -static size_t spi_get_flash_size(pch_spi_regs *spi_bar) +static size_t spi_get_flash_size(pch_spi_flash_regs *spi_bar) { uint32_t flcomp; size_t size; @@ -151,7 +152,7 @@ static size_t spi_get_flash_size(pch_spi_regs *spi_bar) return size; } -void spi_init(void) +void spi_flash_init(void) { uint8_t bios_cntl; device_t dev = PCH_DEV_SPI; @@ -178,7 +179,7 @@ int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) end = start + len; while (offset < end) { - if (spi_do_operation(HSFC_FCYCLE_4KE, offset, 0, 5000)) { + if (spi_flash_do_operation(HSFC_FCYCLE_4KE, offset, 0, 5000)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset); ret = -1; goto out; @@ -197,7 +198,7 @@ out: static void pch_read_data(uint8_t *data, int len) { int i; - pch_spi_regs *spi_bar; + pch_spi_flash_regs *spi_bar; uint32_t temp32 = 0; spi_bar = get_spi_bar(); @@ -230,7 +231,7 @@ int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; - if (spi_do_operation(HSFC_FCYCLE_RD, addr, block_len, + if (spi_flash_do_operation(HSFC_FCYCLE_RD, addr, block_len, timeout_ms)) return -1; @@ -251,7 +252,7 @@ static void pch_fill_data(const uint8_t *data, int len) { uint32_t temp32 = 0; int i; - pch_spi_regs *spi_bar; + pch_spi_flash_regs *spi_bar; spi_bar = get_spi_bar(); if (len <= 0) @@ -277,7 +278,7 @@ int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, { uint8_t block_len; uint32_t start = addr; - pch_spi_regs *spi_bar; + pch_spi_flash_regs *spi_bar; spi_bar = get_spi_bar(); @@ -296,7 +297,7 @@ int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, block_len = (~addr & 0xff) + 1; pch_fill_data(buf, block_len); - if (spi_do_operation(HSFC_FCYCLE_WR, addr, block_len, + if (spi_flash_do_operation(HSFC_FCYCLE_WR, addr, block_len, timeout_ms)) { printk(BIOS_ERR, "SF: write failure at %x\n", addr); return -1; @@ -315,7 +316,7 @@ int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg) size_t block_len = SPI_READ_STATUS_LENGTH; const int timeout_ms = 6; - if (spi_do_operation(HSFC_FCYCLE_RS, 0, block_len, timeout_ms)) + if (spi_flash_do_operation(HSFC_FCYCLE_RS, 0, block_len, timeout_ms)) return -1; pch_read_data(reg, block_len); @@ -332,7 +333,7 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) flash = car_get_var_ptr(&boot_flash); /* Ensure writes can take place to the flash. */ - spi_init(); + spi_flash_init(); memcpy(&flash->spi, spi, sizeof(*spi)); flash->name = "Opaque HW-sequencing"; @@ -350,22 +351,9 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) return flash; } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - /* This is special hardware. We expect bus 0 and CS line 0 here. */ - if ((bus != 0) || (cs != 0)) - return -1; - - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = NULL; - - return 0; -} - int spi_flash_get_fpr_info(struct fpr_info *info) { - pch_spi_regs *spi_bar = get_spi_bar(); + pch_spi_flash_regs *spi_bar = get_spi_bar(); if (!spi_bar) return -1; @@ -378,13 +366,13 @@ int spi_flash_get_fpr_info(struct fpr_info *info) #if ENV_RAMSTAGE /* - * spi_init() needs run unconditionally in every boot (including resume) to - * allow write protect to be disabled for eventlog and firmware updates. + * spi_flash_init() needs run unconditionally in every boot (including resume) + * to allow write protect to be disabled for eventlog and firmware updates. */ -static void spi_init_cb(void *unused) +static void spi_flash_init_cb(void *unused) { - spi_init(); + spi_flash_init(); } -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL); +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); #endif diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h index 0050067..25e7734 100644 --- a/src/soc/intel/skylake/include/soc/flash_controller.h +++ b/src/soc/intel/skylake/include/soc/flash_controller.h @@ -28,6 +28,7 @@ int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf); int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg); +void spi_flash_init(void); #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) static u8 readb_(const void *addr) @@ -134,7 +135,7 @@ static void writel_(u32 b, void *addr) #define SPI_FDATA_REGS 16 #define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t)) -typedef struct pch_spi_regs { +typedef struct pch_spi_flash_regs { uint32_t bfpr; uint16_t hsfs; uint16_t hsfc; @@ -164,7 +165,7 @@ typedef struct pch_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) pch_spi_regs; +} __attribute__((packed)) pch_spi_flash_regs; enum { HSFS_FDONE = 0x0001, diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c index 1622404..41e06a7 100644 --- a/src/soc/intel/skylake/romstage/spi.c +++ b/src/soc/intel/skylake/romstage/spi.c @@ -27,7 +27,7 @@ int early_spi_read_wpsr(u8 *sr) uint8_t rdsr; int ret = 0; - spi_init(); + spi_flash_init(); /* sending NULL for spiflash struct parameter since we are not * calling HWSEQ read_status() call via Probe. diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 872cce1..382bdfc 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -26,6 +26,7 @@ #include <spi-generic.h> #include <elog.h> #include <pc80/mc146818rtc.h> +#include <soc/flash_controller.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/nvs.h> @@ -276,7 +277,7 @@ static void finalize(void) if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ - spi_init(); + spi_flash_init(); } static void southbridge_smi_apmc(void) diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c new file mode 100644 index 0000000..57c73d9 --- /dev/null +++ b/src/soc/intel/skylake/spi.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <spi-generic.h> + +/* SPI controller managing the flash-device SPI. */ +static int flash_spi_ctrlr_setup(const struct spi_slave *dev) +{ + if ((dev->bus != 0) || (dev->cs != 0)) { + printk(BIOS_ERR, "%s: Unsupported device bus=0x%x,cs=0x%x!\n", + __func__, dev->bus, dev->cs); + return -1; + } + + return 0; +} + +static const struct spi_ctrlr flash_spi_ctrlr = { + .setup = flash_spi_ctrlr_setup, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); +

1 0

Patch set updated for coreboot: spi: Get rid of SPI_ATOMIC_SEQUENCING
by Furquan Shaikh 21 Dec '16

21 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17681 -gerrit commit d77c45e2da18b70adf324cb4792b077797da7a67 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Nov 29 22:07:42 2016 -0800 spi: Get rid of SPI_ATOMIC_SEQUENCING SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/Kconfig | 10 ---- src/drivers/spi/spi-generic.c | 100 +++++++++++++++++++++++++++++++ src/drivers/spi/spi_flash.c | 47 +++++---------- src/include/spi-generic.h | 56 ++++++++++++++++- src/mainboard/google/purin/Kconfig | 1 - src/soc/broadcom/cygnus/spi.c | 1 + src/soc/imgtec/pistachio/Kconfig | 1 - src/soc/imgtec/pistachio/spi.c | 7 +-- src/soc/intel/baytrail/spi.c | 1 + src/soc/intel/braswell/spi.c | 1 + src/soc/intel/broadwell/spi.c | 1 + src/soc/intel/fsp_baytrail/spi.c | 1 + src/soc/intel/fsp_broadwell_de/spi.c | 1 + src/soc/mediatek/mt8173/Kconfig | 1 - src/soc/mediatek/mt8173/spi.c | 1 + src/soc/qualcomm/ipq40xx/Kconfig | 1 - src/soc/qualcomm/ipq806x/Kconfig | 1 - src/southbridge/amd/agesa/hudson/spi.c | 1 + src/southbridge/amd/cimx/sb800/spi.c | 1 + src/southbridge/amd/sb700/spi.c | 1 + src/southbridge/intel/common/spi.c | 1 + src/southbridge/intel/fsp_rangeley/spi.c | 1 + 22 files changed, 183 insertions(+), 54 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b55de58..c8d86ff 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -61,16 +61,6 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS default n if COMMON_CBFS_SPI_WRAPPER default y -config SPI_ATOMIC_SEQUENCING - bool - default y if ARCH_X86 - default n if !ARCH_X86 - help - Select this option if the SPI controller uses "atomic sequencing." - Atomic sequencing is when the sequence of commands is pre-programmed - in the SPI controller. Hardware manages the transaction instead of - software. This is common on x86 platforms. - config SPI_FLASH_SMM bool "SPI flash driver support in SMM" default n diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 4fcd04c..54bdfdd 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <spi-generic.h> #include <string.h> @@ -32,10 +33,55 @@ void spi_release_bus(const struct spi_slave *slave) ctrlr->release_bus(slave); } +static int spi_xfer_single_op(const struct spi_slave *slave, + struct spi_op *op) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + int ret; + + if (!ctrlr || !ctrlr->xfer) + return -1; + + ret = ctrlr->xfer(slave, op->dout, op->bytesout, op->din, op->bytesin); + if (ret) + op->status = SPI_OP_FAILURE; + else + op->status = SPI_OP_SUCCESS; + + return ret; +} + +static int spi_xfer_vector_default(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + size_t i; + int ret; + + for (i = 0; i < count; i++) { + ret = spi_xfer_single_op(slave, &vectors[i]); + if (ret) + return ret; + } + + return 0; +} + +int spi_xfer_vector(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + + if (ctrlr && ctrlr->xfer_vector) + return ctrlr->xfer_vector(slave, vectors, count); + + return spi_xfer_vector_default(slave, vectors, count); +} + int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { const struct spi_ctrlr *ctrlr = slave->ctrlr; + if (ctrlr && ctrlr->xfer) return ctrlr->xfer(slave, dout, bytesout, din, bytesin); @@ -76,3 +122,57 @@ int __attribute__((weak)) spi_setup_slave(unsigned int bus, unsigned int cs, return 0; } + +static int spi_xfer_combine_two_vectors(const struct spi_slave *slave, + struct spi_op *v1, struct spi_op *v2) +{ + struct spi_op op = { + .dout = v1->dout, .bytesout = v1->bytesout, + .din = v2->din, .bytesin = v2->bytesin, + }; + int ret; + + /* + * Combine two vectors only if: + * v1 has non-NULL dout and NULL din and + * v2 has non-NULL din and NULL dout and + * v1.bytesout is equal to v2.bytesin + * + * In all other cases, do not combine the two vectors. + */ + if ((!v1->dout || v1->din) || (v2->dout || !v2->din)) + return -1; + + ret = spi_xfer_single_op(slave, &op); + v1->status = v2->status = op.status; + + return ret; +} + +/* + * Helper function to allow chipsets to combine two vectors if possible. This + * function can only handle upto 2 vectors. + * + * Two vectors are combined if first vector has a non-NULL dout and NULL din and + * second vector has a non-NULL din and NULL dout. Otherwise, each vector is + * operated upon one at a time. + * + * Returns 0 on success and non-zero on failure. + */ +int spi_xfer_two_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + int ret; + + assert (count <= 2); + + if (count == 2) { + ret = spi_xfer_combine_two_vectors(slave, &vectors[0], + &vectors[1]); + + if (!ret || (vectors[0].status != SPI_OP_NOT_EXECUTED)) + return ret; + } + + return spi_xfer_vector_default(slave, vectors, count); +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3b4272b..a0e3105 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -32,47 +32,30 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -/* - * If atomic sequencing is used, the cycle type is known to the SPI - * controller so that it can perform consecutive transfers and arbitrate - * automatically. Otherwise the SPI controller transfers whatever the - * user requests immediately, without regard to sequence. Atomic - * sequencing is commonly used on x86 platforms. - * - * SPI flash commands are simple two-step sequences. The command byte is - * always written first and may be followed by an address. Then data is - * either read or written. For atomic sequencing we'll pass everything into - * spi_xfer() at once and let the controller handle the details. Otherwise - * we will write all output bytes first and then read if necessary. - * - * FIXME: This really should be abstracted better, but that will - * require overhauling the entire SPI infrastructure. - */ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { int ret = 1; + /* + * SPI flash requires command-response kind of behavior. Thus, two + * separate SPI vectors are required -- first to transmit dout and other + * to receive in din. If some specialized SPI flash controllers + * (e.g. x86) can perform both command and response together, it should + * be handled at SPI flash controller driver level. + */ + struct spi_op vectors[] = { + [0] = { .dout = dout, .bytesout = bytes_out, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = NULL, .bytesout = 0, + .din = din, .bytesin = bytes_in }, + }; if (spi_claim_bus(spi)) return ret; -#if CONFIG_SPI_ATOMIC_SEQUENCING == 1 - if (spi_xfer(spi, dout, bytes_out, din, bytes_in) < 0) - goto done; -#else - if (dout && bytes_out) { - if (spi_xfer(spi, dout, bytes_out, NULL, 0) < 0) - goto done; - } - - if (din && bytes_in) { - if (spi_xfer(spi, NULL, 0, din, bytes_in) < 0) - goto done; - } -#endif + if (spi_xfer_vector(spi, vectors, ARRAY_SIZE(vectors)) == 0) + ret = 0; - ret = 0; -done: spi_release_bus(spi); return ret; } diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index d28fefd..880de94 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -36,20 +36,46 @@ struct spi_slave { const struct spi_ctrlr *ctrlr; }; +/* Representation of SPI operation status. */ +enum spi_op_status { + SPI_OP_NOT_EXECUTED = 0, + SPI_OP_SUCCESS = 1, + SPI_OP_FAILURE = 2, +}; + +/* + * Representation of a SPI operation. + * + * dout: Pointer to data to send. + * bytesout: Count of data in bytes to send. + * din: Pointer to store received data. + * bytesin: Count of data in bytes to receive. + */ +struct spi_op { + const void *dout; + size_t bytesout; + void *din; + size_t bytesin; + enum spi_op_status status; +}; + /*----------------------------------------------------------------------- * Representation of a SPI contoller. * * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. - * xfer: SPI transfer * setup: Setup given SPI device bus. + * xfer: Perform one SPI transfer operation. + * xfer_vector: Vector of SPI transfer operations. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); + int (*setup)(const struct spi_slave *slave); int (*xfer)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); - int (*setup)(const struct spi_slave *slave); + int (*xfer_vector)(const struct spi_slave *slave, + struct spi_op vectors[], size_t count); }; /*----------------------------------------------------------------------- @@ -134,6 +160,19 @@ void spi_release_bus(const struct spi_slave *slave); int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); +/*----------------------------------------------------------------------- + * Vector of SPI transfer operations + * + * spi_xfer_vector() interface: + * slave: The SPI slave which will be sending/receiving the data. + * vectors: Array of SPI op structures. + * count: Number of SPI op vectors. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer_vector(const struct spi_slave *slave, + struct spi_op vectors[], size_t count); + unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len); /*----------------------------------------------------------------------- @@ -158,4 +197,17 @@ static inline int spi_w8r8(const struct spi_slave *slave, unsigned char byte) return ret < 0 ? ret : din[1]; } +/* + * Helper function to allow chipsets to combine two vectors if possible. This + * function can only handle upto 2 vectors. + * + * Two vectors are combined if first vector has a non-NULL dout and NULL din and + * second vector has a non-NULL din and NULL dout. Otherwise, each vector is + * operated upon one at a time. + * + * Returns 0 on success and non-zero on failure. + */ +int spi_xfer_two_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count); + #endif /* _SPI_GENERIC_H_ */ diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index eabab2b..ca0909b 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO # required for the reference board BCM958305K - select SPI_ATOMIC_SEQUENCING config CHROMEOS select VBOOT_VBNV_FLASH diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index e597efc..f03d453 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -279,6 +279,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index da33cc5..1ce488c 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -22,7 +22,6 @@ config CPU_IMGTEC_PISTACHIO select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_HARD_RESET select UART_OVERRIDE_REFCLK diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index e956e46..2b706f0 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -22,10 +22,6 @@ #include <string.h> #include <timer.h> -#if !CONFIG_SPI_ATOMIC_SEQUENCING -#error "Unsupported SPI driver API" -#endif - /* Imgtec controller uses 16 bit packet length. */ #define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) @@ -496,7 +492,7 @@ static int do_spi_xfer(const struct spi_slave *slave, const void *dout, } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) + size_t bytesout, void *din, size_t bytesin) { unsigned int in_sz, out_sz; int ret; @@ -541,6 +537,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; /* Set up communications parameters for a SPI slave. */ diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 0f7b0c6..639954b 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -612,6 +612,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 2a0ddf8..86b3351 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -596,6 +596,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index d2ae943..7a7eaf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -646,6 +646,7 @@ int spi_flash_protect(u32 start, u32 size) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 997bd13..dee7440 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -592,6 +592,7 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 5848966..a6b6f35 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -609,6 +609,7 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index ec3481e..7a6ad87 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8173 select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING if SPI_FLASH select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select GENERIC_GPIO_LIB diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 53d5b8c..415764a 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -293,6 +293,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index f738622..05f29e4 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ40XX select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 7ba5df5..32b61bc 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB if SOC_QC_IPQ806X diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 8a4adfb..00f6b29 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -167,6 +167,7 @@ int chipset_volatile_group_end(const struct spi_flash *flash) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index edf192a..1e84743 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -158,6 +158,7 @@ int chipset_volatile_group_end(const struct spi_flash *flash) static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 2e16ca8..5d56415 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -120,6 +120,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 093017e..ee94937 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -659,6 +659,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 8026698..0bffeb5 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -724,6 +724,7 @@ spi_xfer_exit: static const struct spi_ctrlr spi_ctrlr = { .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

1 0

Patch set updated for coreboot: mb/asus/p5gc-mx: Add mainboard
by Arthur Heymans 21 Dec '16

21 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17558 -gerrit commit e4ef3061c2601a7f8bd551e0fb0c81a3bb4b8fe2 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Nov 21 17:11:48 2016 +0100 mb/asus/p5gc-mx: Add mainboard Tested to work: * GPU (Nvidia gt210) in PCIe x16 slot; * SATA; * serial; * 800MHz and 1067MHz FSB Core 2 Duo CPUs; * ethernet; * native VGA graphic init. What does not work: * resume from s3 suspend; * superio hardware monitor (not initialised in coreboot). Quirks: * does not boot with just one dimm in slot B. Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/Kconfig | 53 +++++ src/mainboard/asus/p5gc-mx/Kconfig.name | 2 + src/mainboard/asus/p5gc-mx/Makefile.inc | 1 + src/mainboard/asus/p5gc-mx/acpi/ec.asl | 1 + src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl | 75 ++++++ src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl | 47 ++++ src/mainboard/asus/p5gc-mx/acpi/mainboard.asl | 30 +++ src/mainboard/asus/p5gc-mx/acpi/superio.asl | 1 + src/mainboard/asus/p5gc-mx/acpi/thermal.asl | 1 + src/mainboard/asus/p5gc-mx/acpi_tables.c | 22 ++ src/mainboard/asus/p5gc-mx/board_info.txt | 6 + src/mainboard/asus/p5gc-mx/cmos.default | 7 + src/mainboard/asus/p5gc-mx/cmos.layout | 97 ++++++++ src/mainboard/asus/p5gc-mx/cstates.c | 20 ++ src/mainboard/asus/p5gc-mx/devicetree.cb | 124 ++++++++++ src/mainboard/asus/p5gc-mx/dsdt.asl | 53 +++++ src/mainboard/asus/p5gc-mx/hda_verb.c | 40 ++++ src/mainboard/asus/p5gc-mx/romstage.c | 275 ++++++++++++++++++++++ 18 files changed, 855 insertions(+) diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig new file mode 100644 index 0000000..6f6eaae --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans <arthur(a)ahemans.xyz +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if BOARD_ASUS_P5GC_MX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627DHG + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_EDID + +config MAINBOARD_DIR + string + default asus/p5gc-mx + +config MAINBOARD_PART_NUMBER + string + default "P5GC-MX" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config MAX_CPUS + int + default 4 ## 2 may be the chipsets limit + +endif # BOARD_ASUS_P5GC_MX diff --git a/src/mainboard/asus/p5gc-mx/Kconfig.name b/src/mainboard/asus/p5gc-mx/Kconfig.name new file mode 100644 index 0000000..a325f58 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5GC_MX + bool "P5GC-MX" diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/asus/p5gc-mx/acpi/ec.asl b/src/mainboard/asus/p5gc-mx/acpi/ec.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..4aaa33f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 17 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 19 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 17 }, + Package() { 0x001fffff, 2, 0, 18 }, + Package() { 0x001fffff, 3, 0, 19 }, + + }) + + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..408397b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/ich7_pci_irqs.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, + + }) +} Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }, + + }) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl new file mode 100644 index 0000000..0454c3f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} diff --git a/src/mainboard/asus/p5gc-mx/acpi/superio.asl b/src/mainboard/asus/p5gc-mx/acpi/superio.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/acpi/thermal.asl b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi/thermal.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c new file mode 100644 index 0000000..ca4cde6 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/asus/p5gc-mx/board_info.txt b/src/mainboard/asus/p5gc-mx/board_info.txt new file mode 100644 index 0000000..c661268 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5GCMX/ +Release year: 2007 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default new file mode 100644 index 0000000..ab7aac1 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout new file mode 100644 index 0000000..eaf51bb --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -0,0 +1,97 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# RAM initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c new file mode 100644 index 0000000..f683756 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/cstates.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <arch/x86/include/arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb new file mode 100644 index 0000000..7064feb --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x + device lapic 0xACAC off end + end + end + + device domain 0 on + device pci 00.0 on # host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 on # i945 PCIe root port + subsystemid 0x1458 0x5000 + ioapic_irq 2 INTA 0x10 + end + device pci 02.0 on # vga controller + subsystemid 0x1458 0xd000 + ioapic_irq 2 INTA 0x10 + end + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x86" + register "pirqd_routing" = "0x85" + register "pirqe_routing" = "0x83" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x85" + + register "gpe0_en" = "0" + + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + register "p_cnt_throttling_supported" = "0" + + device pci 1b.0 on # High Definition Audio + ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + #device pci 1c.2 off end # PCIe port 3 + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on # USB UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # USB UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # USB UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1d.3 on # USB UHCI + ioapic_irq 2 INTD 0x13 + end + device pci 1d.7 on # USB2 EHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on end # PCI bridge + + device pci 1f.0 on # LPC bridge + ioapic_irq 2 INTA 0x10 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + end + device pci 1f.1 on # IDE + ioapic_irq 2 INTB 0x11 + end + device pci 1f.2 on # SATA + ioapic_irq 2 INTC 0x12 + end + device pci 1f.3 on # SMBus + ioapic_irq 2 INTD 0x13 + end + end + end +end diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl new file mode 100644 index 0000000..b55aa3f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + /* #include "acpi/platform.asl" */ + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + //#include "acpi/thermal.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c new file mode 100644 index 0000000..a9c25f3 --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0883, /* Vendor ID */ + 0x104382c7, /* Subsystem ID */ + 0x0000000c, /* Number of entries */ + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), + AZALIA_PIN_CFG(0, 0x1e, 0x18561130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c new file mode 100644 index 0000000..9be061f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz + * Copyright (C) 2016 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <halt.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> +#include <arch/cpu.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) + +void setup_ich7_gpios(void) +{ + /* TODO: This is highly board specific and should be moved */ + printk(BIOS_DEBUG, " GPIOS..."); + /* General Registers */ + outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +/* + * BSEL0 is connected with GPIO32 + * BSEL1 is connected with GPIO33 with inversed logic + * BSEL2 is connected with GPIO55 + */ +static void setup_sio_gpio(u8 bsel) +{ + int need_reset = 0; + u8 reg, old_reg; + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + reg = 0x9a; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + + pnp_write_config(GPIO_DEV, 0x30, 0x0e); + pnp_write_config(GPIO_DEV, 0xe0, 0xde); + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); + pnp_write_config(GPIO_DEV, 0xf4, 0x80); + pnp_write_config(GPIO_DEV, 0xf5, 0x80); + + /* Invert GPIO33 */ + pnp_write_config(GPIO_DEV, 0xf2, 0x08); + + reg = (bsel & 3) << 2; + old_reg = pnp_read_config(GPIO_DEV, 0xf1); + pnp_write_config(GPIO_DEV, 0xf1, reg); + need_reset += ((reg & 0xc) != (old_reg & 0xc)); + + reg = (bsel >> 2) << 5; + old_reg = pnp_read_config(GPIO_DEV, 0xe1); + pnp_write_config(GPIO_DEV, 0xe1, reg); + need_reset += ((reg & 0x20) != (old_reg & 0x20)); + + pnp_exit_ext_func_mode(GPIO_DEV); + + if (need_reset) { + int i = 1000; + while (i--) + outb(i & 0xff, 0x80); + outb(0xe, 0xcf9); + halt(); + } +} + +static u8 msr_get_fsb(void) +{ + u8 fsbcfg; + msr_t msr; + const u32 eax = cpuid_eax(1); + + /* Netburst */ + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(0x2c); + fsbcfg = (msr.lo >> 16) & 0x7; + } else { /* Intel Core 2 */ + msr = rdmsr(MSR_FSB_FREQ); + fsbcfg = msr.lo & 0x7; + } + + return fsbcfg; +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140f); + // Enable SuperIO Power Management Events + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801); + + /* range 0x15e0 - 0x10ef */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291); + + +} + +static void rcba_config(void) +{ + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Disable unused devices */ + RCBA32(0x3418) = 0x003c0061; + + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030509; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void mainboard_romstage_entry(unsigned long bist) +{ + int s3resume = 0, boot_mode = 0; + + u8 m_bsel; + u8 c_bsel = msr_get_fsb(); + + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + setup_sio_gpio(c_bsel); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected.\n"); + boot_mode = 1; + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + m_bsel = MCHBAR32(CLKCFG) & 7; + printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel); + if (c_bsel != m_bsel) { /* Should not happen */ + printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n"); + outb(0xe, 0xcf9); + halt(); + } + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(s3resume ? 2 : boot_mode, NULL); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +}

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Patch set updated for coreboot: agesawrapper: Fix endless loop on bettong
by Ricardo Ribalda Delgado 21 Dec '16

21 Dec '16

Ricardo Ribalda Delgado (ricardo.ribalda(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17924 -gerrit commit e12095ff877b8a059cbc7d800934e6d022ebf84e Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Tue Dec 20 10:08:45 2016 +0100 agesawrapper: Fix endless loop on bettong AGESA AmdInitEarly() reconfigures the lapic timer in a way that conflicts with lapic/apic_timer. This results in an endless loop when printk() is called after AmdInitEarly() and before the apic_timer is initialized. This patch forces a reconfiguration of the timer after AmdInitEarly() is called. Codepath of the endless loop: printk()-> (...)-> uart_tx_byte-> uart8250_mem_tx_byte-> udelay()-> start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while ((start - value) < ticks); [lapic_read returns the same value after AmdInitEarly()] Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- src/northbridge/amd/pi/agesawrapper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 8e16e75..0edfc13 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -15,6 +15,7 @@ #include <AGESA.h> #include <cbfs.h> +#include <delay.h> #include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> @@ -107,6 +108,13 @@ AGESA_STATUS agesawrapper_amdinitearly(void) AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled; status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); +#if CONFIG_BOARD_AMD_BETTONG + /* + * init_timer() needs to be called on CZ PI, because AGESA resets the LAPIC reload value + * on the AMD_INIT_EARLY call + */ + init_timer(); +#endif if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct);

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coreboot-gerrit December 2016