Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17940
-gerrit
commit 858d4a2efeebd07457753d5cc4e6d89ad4271699
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Dec 22 10:29:20 2016 -0700
Microcode: Show a useful warning when microcode bins are missing
Because the binary repo is disabled by default, we get frequent
questions about why the build failed, relating to microcode in the
binary repository.
- Show an error saying that the file is missing instead of the typical
make error of no rule to build the file.
- Show a note encouraging users to try enabling the binary repo if it's
not enabled.
Change-Id: If4148c18cfb781ed2932bd2ae4a289b621afdebf
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
src/cpu/Makefile.inc | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 4ac6812..f74e354 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -37,7 +37,19 @@ endif
# updates are wrapped in a container, like AMD's microcode update container. If
# there is only one microcode binary (i.e. one container), then we don't have
# this issue, and this rule will continue to work.
-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
+$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
+ for bin in $(cpu_microcode_bins); do \
+ if [ ! -f "$$bin" ]; then \
+ echo "Microcode error: $$bin does not exist"; \
+ NO_MICROCODE_FILE=1; \
+ fi; \
+ done; \
+ if [ -n "$$NO_MICROCODE_FILE" ]; then \
+ if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)" ]; then \
+ echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
+ fi; \
+ false; \
+ fi
@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
@echo $(cpu_microcode_bins)
cat /dev/null $+ > $@
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17960
-gerrit
commit 98de2d9c28c8e11fcd75789f1e378e81664f4ac6
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Fri Dec 23 14:56:12 2016 -0600
google/auron: Fix omitted ACPI KB backlight for variants
Restores KB backlight functionality for auron variants
gandof, lulu, and saumus
TEST: boot Lulu and observe KB backlight functional
Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/auron/acpi/ec.asl | 3 +++
.../variants/auron_paine/include/variant/acpi/ec.asl | 0
.../auron/variants/auron_yuna/include/variant/acpi/ec.asl | 0
.../auron/variants/gandof/include/variant/acpi/ec.asl | 15 +++++++++++++++
.../auron/variants/lulu/include/variant/acpi/ec.asl | 15 +++++++++++++++
.../auron/variants/samus/include/variant/acpi/ec.asl | 15 +++++++++++++++
6 files changed, 48 insertions(+)
diff --git a/src/mainboard/google/auron/acpi/ec.asl b/src/mainboard/google/auron/acpi/ec.asl
index c6cf506..98b34af 100644
--- a/src/mainboard/google/auron/acpi/ec.asl
+++ b/src/mainboard/google/auron/acpi/ec.asl
@@ -16,5 +16,8 @@
/* mainboard configuration */
#include "ec.h"
+/*variant configuration */
+#include <variant/acpi/ec.asl>
+
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl
new file mode 100644
index 0000000..12b59b4
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl
new file mode 100644
index 0000000..12b59b4
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl
new file mode 100644
index 0000000..12b59b4
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17959
-gerrit
commit 581c28271a0eb7608d2a41c4ec5e6cda1f85e378
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Fri Dec 23 12:20:47 2016 -0800
intel/wifi: Create ACPI objects for wifi SAR configuration
To support intel wifi SAR configuration, it is required coreboot
to publish two ACPI objects (WRDS and EWRD) to supply SAR limit
data sets. VPD is to supply the raw SAR limit data.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/drivers/intel/wifi/Kconfig | 21 +++++++++++++++++
src/drivers/intel/wifi/wifi.c | 53 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig
index 330de6c..10d09fe 100644
--- a/src/drivers/intel/wifi/Kconfig
+++ b/src/drivers/intel/wifi/Kconfig
@@ -5,3 +5,24 @@ config DRIVERS_INTEL_WIFI
help
When enabled, add identifiers in ACPI and SMBIOS tables to
make OS drivers work with certain Intel PCI-e WiFi chipsets.
+
+config USE_SAR
+ bool
+ default n
+ help
+ Enable it when wifi driver uses SAR configuration feature.
+ VPD entry "wifi_sar" is required to support it.
+
+config SAR_ENABLE
+ bool
+ default n
+
+config DSAR_ENABLE
+ bool
+ default n
+
+config DSAR_SET_NUM
+ hex "Number of SAR sets when D-SAR is enabled"
+ default 0x3
+ help
+ There can be up to 3 optional SAR table sets
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index 789d0d5..3ac9d00 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <sar.h>
#include <smbios.h>
#include <string.h>
#include <wrdd.h>
@@ -105,6 +106,58 @@ static void intel_wifi_fill_ssdt(struct device *dev)
acpigen_pop_len();
}
+ /* Fill Wifi SAR related structures */
+ if (IS_ENABLED(CONFIG_USE_SAR)) {
+ int i;
+ const struct wifi_sar_limit_t *sar_t = wifi_sar_limits();
+
+ /*
+ * Name ("WRDS", Package () {
+ * Revision,
+ * Package () {
+ * Domain Type, // 0x7:WiFi
+ * WiFi SAR BIOS, // BIOS SAR Enable/disable
+ * SAR Table Set // Set#1 of SAR Table (10 bytes)
+ * }
+ * })
+ */
+ acpigen_write_name("WRDS");
+ acpigen_write_package(2);
+ acpigen_write_dword(WRDS_REVISION);
+ acpigen_write_package(2);
+ acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI);
+ acpigen_write_dword(CONFIG_SAR_ENABLE);
+ for (i = 0; i < BYTES_OF_SAR_SET; i++)
+ acpigen_write_byte(*(&sar_t->sar_limit[0] + i));
+ acpigen_pop_len();
+ acpigen_pop_len();
+
+ /*
+ * Name ("EWRD", Package () {
+ * Revision,
+ * Package () {
+ * Domain Type, // 0x7:WiFi
+ * Dynamic SAR Enable, // Dynamic SAR Enable/disable
+ * Extended SAR sets, // Number of optional SAR table sets
+ * SAR Table Set, // Set#2 of SAR Table (10 bytes)
+ * SAR Table Set, // Set#3 of SAR Table (10 bytes)
+ * SAR Table Set // Set#4 of SAR Table (10 bytes)
+ * }
+ * })
+ */
+ acpigen_write_name("EWRD");
+ acpigen_write_package(2);
+ acpigen_write_dword(EWRD_REVISION);
+ acpigen_write_package(2);
+ acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI);
+ acpigen_write_dword(CONFIG_DSAR_ENABLE);
+ acpigen_write_dword(CONFIG_DSAR_SET_NUM);
+ for (i = 0; i < BYTES_OF_SAR_SET * 3; i++)
+ acpigen_write_byte(*(&sar_t->sar_limit[10] + i));
+ acpigen_pop_len();
+ acpigen_pop_len();
+ }
+
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17959
-gerrit
commit 654db10b46f0320655b5d99d3af6198142aa6bbc
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Fri Dec 23 12:20:47 2016 -0800
intel/wifi: Create ACPI objects for wifi SAR configuration
To support intel wifi SAR configuration, it is required coreboot
to publish two ACPI objects (WRDS and EWRD) to supply SAR limit
data sets. VPD is to supply the raw SAR limit data.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/drivers/intel/wifi/Kconfig | 21 +++++++++++++++++
src/drivers/intel/wifi/wifi.c | 53 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig
index 330de6c..32b5900 100644
--- a/src/drivers/intel/wifi/Kconfig
+++ b/src/drivers/intel/wifi/Kconfig
@@ -5,3 +5,24 @@ config DRIVERS_INTEL_WIFI
help
When enabled, add identifiers in ACPI and SMBIOS tables to
make OS drivers work with certain Intel PCI-e WiFi chipsets.
+
+config USE_SAR
+ bool
+ default y
+ help
+ Enable it when wifi driver uses SAR configuration feature.
+ VPD entry "wifi_sar" is required to support it.
+
+config SAR_ENABLE
+ bool
+ default n
+
+config DSAR_ENABLE
+ bool
+ default n
+
+config DSAR_SET_NUM
+ hex "Number of SAR sets when D-SAR is enabled"
+ default 0x3
+ help
+ There can be up to 3 optional SAR table sets
\ No newline at end of file
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index 789d0d5..3ac9d00 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <sar.h>
#include <smbios.h>
#include <string.h>
#include <wrdd.h>
@@ -105,6 +106,58 @@ static void intel_wifi_fill_ssdt(struct device *dev)
acpigen_pop_len();
}
+ /* Fill Wifi SAR related structures */
+ if (IS_ENABLED(CONFIG_USE_SAR)) {
+ int i;
+ const struct wifi_sar_limit_t *sar_t = wifi_sar_limits();
+
+ /*
+ * Name ("WRDS", Package () {
+ * Revision,
+ * Package () {
+ * Domain Type, // 0x7:WiFi
+ * WiFi SAR BIOS, // BIOS SAR Enable/disable
+ * SAR Table Set // Set#1 of SAR Table (10 bytes)
+ * }
+ * })
+ */
+ acpigen_write_name("WRDS");
+ acpigen_write_package(2);
+ acpigen_write_dword(WRDS_REVISION);
+ acpigen_write_package(2);
+ acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI);
+ acpigen_write_dword(CONFIG_SAR_ENABLE);
+ for (i = 0; i < BYTES_OF_SAR_SET; i++)
+ acpigen_write_byte(*(&sar_t->sar_limit[0] + i));
+ acpigen_pop_len();
+ acpigen_pop_len();
+
+ /*
+ * Name ("EWRD", Package () {
+ * Revision,
+ * Package () {
+ * Domain Type, // 0x7:WiFi
+ * Dynamic SAR Enable, // Dynamic SAR Enable/disable
+ * Extended SAR sets, // Number of optional SAR table sets
+ * SAR Table Set, // Set#2 of SAR Table (10 bytes)
+ * SAR Table Set, // Set#3 of SAR Table (10 bytes)
+ * SAR Table Set // Set#4 of SAR Table (10 bytes)
+ * }
+ * })
+ */
+ acpigen_write_name("EWRD");
+ acpigen_write_package(2);
+ acpigen_write_dword(EWRD_REVISION);
+ acpigen_write_package(2);
+ acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI);
+ acpigen_write_dword(CONFIG_DSAR_ENABLE);
+ acpigen_write_dword(CONFIG_DSAR_SET_NUM);
+ for (i = 0; i < BYTES_OF_SAR_SET * 3; i++)
+ acpigen_write_byte(*(&sar_t->sar_limit[10] + i));
+ acpigen_pop_len();
+ acpigen_pop_len();
+ }
+
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17956
-gerrit
commit 29999fb6b4fe04c90dbbea35a49068241f2ccdeb
Author: Subrata Banik <subrata.banik(a)intel.com>
Date: Fri Dec 23 16:42:55 2016 +0530
soc/intel/skylake: Initialize LPSS UART based on DRIVERS_UART_8250MEM_32
pch_uart_init and base address assignment should be done
based on DRIVERS_UART_8250MEM_32 config selection. Enabling
legacy UART for debug on RVP does not require additional UART2
programming.
TEST=Build and boot SKL RVP to have serial log through legacy UART.
Change-Id: Iea4f204275c6eb78646f510a7097f7cf8470b576
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
src/soc/intel/skylake/bootblock/bootblock.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 93a031f..1c0892f 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -29,8 +29,10 @@ void bootblock_soc_early_init(void)
bootblock_cpu_init();
pch_early_iorange_init();
- if (IS_ENABLED(CONFIG_UART_DEBUG))
- pch_uart_init();
+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
+ return;
+
+ pch_uart_init();
}
void bootblock_soc_init(void)
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17958
-gerrit
commit 6f22b439e10c9ab791391a19148a65d5b67a4aaf
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Fri Dec 23 11:43:07 2016 -0800
chromeos: Implement locating and decoding wifi sar data from VPD
A VPD entry "wifi_sar" needs to be created which contains a heximal
encoded string in length of 40 bytes. wifi_sar_limits() function
retrives and decodes the data from the VPD entry, returning pointer
to an instance of the structure (array of 40 bytes (u8)), which
would be later consumed by platform code needing this data.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: I923b58a63dc1f8a7fdd685cf1c618b2fdf4e7061
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/include/sar.h | 43 ++++++++++++++
src/vendorcode/google/chromeos/Makefile.inc | 1 +
src/vendorcode/google/chromeos/cros_vpd.h | 1 +
src/vendorcode/google/chromeos/sar.c | 92 +++++++++++++++++++++++++++++
4 files changed, 137 insertions(+)
diff --git a/src/include/sar.h b/src/include/sar.h
new file mode 100644
index 0000000..bf3e4a5
--- /dev/null
+++ b/src/include/sar.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _SAR_H_
+#define _SAR_H_
+
+#include <stdint.h>
+
+/* WRDS Spec Revision */
+#define WRDS_REVISION 0x0
+
+/* EWRD Spec Revision */
+#define EWRD_REVISION 0x0
+
+/* WRDS Domain type */
+#define WRDS_DOMAIN_TYPE_WIFI 0x7
+
+/* EWRD Domain type */
+#define EWRD_DOMAIN_TYPE_WIFI 0x7
+
+/* Number of bytes for a SAR set */
+#define BYTES_OF_SAR_SET 10
+
+/* Wifi SAR limit table structure */
+struct wifi_sar_limit_t{
+ u8 sar_limit[40]; /* Total 4 SAR limit sets, each contains 10 bytes */
+};
+
+/* Retrieve the SAR limits data from VPD */
+struct wifi_sar_limit_t *wifi_sar_limits(void);
+
+#endif /* _SAR_H_ */
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index e84eb3d..878b068 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -25,6 +25,7 @@ ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
romstage-y += vpd_decode.c
ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c
ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c
+ramstage-$(CONFIG_USE_SAR) += sar.c
ifeq ($(CONFIG_ARCH_MIPS),)
bootblock-y += watchdog.c
ramstage-y += watchdog.c
diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h
index 96ca8af..1fa56a4 100644
--- a/src/vendorcode/google/chromeos/cros_vpd.h
+++ b/src/vendorcode/google/chromeos/cros_vpd.h
@@ -8,6 +8,7 @@
#define __CROS_VPD_H__
#define CROS_VPD_REGION_NAME "region"
+#define CROS_VPD_WIFI_SAR_NAME "wifi_sar"
/*
* Reads VPD string value by key.
diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c
new file mode 100644
index 0000000..24cf73b
--- /dev/null
+++ b/src/vendorcode/google/chromeos/sar.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <console/console.h>
+#include <types.h>
+#include <string.h>
+#include <sar.h>
+#include "cros_vpd.h"
+
+/*
+ * Decode string representation of the SAR limits (a string of hex symbols)
+ * into binary. 'key_name' is the name of the VPD field, it's used if
+ * it is necessary to report an input data format problem.
+ */
+static void decode_sar_limit(struct wifi_sar_limit_t *sar_limits,
+ const char *sar_limit_str,
+ const char *key_name)
+{
+ int i;
+ int size = sizeof(struct wifi_sar_limit_t) / sizeof(u8);
+
+ for (i = 0; i < size; i++) {
+ int j;
+ int n = 0;
+
+ for (j = 0; j < 2; j++) {
+ char c = sar_limit_str[i * 2 + j];
+ if (isxdigit(c)) {
+ if (isdigit(c))
+ c = c - '0';
+ else
+ c = tolower(c) - 'a' + 10;
+ } else {
+ printk(BIOS_ERR, "%s: non hexadecimal symbol "
+ "%#2.2x in the VPD field %s:%s\n",
+ __func__, (uint8_t)c, key_name,
+ sar_limit_str);
+ }
+ n <<= 4;
+ n |= c;
+ }
+ sar_limits->sar_limit[i] = n;
+ }
+}
+
+/*
+ * Retrieve the wifi SAR limits from VPD
+ * If the information is not found in the VPD, this function will
+ * return a NULL pointer.
+ */
+struct wifi_sar_limit_t *wifi_sar_limits(void)
+{
+ struct wifi_sar_limit_t *p;
+ const char *wifi_sar_limit_key = CROS_VPD_WIFI_SAR_NAME;
+ /*
+ * cros_vpd_gets() reads in one less than size characters from the VPD
+ * with a terminating null byte ('\0') stored as the last character into
+ * the buffer, thus the increasing by 1 for buffer_size.
+ */
+ int buffer_size = (sizeof(struct wifi_sar_limit_t) / sizeof(u8)) * 2 + 1;
+ char wifi_sar_limit_str[buffer_size];
+
+ p = malloc(sizeof(struct wifi_sar_limit_t));
+ if (!p) {
+ printk(BIOS_ERR, "Wifi SAR: Could not allocate memory\n");
+ return NULL;
+ }
+
+ /* Try to read the SAR limit entry from VPD */
+ if (!cros_vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str,
+ ARRAY_SIZE(wifi_sar_limit_str))) {
+ printk(BIOS_DEBUG,
+ "Error: Could not locate '%s' in VPD\n", wifi_sar_limit_key);
+ return NULL;
+ }
+ printk(BIOS_ERR, "VPD wifi_sar = %s\n", wifi_sar_limit_str);
+
+ /* Decode the heximal encoded string to binary values */
+ decode_sar_limit(p, wifi_sar_limit_str, wifi_sar_limit_key);
+ return p;
+}
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17936
-gerrit
commit 31c3dfeff1571d328a8b647e33648c356f582d64
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Thu Dec 22 16:05:54 2016 +0100
buildgcc: Build GMP `--with-pic` if GCC defaults to `-pie`
GCC 6 can optionally default to building all binaries as position
independent executables (PIE). This breaks linking against static
libraries that are compiled without position independent code (PIC).
Building GMP `--with-pic` in this case seems to be the least fragile
solution.
TEST=Run `make all` and `make BUILDGCC_OPTIONS=-b build-i386` in
util/crossgcc on Debian Stretch.
Change-Id: I5f3185af9c8d599379a628e18724b217b88be974
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
util/crossgcc/buildgcc | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 97c38b8..30e2188 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -515,6 +515,13 @@ set_hostcflags_from_gmp() {
}
build_GMP() {
+ # Check if GCC enables `-pie` by default (possible since GCC 6).
+ # We need PIC in all static libraries then.
+ if "${CC}" -dumpspecs 2>/dev/null | grep -q '[{;][[:space:]]*:-pie\>'
+ then
+ OPTIONS="$OPTIONS --with-pic"
+ fi
+
CC="$CC" ../${GMP_DIR}/configure --disable-shared --enable-fat \
--prefix=$TARGETDIR $OPTIONS \
|| touch .failed