coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mb/asus/p5gc-mx: Fix and complete SIO devicetree options
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17965 -gerrit commit 9d3de1fa5385d7c20d08b51d945f9a6663a8ec16 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 17:52:15 2016 +0100 mb/asus/p5gc-mx: Fix and complete SIO devicetree options The devicetree lacks the 'chip' option for the Super I/O, which causes the Super I/O related entries to be ignored. This also adds other LDN that are present on this Super I/O. Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/devicetree.cb | 60 ++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 7064feb..824beed 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -85,29 +85,43 @@ chip northbridge/intel/i945 device pci 1f.0 on # LPC bridge ioapic_irq 2 INTA 0x10 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 + device pnp 2e.8 off end # WDTO# & PLED + device pnp 2e.9 on end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0x70 = 0 + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c on end # PECI, SST end end device pci 1f.1 on # IDE

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Patch set updated for coreboot: mb/asus/p5gc-mx: Fix and complete SIO devicetree options
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17965 -gerrit commit 752ee20d337168a0b22e9253ed959ab10bb8e63b Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 17:52:15 2016 +0100 mb/asus/p5gc-mx: Fix and complete SIO devicetree options The devicetree lacks the 'chip' option for the Super I/O, which causes the Super I/O related entries to be ignored. This also adds other LDN that are present on this Super I/O. Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/devicetree.cb | 60 ++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 7064feb..07a2afe 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -85,29 +85,43 @@ chip northbridge/intel/i945 device pci 1f.0 on # LPC bridge ioapic_irq 2 INTA 0x10 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 + device pnp 2e.8 off end # WDTO# & PLED + device pnp 2e.9 on end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0x70 = 0 + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + device pnp 2e.c on end # PECI, SST + end end end device pci 1f.1 on # IDE

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Patch set updated for coreboot: superiotool: Add support for HWM registers on W83627EHG
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17457 -gerrit commit f7b4b6bdc04912f89adeb16c961840f3bf54875f Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 17 08:56:09 2016 +0100 superiotool: Add support for HWM registers on W83627EHG Based on datasheet: "W83627EHF/EF W83627EHG/EG WINBOND LPC I/O, Revision : 1.0" Change-Id: Ia2e5ab8bc454a34a89fe2cf06bfba55261109785 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/superiotool/winbond.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c index 7e9976c..281c179 100644 --- a/util/superiotool/winbond.c +++ b/util/superiotool/winbond.c @@ -772,6 +772,57 @@ static const struct superio_registers hwm_table[] = { {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, {EOT}}}, + {0x88, "W83627EHF/EF/EHG/EG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,EOT}, + {0x04,0xff,0x04,0xff,0x01,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,0x04,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,RSVD,RSVD,RSVD,RSVD, + RSVD,RSVD,EOT}}, + {NOLDN, NULL, /* Value RAM */ + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33, + 0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d, + 0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,NANA,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {0x03,0x00,0x00,0xde,0xff,RSVD,0x07,0x55,0x2d,RSVD, + 0x64,0x44,0x10,0x15,0x80,0x5c,EOT}}, + {0x0, "Bank 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63, + 0x64,0x65,0x66,0x67,0x68,0x69,0x6a,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,0x00,0x80,0xa1,0x70, + RSVD,RSVD,RSVD,0x00,RSVD,RSVD,0x04,0xff,0x40,0x00, + 0x01,0x01,0x3c,0xff,0x01,0xff,0x01,EOT}}, + {0x1, "Bank 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "Bank 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "Bank 4", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,EOT}, + {0x00,0x00,RSVD,0x00,0x00,0x00,0x00,RSVD,RSVD,0x00, + 0x00,0x00,RSVD,RSVD,EOT}}, + {0x5, "Bank 5", /* Value RAM 2 */ + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,EOT}, + {NANA,NANA,RSVD,RSVD,MISC,MISC,MISC,MISC,MISC,MISC, + RSVD,RSVD,MISC,EOT}}, + {0x6, "Bank 6", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {EOT}}}, {0xb07, "W83627DHG-P/-PT", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,

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Patch set updated for coreboot: superiotool: Add support for HWM registers on W83627DHG
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17964 -gerrit commit e2c3f93df6a43a302063ce5c30acfe58b72aca4c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 15:26:44 2016 +0100 superiotool: Add support for HWM registers on W83627DHG Based on datasheet: "W83627DHG WINBOND LPC I/O, Version: 1.4" Change-Id: Id20dff7539d926ef6f68265efbfc7420539d9bca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/superiotool/winbond.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c index bc56aaf..7e9976c 100644 --- a/util/superiotool/winbond.c +++ b/util/superiotool/winbond.c @@ -719,6 +719,59 @@ static const struct superio_registers hwm_table[] = { {0x50,EOT}, {RSVD,EOT}}, {EOT}}}, + {0xa02, "W83627DHG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,EOT}, + {0x04,0xff,0x04,NANA,0x01,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,0x04,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,RSVD,RSVD,RSVD,RSVD, + RSVD,RSVD,EOT}}, + {NOLDN, NULL, /* Value RAM */ + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33, + 0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d, + 0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {0x03,0x00,0x00,0xff,0xff,RSVD,0x07,0x55,0x2d,0x00, + 0x00,0x44,0x10,0x95,0x80,0xa3,EOT}}, + {0x0, "Bank 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63, + 0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x6b,0x6c,0x6d, + 0x6e,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,0x00,0x80,0xc1,0x70, + RSVD,RSVD,RSVD,0x04,0x04,RSVD,0x04,NANA,0x40,0x00, + 0x01,0x01,0x3c,0xff,0x01,0xff,0x01,0xff,0xff,0xff, + 0xff,EOT}}, + {0x1, "Bank 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "Bank 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "Bank 4", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {0x00,0x13,RSVD,0x00,0x00,0x00,0x00,RSVD,RSVD,0x00, + 0x00,0x00,RSVD,RSVD,RSVD,RSVD,EOT}}, + {0x5, "Bank 5", /* Value RAM 2 */ + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,EOT}, + {NANA,NANA,RSVD,NANA,MISC,MISC,MISC,MISC,RSVD,RSVD, + RSVD,RSVD,MISC,EOT}}, + {0x6, "Bank 6", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {EOT}}}, {0xb07, "W83627DHG-P/-PT", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,

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Patch set updated for coreboot: google/auron: Fix omitted ACPI KB backlight for variants
by Matt DeVillier 25 Dec '16

25 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17960 -gerrit commit f340269f9751ff7816d688816c4960b65a4a645c Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri Dec 23 14:56:12 2016 -0600 google/auron: Fix omitted ACPI KB backlight for variants Restores KB backlight functionality for auron variants gandof, lulu, and samus. TEST: boot Lulu and observe KB backlight functional Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/auron/acpi/ec.asl | 3 +++ .../variants/auron_paine/include/variant/acpi/ec.asl | 0 .../auron/variants/auron_yuna/include/variant/acpi/ec.asl | 0 .../auron/variants/gandof/include/variant/acpi/ec.asl | 15 +++++++++++++++ .../auron/variants/lulu/include/variant/acpi/ec.asl | 15 +++++++++++++++ .../auron/variants/samus/include/variant/acpi/ec.asl | 15 +++++++++++++++ 6 files changed, 48 insertions(+) diff --git a/src/mainboard/google/auron/acpi/ec.asl b/src/mainboard/google/auron/acpi/ec.asl index c6cf506..98b34af 100644 --- a/src/mainboard/google/auron/acpi/ec.asl +++ b/src/mainboard/google/auron/acpi/ec.asl @@ -16,5 +16,8 @@ /* mainboard configuration */ #include "ec.h" +/*variant configuration */ +#include <variant/acpi/ec.asl> + /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl new file mode 100644 index 0000000..12b59b4 --- /dev/null +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl new file mode 100644 index 0000000..12b59b4 --- /dev/null +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl new file mode 100644 index 0000000..12b59b4 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT

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New patch to review for coreboot: mb/asus/p5gc-mx: Fix and complete SIO devicetree options
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17965 -gerrit commit ee36747d78d947aa4fb81e4275a131daf51a06b3 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 17:52:15 2016 +0100 mb/asus/p5gc-mx: Fix and complete SIO devicetree options The devicetree lacked the 'chip' option for the Super I/O. This also adds other LDN that are present on this Super I/O. The consequence is that the HWM device can now be used (default is off). Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/devicetree.cb | 59 +++++++++++++++++++------------- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 7064feb..753149c 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -85,29 +85,42 @@ chip northbridge/intel/i945 device pci 1f.0 on # LPC bridge ioapic_irq 2 INTA 0x10 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 + device pnp 2e.8 off end # WDTO# & PLED + device pnp 2e.9 on end #GPIO2-5 + device pnp 2e.a on # ACPI + irq 0x70 = 0 + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + end end end device pci 1f.1 on # IDE

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Patch set updated for coreboot: superiotool: Add support for HWM registers on W83627EHG
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17457 -gerrit commit 8e647c4b60eacbddda137aa1b98d649218ea8fb5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 17 08:56:09 2016 +0100 superiotool: Add support for HWM registers on W83627EHG Based on datasheet: "W83627EHF/EF W83627EHG/EG WINBOND LPC I/O, Revision : 1.0" Change-Id: Ia2e5ab8bc454a34a89fe2cf06bfba55261109785 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/superiotool/winbond.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c index 5263398..9e76540 100644 --- a/util/superiotool/winbond.c +++ b/util/superiotool/winbond.c @@ -774,6 +774,58 @@ static const struct superio_registers hwm_table[] = { {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, {EOT}}}, + {0x88, "W83627EHF/EF/EHG/EG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,EOT}, + {0x04,0xff,0x04,0xff,0x01,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,0x04,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,RSVD,RSVD,RSVD,RSVD, + RSVD,RSVD,EOT}}, + {NOLDN, NULL, /* Value RAM */ + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33, + 0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d, + 0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,NANA,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {0x03,0x00,0x00,0xde,0xff,RSVD,0x07,0x55,0x2d,RSVD, + 0x64,0x44,0x10,0x15,0x80,0x5c,EOT}}, + {0x0, "Bank 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63, + 0x64,0x65,0x66,0x67,0x68,0x69,0x6a,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,0x00,0x80,0xa1,0x70, + RSVD,RSVD,RSVD,0x00,RSVD,RSVD,0x04,0xff,0x40,0x00, + 0x01,0x01,0x3c,0xff,0x01,0xff,0x01,EOT}}, + {0x1, "Bank 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "Bank 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "Bank 4", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,EOT}, + {0x00,0x00,RSVD,0x00,0x00,0x00,0x00,RSVD,RSVD,0x00, + 0x00,0x00,RSVD,RSVD,EOT}}, + {0x5, "Bank 5", /* Value RAM 2 */ + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,EOT}, + {NANA,NANA,RSVD,RSVD,MISC,MISC,MISC,MISC,MISC,MISC, + RSVD,RSVD,MISC,EOT}}, + {0x6, "Bank 6", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {EOT}}}, + {0xb07, "W83627DHG-P/-PT", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,

1 0

Patch set updated for coreboot: superiotool: Add support for HWM registers on W83627DHG
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17964 -gerrit commit 7fb19e1ff9aa22e4a4075b6b5bf864e337127c85 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 15:26:44 2016 +0100 superiotool: Add support for HWM registers on W83627DHG Based on datasheet: "W83627DHG WINBOND LPC I/O, Version: 1.4" Change-Id: Id20dff7539d926ef6f68265efbfc7420539d9bca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/superiotool/winbond.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c index bc56aaf..5263398 100644 --- a/util/superiotool/winbond.c +++ b/util/superiotool/winbond.c @@ -719,6 +719,61 @@ static const struct superio_registers hwm_table[] = { {0x50,EOT}, {RSVD,EOT}}, {EOT}}}, + + {0xa02, "W83627DHG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,EOT}, + {0x04,0xff,0x04,NANA,0x01,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,0x04,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,RSVD,RSVD,RSVD,RSVD, + RSVD,RSVD,EOT}}, + {NOLDN, NULL, /* Value RAM */ + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33, + 0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d, + 0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {0x03,0x00,0x00,0xff,0xff,RSVD,0x07,0x55,0x2d,0x00, + 0x00,0x44,0x10,0x95,0x80,0xa3,EOT}}, + {0x0, "Bank 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63, + 0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x6b,0x6c,0x6d, + 0x6e,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,0x00,0x80,0xc1,0x70, + RSVD,RSVD,RSVD,0x04,0x04,RSVD,0x04,NANA,0x40,0x00, + 0x01,0x01,0x3c,0xff,0x01,0xff,0x01,0xff,0xff,0xff, + 0xff,EOT}}, + {0x1, "Bank 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "Bank 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "Bank 4", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {0x00,0x13,RSVD,0x00,0x00,0x00,0x00,RSVD,RSVD,0x00, + 0x00,0x00,RSVD,RSVD,RSVD,RSVD,EOT}}, + {0x5, "Bank 5", /* Value RAM 2 */ + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,EOT}, + {NANA,NANA,RSVD,NANA,MISC,MISC,MISC,MISC,RSVD,RSVD, + RSVD,RSVD,MISC,EOT}}, + {0x6, "Bank 6", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {EOT}}}, + {0xb07, "W83627DHG-P/-PT", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,

1 0

New patch to review for coreboot: superiotool: Add support for HWM registers on W83627DHG
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17964 -gerrit commit 76ba86514a08bcf8769852edb5bc032fd362b6ed Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 15:26:44 2016 +0100 superiotool: Add support for HWM registers on W83627DHG Based on datasheet: "W83627DHG WINBOND LPC I/O, Version: 1.4" Change-Id: Id20dff7539d926ef6f68265efbfc7420539d9bca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/superiotool/winbond.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c index bc56aaf..34f3999 100644 --- a/util/superiotool/winbond.c +++ b/util/superiotool/winbond.c @@ -719,6 +719,60 @@ static const struct superio_registers hwm_table[] = { {0x50,EOT}, {RSVD,EOT}}, {EOT}}}, + {0xa02, "W83627DHG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,EOT}, + {0x04,0xff,0x04,NANA,0x01,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,0x04,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,RSVD,RSVD,RSVD,RSVD, + RSVD,RSVD,EOT}}, + {NOLDN, NULL, /* Value RAM */ + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33, + 0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d, + 0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49, + 0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {0x03,0x00,0x00,0xff,0xff,RSVD,0x07,0x55,0x2d,0x00, + 0x00,0x44,0x10,0x95,0x80,0xa3,EOT}}, + {0x0, "Bank 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63, + 0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x6b,0x6c,0x6d, + 0x6e,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,0x00,0x80,0xc1,0x70, + RSVD,RSVD,RSVD,0x04,0x04,RSVD,0x04,NANA,0x40,0x00, + 0x01,0x01,0x3c,0xff,0x01,0xff,0x01,0xff,0xff,0xff, + 0xff,EOT}}, + {0x1, "Bank 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "Bank 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "Bank 4", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {0x00,0x13,RSVD,0x00,0x00,0x00,0x00,RSVD,RSVD,0x00, + 0x00,0x00,RSVD,RSVD,RSVD,RSVD,EOT}}, + {0x5, "Bank 5", /* Value RAM 2 */ + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5a,0x5b,0x5c,EOT}, + {NANA,NANA,RSVD,NANA,MISC,MISC,MISC,MISC,RSVD,RSVD, + RSVD,RSVD,MISC,EOT}}, + {0x6, "Bank 6", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {EOT}}}, + {0xb07, "W83627DHG-P/-PT", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,

1 0

Patch set updated for coreboot: superio/w83627dhg: Add power_on_fail cmos option
by Arthur Heymans 25 Dec '16

25 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17963 -gerrit commit bf5872c3362e40e5e33895203299efa03593e956 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Dec 25 10:58:02 2016 +0100 superio/w83627dhg: Add power_on_fail cmos option This change allows to configure the power-loss control bits of the superio. An entry to cmos.default was added if the motherboard already featured such a file. Change-Id: I4eaa8ad61f6d89cbfd541fc6e1b06710ce41b7a4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asrock/939a785gmh/cmos.layout | 5 ++++- src/mainboard/asus/p5gc-mx/cmos.default | 3 ++- src/mainboard/asus/p5gc-mx/cmos.layout | 8 +++++++- src/mainboard/kontron/kt690/cmos.layout | 5 ++++- src/mainboard/lippert/toucan-af/cmos.layout | 5 ++++- src/mainboard/supermicro/h8qgi/cmos.layout | 5 ++++- src/mainboard/supermicro/h8scm/cmos.layout | 5 ++++- src/mainboard/tyan/s8226/cmos.layout | 5 ++++- src/superio/winbond/w83627dhg/superio.c | 19 +++++++++++++++++++ 9 files changed, 52 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asrock/939a785gmh/cmos.layout b/src/mainboard/asrock/939a785gmh/cmos.layout index 0d4f95e..cb91284 100644 --- a/src/mainboard/asrock/939a785gmh/cmos.layout +++ b/src/mainboard/asrock/939a785gmh/cmos.layout @@ -25,7 +25,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +400 2 e 7 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi @@ -59,6 +59,9 @@ enumerations 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep 8 0 DDR400 8 1 DDR333 8 2 DDR266 diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default index ab7aac1..3a53775 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.default +++ b/src/mainboard/asus/p5gc-mx/cmos.default @@ -4,4 +4,5 @@ debug_level=Spew hyper_threading=Enable nmi=Enable boot_devices='' -gfx_uma_size=8M \ No newline at end of file +gfx_uma_size=8M +power_on_after_fail=Disable \ No newline at end of file diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout index eaf51bb..feeb3b1 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.layout +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -32,7 +32,10 @@ entries # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused +#401 4 r 0 unused + +# coreboot config option: superio +405 2 e 7 power_on_after_fail # coreboot config options: southbridge 408 1 e 1 nmi @@ -83,6 +86,9 @@ enumerations 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep 11 0 1M 11 1 4M 11 2 8M diff --git a/src/mainboard/kontron/kt690/cmos.layout b/src/mainboard/kontron/kt690/cmos.layout index 93aa445..9c9088c 100644 --- a/src/mainboard/kontron/kt690/cmos.layout +++ b/src/mainboard/kontron/kt690/cmos.layout @@ -25,7 +25,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +400 2 e 7 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi @@ -59,6 +59,9 @@ enumerations 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep 8 0 DDR400 8 1 DDR333 8 2 DDR266 diff --git a/src/mainboard/lippert/toucan-af/cmos.layout b/src/mainboard/lippert/toucan-af/cmos.layout index ca3d9e5..219ee7c 100644 --- a/src/mainboard/lippert/toucan-af/cmos.layout +++ b/src/mainboard/lippert/toucan-af/cmos.layout @@ -24,7 +24,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +400 2 e 7 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi @@ -58,6 +58,9 @@ enumerations 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout index ca3d9e5..219ee7c 100644 --- a/src/mainboard/supermicro/h8qgi/cmos.layout +++ b/src/mainboard/supermicro/h8qgi/cmos.layout @@ -24,7 +24,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +400 2 e 7 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi @@ -58,6 +58,9 @@ enumerations 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz diff --git a/src/mainboard/supermicro/h8scm/cmos.layout b/src/mainboard/supermicro/h8scm/cmos.layout index ca3d9e5..219ee7c 100644 --- a/src/mainboard/supermicro/h8scm/cmos.layout +++ b/src/mainboard/supermicro/h8scm/cmos.layout @@ -24,7 +24,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +400 2 e 7 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi @@ -58,6 +58,9 @@ enumerations 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz diff --git a/src/mainboard/tyan/s8226/cmos.layout b/src/mainboard/tyan/s8226/cmos.layout index ca3d9e5..219ee7c 100644 --- a/src/mainboard/tyan/s8226/cmos.layout +++ b/src/mainboard/tyan/s8226/cmos.layout @@ -24,7 +24,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +400 2 e 7 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi @@ -58,6 +58,9 @@ enumerations 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 5a1502a..a1960c4 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -18,9 +18,25 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> +#include <pc80/mc146818rtc.h> #include <stdlib.h> #include "w83627dhg.h" +static void init_acpi(struct device *dev) +{ + u8 value; + int power_on = 0; + + get_option(&power_on, "power_on_after_fail"); + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + value = pnp_read_config(dev, 0xe4); + value &= ~(3 << 5); + value |= (power_on << 5); + pnp_write_config(dev, 0xe4, value); + pnp_exit_conf_mode(dev); +} + static void w83627dhg_enable_UR2(struct device *dev) { u8 reg8; @@ -45,6 +61,9 @@ static void w83627dhg_init(struct device *dev) case W83627DHG_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; + case W83627DHG_ACPI: + init_acpi(dev); + break; } }

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coreboot-gerrit December 2016