coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/google/reef: Update DPTF parameters EVT1_v0.3
by Tim Chen 28 Dec '16

28 Dec '16

Tim Chen (Tim-Chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17975 -gerrit commit e9eeb4df44c84a7927eef4e4bd987555b780d7d5 Author: Tim Chen <Tim-Chen(a)quantatw.com> Date: Wed Dec 28 14:44:52 2016 +0800 mainboard/google/reef: Update DPTF parameters EVT1_v0.3 Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT1_v0.3_20161227.xlsx) 1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU critical point:103 TSR1 passive point:45 TSR2 passive point:55, critical point:90 2. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 3secs Change Charger Effect on Temp Sensor 2 sample rate to 60secs Change CPU Effect on Temp Sensor 1 sample rate to 8secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c --- .../variants/baseboard/include/baseboard/acpi/dptf.asl | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index 116e675..87d3fa3 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -15,7 +15,7 @@ */ #define DPTF_CPU_PASSIVE 95 -#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_CRITICAL 103 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 80 #define DPTF_CPU_ACTIVE_AC2 70 @@ -29,13 +29,13 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 46 +#define DPTF_TSR1_PASSIVE 45 #define DPTF_TSR1_CRITICAL 75 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 100 -#define DPTF_TSR2_CRITICAL 125 +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 90 #define DPTF_ENABLE_CHARGER @@ -50,18 +50,18 @@ Name (CHPS, Package () { Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 800, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 30, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 0 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 }, #ifdef DPTF_ENABLE_CHARGER /* Charger Effect on Temp Sensor 2 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 1200, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 }, #endif /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 2 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },

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Patch merged into coreboot/master: buildgcc: Indicate CXXFLAGS for binutils
by gerrit＠coreboot.org 28 Dec '16

28 Dec '16

the following patch was just integrated into master: commit 010ecf800956f389bc34e09b968fe8934d4aa2ae Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Dec 22 16:19:37 2016 +0100 buildgcc: Indicate CXXFLAGS for binutils CXXFLAGS seems to be used a lot and have to be specified independently from CFLAGS. Change-Id: Iff4c76e54a46e908299b532fd848165a3dc04d43 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17937 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17937 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Fix string comparison operator
by gerrit＠coreboot.org 28 Dec '16

28 Dec '16

the following patch was just integrated into master: commit ae6187f01f29cb383a1d3bba0ce2614b17c18c5a Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Dec 22 22:16:39 2016 +0100 buildgcc: Fix string comparison operator Change-Id: I8ff8d51507dcf12cd554c8b4713074a99e47c11e Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/17942 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17942 for details. -gerrit

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Patch merged into coreboot/master: Microcode: Show a useful warning when microcode bins are missing
by gerrit＠coreboot.org 28 Dec '16

28 Dec '16

the following patch was just integrated into master: commit 85653748a4a503fc8fae82a12e5b7d162f50348c Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 22 10:29:20 2016 -0700 Microcode: Show a useful warning when microcode bins are missing Because the binary repo is disabled by default, we get frequent questions about why the build failed, relating to microcode in the binary repository. - Show an error saying that the file is missing instead of the typical make error of no rule to build the file. - Show a note encouraging users to try enabling the binary repo if it's not enabled. Change-Id: If4148c18cfb781ed2932bd2ae4a289b621afdebf Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/17940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17940 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Build GMP `--with-pic` if GCC defaults to `-pie`
by gerrit＠coreboot.org 27 Dec '16

27 Dec '16

the following patch was just integrated into master: commit 8bbd596de631adc8b677e69603e978b848eb1708 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Dec 22 16:05:54 2016 +0100 buildgcc: Build GMP `--with-pic` if GCC defaults to `-pie` GCC 6 can optionally default to building all binaries as position independent executables (PIE). This breaks linking against static libraries that are compiled without position independent code (PIC). Building GMP `--with-pic` in this case seems to be the least fragile solution. TEST=Run `make all` and `make BUILDGCC_OPTIONS=-b build-i386` in util/crossgcc on Debian Stretch. Change-Id: I5f3185af9c8d599379a628e18724b217b88be974 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17936 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> See https://review.coreboot.org/17936 for details. -gerrit

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Patch set updated for coreboot: google/auron: Fix omitted ACPI KB backlight for variants
by Matt DeVillier 27 Dec '16

27 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17960 -gerrit commit c2e3c3a991aafb8fbb11aec1a83b0d2ee0a16cc8 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri Dec 23 14:56:12 2016 -0600 google/auron: Fix omitted ACPI KB backlight for variants Restores KB backlight functionality for auron variants gandof, lulu, and samus. TEST: boot Lulu and observe KB backlight functional Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/auron/acpi/ec.asl | 3 +++ .../variants/auron_paine/include/variant/acpi/ec.asl | 0 .../auron/variants/auron_yuna/include/variant/acpi/ec.asl | 0 .../auron/variants/gandof/include/variant/acpi/ec.asl | 15 +++++++++++++++ .../auron/variants/lulu/include/variant/acpi/ec.asl | 15 +++++++++++++++ .../auron/variants/samus/include/variant/acpi/ec.asl | 15 +++++++++++++++ 6 files changed, 48 insertions(+) diff --git a/src/mainboard/google/auron/acpi/ec.asl b/src/mainboard/google/auron/acpi/ec.asl index c6cf506..e25cd29 100644 --- a/src/mainboard/google/auron/acpi/ec.asl +++ b/src/mainboard/google/auron/acpi/ec.asl @@ -16,5 +16,8 @@ /* mainboard configuration */ #include "ec.h" +/* variant configuration */ +#include <variant/acpi/ec.asl> + /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl new file mode 100644 index 0000000..12b59b4 --- /dev/null +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl new file mode 100644 index 0000000..12b59b4 --- /dev/null +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl new file mode 100644 index 0000000..12b59b4 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT

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Patch merged into coreboot/master: device/dram/ddr3: add FTB timings
by gerrit＠coreboot.org 27 Dec '16

27 Dec '16

the following patch was just integrated into master: commit 76f8dbc4f70469e0b5913796d6130e85df1cdd77 Author: Nicola Corna <nicola(a)corna.info> Date: Wed Nov 16 08:57:15 2016 +0100 device/dram/ddr3: add FTB timings SPD revision 1.1 introduced FTB timings, an extra set of SPD values that specify a more precise tCKmin, tAAmin, tRCDmin, tRPmin and tRCmin. For backwards compatibility, the MTB is usually rounded up and the FTB part is negative. For this reason some memories were not set up optimally, as the FTB part was ignored and the resulting timing wasn't set to the minimum value. The tests were performed on a Lenovo X220 with two Micron 8KTF51264HZ-1G9E (1866 MHz): reading only the MTB part, coreboot reports a tCKmin of 1.125 ns, corresponding to a working frequency of 800 MHz; with the additional tCKmin FTB part (-0.054 ns) the new (rounded) value is 1.070 ns, valid for a 933 MHz operation. Tested also with Ballistix DDR3-1866 SODIMM on Lenovo T420: the memory is now detected as DDR3-1866 instead of DDR3-1600. Some manufacturers (like Micron) seems to expect a small rounding on the timings, so a nearest-value rounding is performed. If this assumption isn't correct, an error up to ~2 ps can be committed, which is low enough to be safely ignored. Change-Id: Ib98f2e70820f207429d04ca6421680109a81f457 Signed-off-by: Nicola Corna <nicola(a)corna.info> Reviewed-on: https://review.coreboot.org/17476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17476 for details. -gerrit

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Patch merged into coreboot/master: console: Enable do_printk_va_list for VBOOT
by gerrit＠coreboot.org 27 Dec '16

27 Dec '16

the following patch was just integrated into master: commit aa5c8f78f98614130cfb4802faa30b6a6b92e815 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Dec 26 10:58:16 2016 -0800 console: Enable do_printk_va_list for VBOOT Use CONFIG_VBOOT to enable do_printk_va_list to match the conditionals in include/console/console.h and the only caller is vboot/vboot_logic.c. CONFIG_VBOOT is also selected for CONFIG_CHROMEOS. TEST=Build and run on Galileo Gen2 Change-Id: Ia115c74afa498a14d5edd6f7940ec2edc124516f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/17967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17967 for details. -gerrit

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New patch to review for coreboot: [WIP] nb/i945/gma : Implement VESA mode on VGA output
by Arthur Heymans 27 Dec '16

27 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17974 -gerrit commit fffebd81d27911355e74306d256a2dfa45e61a68 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Dec 27 18:04:34 2016 +0100 [WIP] nb/i945/gma : Implement VESA mode on VGA output This implements VESA mode on the VGA output to have native resolution in the payload. Currently this breaks textmode. Change-Id: Ic1d365995b16a9033042ceb608592e970c263533 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 329 +++++++++++++++++++++++++-------------- 1 file changed, 211 insertions(+), 118 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..e1abaaf 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -393,15 +393,82 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, void *pmmio, unsigned int pgfx) { - int i; - u32 hactive, vactive; - u16 reg16; + struct edid edid; + struct edid_mode *mode; + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; + u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1, pixel_p2, pixel_n, pixel_m1, pixel_m2; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; u32 uma_size; + u16 reg16; + + printk(BIOS_SPEW, + "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", + (void *)pgfx, pmmio, piobase, pphysbase); + + if (gtt_setup(pmmio)) { + printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + return 0; + } + + /* Setup GTT. */ + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + uma_size = 0; + if (!(reg16 & 2)) { + uma_size = decode_igd_memory_size((reg16 >> 4) & 7); + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); + } + + for (i = 0; i < (uma_size - 256) / 4; i++) { + outl((i << 2) | 1, piobase); + outl(pphysbase + (i << 12) + 1, piobase + 4); + } + + temp = read32(pmmio + PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + + if (temp & 1) + printk(BIOS_INFO, "GTT Enabled\n"); + else + printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + + + intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, edid_data, + sizeof(edid_data)); + decode_edid(edid_data, sizeof(edid_data), &edid); + mode = &edid.mode; + + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + vblank = mode->vbl; + hblank = mode->hbl; + vsync = mode->vspw; + hsync = mode->hspw; + hfront_porch = mode->hso; + vfront_porch = mode->vso; - printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", - (u32)pmmio, piobase, pphysbase); + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + /* R = j, G = j, B = j. */ + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); - gtt_setup(pmmio); + write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + /* Clean registers. */ + for (i = 0; i < 0x20; i += 4) + write32(pmmio + RENDER_RING_BASE + i, 0); + for (i = 0; i < 0x20; i += 4) + write32(pmmio + FENCE_REG_965_0 + i, 0); + write32(pmmio + PP_ON_DELAYS, 0); + write32(pmmio + PP_OFF_DELAYS, 0); /* Disable VGA. */ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); @@ -410,153 +477,179 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, write32(pmmio + PIPECONF(0), 0); write32(pmmio + PIPECONF(1), 0); - write32(pmmio + INSTPM, 0x800); - - vga_gr_write(0x18, 0); - - write32(pmmio + VGA0, 0x200074); - write32(pmmio + VGA1, 0x200074); + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); - write32(pmmio + DSPCLK_GATE_D, 0); - write32(pmmio + FW_BLC, 0x03060106); - write32(pmmio + FW_BLC2, 0x00000306); + target_frequency = mode->pixel_clock; + pixel_p2 = target_frequency <= 225000 ? 10 : 5; - write32(pmmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + /* Find suitable divisors, m1, m2, p1, n. */ + /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ + /* should be closest to target frequency as possible */ + u32 candn, candm1, candm2, candp1; + for (candm1 = 8; candm1 <= 18; candm1++) { + for (candm2 = 3; candm2 <= 7; candm2++) { + for (candn = 1; candn <= 6; candn++) { + for (candp1 = 1; candp1 <= 8; candp1++) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * pixel_p2; + u32 vco = DIV_ROUND_CLOSEST( + BASE_FREQUENCY * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = MAX(dot, target_frequency) + - MIN(dot, target_frequency); + if ((m < 70) || (m > 120)) + continue; + if (this_err < smallest_err) { + smallest_err = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } + } + } + } - write32(pmmio + 0x7041c, 0x0); + if (smallest_err == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } - write32(pmmio + DPLL_MD(0), 0x3); - write32(pmmio + DPLL_MD(1), 0x3); - write32(pmmio + DSPCNTR(1), 0x1000000); - write32(pmmio + PIPESRC(1), 0x027f01df); + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); - vga_misc_write(0x67); - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); + write32(pmmio + PF_WIN_POS(0), 0); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + /* Disable panel fitter (we're in native resolution). */ + write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) + | (vactive - 1)); + write32(pmmio + PF_CTL(1), 0); + write32(pmmio + PF_WIN_SZ(1), 0); + write32(pmmio + PFIT_PGM_RATIOS, 0); + write32(pmmio + PFIT_CONTROL, 0); + } else { + write32(pmmio + PIPESRC(1), (639 << 16) | 399); + write32(pmmio + PF_CTL(1), PF_ENABLE | PF_FILTER_MED_3x3); + write32(pmmio + PF_WIN_SZ(1), vactive | (hactive << 16)); + write32(pmmio + PFIT_CONTROL, PFIT_ENABLE + | (0 << PFIT_PIPE_SHIFT)); + } - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); + mdelay(1); - // Disable screen memory to prevent garbage from appearing. - vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_A | DISPPLANE_GAMMA_ENABLE); mdelay(1); - write32(pmmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_VGA_MODE_DIS - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(0), (pixel_n << 16) | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); mdelay(1); - write32(pmmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_VGA_MODE_DIS - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); - - write32(pmmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); - - write32(pmmio + HTOTAL(0), - ((hactive - 1) << 16) - | (hactive - 1)); - write32(pmmio + HBLANK(0), - ((hactive - 1) << 16) + write32(pmmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); + write32(pmmio + HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); + write32(pmmio + HBLANK(0), ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(pmmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(pmmio + VBLANK(0), ((vactive - 1) << 16) + write32(pmmio + VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(pmmio + VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(pmmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); - - write32(pmmio + PF_WIN_POS(0), 0); - - write32(pmmio + PIPESRC(0), (639 << 16) | 399); - write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(pmmio + PFIT_CONTROL, 0x0); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x00002040); - mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x80002050); - write32(pmmio + FDI_TX_CTL(0), 0x00044000); - mdelay(1); - write32(pmmio + FDI_TX_CTL(0), 0x80044000); - write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio + DSPPOS(0), 0); + + /* Backlight init just in case a LVDS display is connected too */ + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC, 0x011d011a); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC_SELF, 0x0001003f); + write32(pmmio + FW_BLC, 0x011d0109); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); - write32(pmmio + VGACNTRL, 0x0); - write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_A | DISPPLANE_GAMMA_ENABLE); mdelay(1); + write32(pmmio + PIPECONF(0), PIPECONF_ENABLE); write32(pmmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT - | ADPA_USE_VGA_HVPOLARITY + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); - - write32(pmmio + DSPFW3, 0x7f3f00c1); - write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); - write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); - write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); - /* Set up GTT. */ - - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); - uma_size = 0; - if (!(reg16 & 2)) { - uma_size = decode_igd_memory_size((reg16 >> 4) & 7); - printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - } + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); - for (i = 0; i < (uma_size - 256) / 4; i++) - { - outl((i << 2) | 1, piobase); - outl(pphysbase + (i << 12) + 1, piobase + 4); - } + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); /* Clear interrupts. */ write32(pmmio + DEIIR, 0xffffffff); write32(pmmio + SDEIIR, 0xffffffff); - write32(pmmio + IIR, 0xffffffff); - write32(pmmio + IMR, 0xffffffff); - write32(pmmio + EIR, 0xffffffff); - vga_textmode_init(); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", + (void *)pgfx, hactive * vactive * 4); + memset((void *)pgfx, 0x00, hactive * vactive * 4); + set_vbe_mode_info_valid(&edid, pgfx); + } else { + vga_misc_write(0x67); + write32(pmmio + DSPCNTR(0), 0); + write32(pmmio + VGACNTRL, 0xc4008e); + vga_textmode_init(); + } return 0; - } /* compare the header of the vga edid header */

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New patch to review for coreboot: Kconfig: Document what ASPM means
by Jonathan Neuschäfer 27 Dec '16

27 Dec '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17973 -gerrit commit 52ad404b96a1a5b13929e6d09411eb926384cbbd Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Dec 27 16:31:28 2016 +0100 Kconfig: Document what ASPM means Change-Id: I57dd933ad70ffac95388d832bd5047f2225688e3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/device/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index c90da89..d1f5694 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -264,7 +264,7 @@ config PCIEXP_ASPM bool default n help - Detect and enable ASPM on PCIe links. + Detect and enable ASPM (Active State Power Management) on PCIe links. config PCIEXP_CLK_PM prompt "Enable PCIe Clock Power Management"

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coreboot-gerrit December 2016