coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ec/ene932: correct ACPI battery data fed into ToString()
by Matt DeVillier 15 Dec '16

15 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17783 -gerrit commit 05897ee994292b503eda1ab8aeeae89bbf50ba6e Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri Dec 9 18:14:57 2016 -0600 ec/ene932: correct ACPI battery data fed into ToString() ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString() where needed Change-Id: Ic86048d1d6354b9b0dac3c8957df318d0825c905 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/ec/compal/ene932/acpi/battery.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl index 12092c7..f86cb01 100644 --- a/src/ec/compal/ene932/acpi/battery.asl +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -84,9 +84,9 @@ Device (BATX) Multiply(Local1, 0x03, Local1) Store (Local1, Index (PBIF, 6)) - Store (ToString(BATD), Index (PBIF, 9)) // model + Store (ToString(Concatenate(BATD, 0x00)), Index (PBIF, 9)) // model Store (ToHexString(BSN0), Index (PBIF, 10)) // serial - Store (ToString(BMFN), Index (PBIF, 12)) // venor + Store (ToString(BMFN), Index (PBIF, 12)) // vendor Store(BDN0, BTNM) // Save the battery number

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New patch to review for coreboot: skylake: Add target offset for throttling action
by Sumeet R Pawnikar 15 Dec '16

15 Dec '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17889 -gerrit commit bcd3adf980285f9e3a3ff0af73d631691cf8f7bc Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Thu Dec 15 19:29:51 2016 +0530 skylake: Add target offset for throttling action This patch adds the target offset to 10 degree C to adjust the thermal throttling action at prochot activation temperature from the default temperature target. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the target offset value before and after S3. Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/skylake/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3ec8d2c..0458a93 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -206,6 +206,8 @@ static void configure_thermal_target(void) wrmsr(MSR_TEMPERATURE_TARGET, msr); } msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= 0xa << 24; /* set target offset as 10 degree C */ msr.lo &= ~0x7f; /* Bits 6:0 */ msr.lo |= 0xe6; /* setting 100ms thermal time window */ wrmsr(MSR_TEMPERATURE_TARGET, msr);

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New patch to review for coreboot: samsung/exynos5420: Fix test for src < 0
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17888 -gerrit commit f544dbe12f698556473a31ac85aaff2e8ec86ccd Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:51:13 2016 +0100 samsung/exynos5420: Fix test for src < 0 It was unsigned, not a good place to be for testing < 0. Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1241911 --- src/soc/samsung/exynos5420/clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 49ac07b..3c4bb04 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -161,7 +161,8 @@ static int clock_select_to_pll(enum peripheral_clock_select sel) unsigned long clock_get_periph_rate(enum periph_id peripheral) { unsigned long sclk; - unsigned int src, div; + unsigned int div; + int src; switch (peripheral) { case PERIPH_ID_UART0:

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New patch to review for coreboot: util/romcc: Don't read 'member' if it might be NULL
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17887 -gerrit commit 0a30d03b8337fdd67e9b65d7a1d5923edb81d3ec Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:24:06 2016 +0100 util/romcc: Don't read 'member' if it might be NULL The earlier loop exits gracefully iff i == index. In other cases, member might be NULL, so check that the scan was successful before using its results. Change-Id: I818c233d797d82fa819243c4626dd9c4b7de3ac6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1129147 --- util/romcc/romcc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 052be12..cc1a3ac 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -6406,11 +6406,10 @@ static size_t index_reg_offset(struct compile_state *state, i++; member = member->right; } - size += reg_needed_padding(state, member, size); if (i != index) { internal_error(state, 0, "Missing member index: %u", index); } - + size += reg_needed_padding(state, member, size); } else if ((type->type & TYPE_MASK) == TYPE_JOIN) { ulong_t i;

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New patch to review for coreboot: util/romcc: Don't reference a variable after checking it for NULL
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17886 -gerrit commit 8b21ab6c00c0815ca11af05fccab83fe6623b06e Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:21:56 2016 +0100 util/romcc: Don't reference a variable after checking it for NULL Change-Id: Ic8e850bdf75d38fc061fb3a8c55d38bcf09c305a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1129146 --- util/romcc/romcc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 7b5e5d7..052be12 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -21322,15 +21322,15 @@ static void verify_blocks(struct compile_state *state) "computed users %d != stored users %d", users, block->users); } + if (!(block->last->next)) { + internal_error(state, block->first, + "bad next block"); + } if (!triple_stores_block(state, block->last->next)) { internal_error(state, block->last->next, "cannot find next block"); } block = block->last->next->u.block; - if (!block) { - internal_error(state, block->last->next, - "bad next block"); - } } while(block != state->bb.first_block); if (blocks != state->bb.last_vertex) { internal_error(state, 0, "computed blocks: %d != stored blocks %d",

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New patch to review for coreboot: util/romcc: remove self-assignment
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17885 -gerrit commit 5cf7dfb6d534d542229d78d9bfb5601bfaac9c77 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:17:45 2016 +0100 util/romcc: remove self-assignment Change-Id: I0f78b55b28011cdefc90665bca2a7ea17647e955 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1129127 --- util/romcc/romcc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 655e6f5..7b5e5d7 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -20919,7 +20919,6 @@ static void scc_visit_phi(struct compile_state *state, struct scc_state *scc, } /* meet(X, lattice high) = X */ else if (is_lattice_hi(state, tmp)) { - lnode->val = lnode->val; } /* meet(lattice high, X) = X */ else if (is_lattice_hi(state, lnode)) {

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New patch to review for coreboot: util/romcc: Move access after NULL-check
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17884 -gerrit commit 9775992654b87e229b6b2bd10b2035eff6981fd3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:14:59 2016 +0100 util/romcc: Move access after NULL-check Change-Id: I7f9c38fd6e75b32fe1ed8a60c7054f4dd1fcd5c0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1129104 --- util/romcc/romcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 9a90167..655e6f5 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -6287,10 +6287,10 @@ static size_t field_reg_offset(struct compile_state *state, internal_error(state, 0, "field_reg_offset only works on structures and unions"); } - size += reg_needed_padding(state, member, size); if (!member || (member->field_ident != field)) { error(state, 0, "member %s not present", field->name); } + size += reg_needed_padding(state, member, size); return size; }

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New patch to review for coreboot: util/romcc: Fix resource leak
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17883 -gerrit commit 25cad2ec8453a78b65d5335e9658e50e5e02a9c3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:12:16 2016 +0100 util/romcc: Fix resource leak Change-Id: I0d260254bab714ec939fc199b3a133b0fc05b10d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1129112 --- util/romcc/romcc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index c97312c..9a90167 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -10779,6 +10779,7 @@ static struct triple *string_constant(struct compile_state *state) ptr = buf; buf = xmalloc(type->elements + str_len + 1, "string_constant"); memcpy(buf, ptr, type->elements); + free(ptr); ptr = buf + type->elements; do { *ptr++ = char_value(state, &str, end);

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New patch to review for coreboot: util/broadcom: Add two more NULL checks
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17882 -gerrit commit 0c26c4f96d28e082e4f721649f329039a60e444f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:03:55 2016 +0100 util/broadcom: Add two more NULL checks Change-Id: I088730fd87dd39fa2c36a06c5770fad05a5808b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1323511, #1323512 --- util/broadcom/secimage/sbi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/util/broadcom/secimage/sbi.c b/util/broadcom/secimage/sbi.c index d972ba4..f56f896 100644 --- a/util/broadcom/secimage/sbi.c +++ b/util/broadcom/secimage/sbi.c @@ -109,6 +109,11 @@ int CreateSecureBootImage(int ac, char **av) --ac, ++av; } + if (!bl) { + puts("-bl not set"); + return -1; + } + if (stat(bl, &file_stat) == -1) { puts("Can't stat bl"); return -1; @@ -136,6 +141,11 @@ int CreateSecureBootImage(int ac, char **av) if (configfile) FillHeaderFromConfigFile(buf, configfile); + if (!privkey) { + status = -1; + goto done; + } + status = AddImagePayload(buf, bl, filesize); if (status) { status = -1;

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New patch to review for coreboot: util/broadcom: Check return value of stat()
by Patrick Georgi 15 Dec '16

15 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17881 -gerrit commit 5c70592bdc4b1f41db4712df0f4cd4354156d58d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Dec 15 15:02:09 2016 +0100 util/broadcom: Check return value of stat() Change-Id: Ib53408e8b186c07aa8e42c67131d39c4add05983 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1323515 --- util/broadcom/secimage/sbi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/broadcom/secimage/sbi.c b/util/broadcom/secimage/sbi.c index 8718f14..d972ba4 100644 --- a/util/broadcom/secimage/sbi.c +++ b/util/broadcom/secimage/sbi.c @@ -109,7 +109,10 @@ int CreateSecureBootImage(int ac, char **av) --ac, ++av; } - stat(bl, &file_stat); + if (stat(bl, &file_stat) == -1) { + puts("Can't stat bl"); + return -1; + } filesize = file_stat.st_size + MIN_SIZE; buf = calloc(sizeof(uint8_t), filesize);

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coreboot-gerrit December 2016