coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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1140 discussions

Patch set updated for coreboot: amd/gardenia: Add AHB bridge registers in ACPI
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17848 -gerrit commit 938cf6b0be4f4ef662cd53948e402931687007c4 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Oct 19 19:28:15 2016 -0400 amd/gardenia: Add AHB bridge registers in ACPI Add the region used by the A-Link to AHB configuration registers. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705 and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b) Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/amd/gardenia/acpi/carrizo_fch.asl | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl index 2b9df3b..954ab43 100644 --- a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl +++ b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl @@ -13,6 +13,20 @@ * GNU General Public License for more details. */ +Device(AAHB) { + Name(_HID,"AAHB0000") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() + { + IRQ(Edge, ActiveHigh, Exclusive) {7} + Memory32Fixed(ReadWrite, 0xFEDC0000, 0x2000) + }) + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + Device(GPIO) { Name (_HID, "AMD0030") Name (_CID, "AMD0030")

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Patch set updated for coreboot: amd/gardenia: Add I2C devices to ACPI
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17847 -gerrit commit f0656a6ccdcff6b1a4203bc89b2ff9b5cceed19b Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Oct 19 18:32:27 2016 -0400 amd/gardenia: Add I2C devices to ACPI Add the missing two I2C controllers. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d) Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/amd/gardenia/acpi/carrizo_fch.asl | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl index a177306..2b9df3b 100644 --- a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl +++ b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl @@ -77,3 +77,29 @@ Device(I2CB) Return (0x0F) } } + +Device(I2CC) { + Name(_HID,"AMD0010") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {6} + Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000) + }) + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(I2CD) +{ + Name(_HID,"AMD0010") + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {14} + Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +}

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Patch set updated for coreboot: amd/gardenia: Clean up GPIO ASL
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17846 -gerrit commit d18b87181e78b29dea3c9b5b70b49016848248e8 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 20 12:43:15 2016 -0400 amd/gardenia: Clean up GPIO ASL Remove the unused Name field. Its previous design generates an FWTS error and a recommendation for changing it to Serialized. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0) Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/amd/gardenia/acpi/carrizo_fch.asl | 30 +++++-------------------- 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl index 79f5420..a177306 100644 --- a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl +++ b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,31 +18,13 @@ Device(GPIO) { Name (_CID, "AMD0030") Name(_UID, 0) - Method (_CRS, 0x0, NotSerialized) { - Name (RBUF, ResourceTemplate () { - // - // Interrupt resource. In this example, banks 0 & 1 share the same - // interrupt to the parent controller and similarly banks 2 & 3. - // - // N.B. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform - // - Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} - - // - // Memory resource. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform. - // - Memory32Fixed(ReadWrite, 0xFED81500, 0x300) - }) - - Return (RBUF) - } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Memory32Fixed(ReadWrite, 0xFED81500, 0x300) + }) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (0x0F) } }

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Patch set updated for coreboot: amd/gardenia: Enable LPC decodes
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17227 -gerrit commit 8eab962fb5dafb03436d26efcdc3c4659a163085 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Oct 11 14:19:07 2016 -0400 amd/gardenia: Enable LPC decodes Turn on LPC decoding in romstage. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc) Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index c3e2aa4..eca9d3b 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,8 +33,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif amd_initmmio(); - hudson_lpc_port80(); + hudson_lpc_decode(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);

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Patch set updated for coreboot: amd/gardenia: Enable HD Audio
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17226 -gerrit commit a4d167265023a3985964a019ce364d3767bccda0 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Oct 25 18:10:18 2016 -0400 amd/gardenia: Enable HD Audio Add ALC286 commands and update the PLATFORM_CONFIGURATION structure with the list address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee) Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/OemCustomize.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 64091ff..1619c95 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -97,6 +97,34 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; +static const UINT32 AzaliaCodecAlc286Table[] = +{ + 0x00172051, 0x001721C7, 0x00172222, 0x00172310, + 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00, + 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7, + 0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40, + 0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90, + 0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41, + 0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04, + 0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41, + 0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41, + 0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40, + 0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04, + 0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04, + 0x02050071, 0x02040014, 0x02050010, 0x02040C22, + 0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50, + 0x0205002D, 0x02041020, 0x02050020, 0x02040000, + 0x02050019, 0x02040817, 0x02050035, 0x02041AA5, + 0x02050063, 0x02042906, 0x02050063, 0x02042906, + 0xffffffff +}; + +CONST CODEC_VERB_TABLE_LIST CodecTableList[] = +{ + { (UINT32) 0x10ec0286, AzaliaCodecAlc286Table}, + { (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF} +}; + /*---------------------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly @@ -118,4 +146,5 @@ VOID OemCustomizeInitEarly ( ) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList; }

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Patch set updated for coreboot: amd/gardenia: Update PCIe and DDI lanes
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17225 -gerrit commit 05b9513ad9dde9d2f35f77cea94a36019a7803b7 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 13 11:42:09 2016 -0400 amd/gardenia: Update PCIe and DDI lanes Change the Carrizo settings used for Bettong to ones specific to Stoney on Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb) Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/OemCustomize.c | 75 +++++++++++++------------------ 1 file changed, 31 insertions(+), 44 deletions(-) diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 3300244..64091ff 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,90 +16,77 @@ #include <northbridge/amd/pi/agesawrapper.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE - static const PCIe_PORT_DESCRIPTOR PortList [] = { - /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 3, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x03, 0) + AspmL0sL1, 0x04, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x04, 0) + AspmL0sL1, 0x17, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x05, 0) + AspmL0sL1, 0x17, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x06, 0) + AspmL0sL1, 0x13, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */ { - DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x07, 0) + AspmL0sL1, 0x16, 0) }, - + /* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */ }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - /* DP0 */ + /* DDI0 - eDP */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) }, - /* DP1 */ + /* DDI1 - DP */ { - 0, //DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, - /* DP2 */ + /* DDI2 - HDMI */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) }, };

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Patch set updated for coreboot: amd/gardenia: Enable SATA controller
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17224 -gerrit commit 6190b7d33461e4a926e1ff2b40bef5e236f4543f Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 20 14:01:32 2016 -0400 amd/gardenia: Enable SATA controller Duplicate the code from DB-FT3lc and use the correct names. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c) Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/BiosCallOuts.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 32b1fec..4b7fc79 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -76,6 +76,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); + FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -92,6 +94,22 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) #endif FchParams_env->Usb.Xhci1Enable = FALSE; FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ + + /* SATA configuration */ + FchParams_env->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams_env->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + break; + } } printk(BIOS_DEBUG, "Done\n");

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Patch set updated for coreboot: amd/gardenia: Update xHCI configuration
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17223 -gerrit commit d42e5ed088b35d9b6f8359621c20a40fa00e2f13 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 13 11:41:50 2016 -0400 amd/gardenia: Update xHCI configuration Remove a duplicated check and setting for xHCI during the AMD_INIT_RESET callout. This is handled by the wrapper. Also remove nearby commented code. EcChannel0 is not a member of FCH_RESET_DATA_BLOCK. Leave the check in AMD_INIT_ENV. Although AGESA honors what was previously requested, additional settings depend on the state of Usb.Xhci0Enable. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd) Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/BiosCallOuts.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index df9139f..32b1fec 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -76,9 +76,6 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;

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Patch set updated for coreboot: amd/gardenia: Configure GPIO signals
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17222 -gerrit commit 32e3c03f30688e18f1a9a3be320242f14716605a Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Oct 11 10:54:33 2016 -0400 amd/gardenia: Configure GPIO signals Change the default configuration for the following settings: AGPIO14: BT radio disable AGPIO64: NFC PU AGPIO65: NFC wake AGPIO66: Webcam AGPIO69: PCIe presence detect AGPIO70: GPS sleep AGPIO116: MUX for Power Express Eval EGPIO119: SD power Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4) Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/BiosCallOuts.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index f7c16b9..df9139f 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -53,8 +53,14 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); static const GPIO_CONTROL oem_gardenia_gpio[] = { - {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, - {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, + {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE}, + {64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE}, + {65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE}, + {66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE}, + {69, Function0, FCH_GPIO_PULL_UP_ENABLE}, + {70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE}, + {116, Function1, FCH_GPIO_PULL_DOWN_ENABLE}, + {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE}, {-1} }; /**

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Patch set updated for coreboot: amd/gardenia: Remove board ID capability
by Marshall Dawson 14 Dec '16

14 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17221 -gerrit commit af1809aa421471938faaf2bd062cb5e3de24a179 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 10:14:14 2016 -0600 amd/gardenia: Remove board ID capability Remove the last bit of Bettong board_id checking from Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c) Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/Makefile.inc | 2 -- src/mainboard/amd/gardenia/boardid.c | 48 --------------------------------- 2 files changed, 50 deletions(-) diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index 99159e8..0994a70 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -15,11 +15,9 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c -romstage-y += boardid.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ifeq ($(CONFIG_HUDSON_IMC_FWM), y) ramstage-y += fchec.c endif -ramstage-y += boardid.c diff --git a/src/mainboard/amd/gardenia/boardid.c b/src/mainboard/amd/gardenia/boardid.c deleted file mode 100644 index e2e8162..0000000 --- a/src/mainboard/amd/gardenia/boardid.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <boardid.h> - -/** - *Gardenia uses 3 GPIO(5-7) pins to identify board. - *The GPIO ports are mapped to MMIO space. - *The GPIO value and board version are mapped as follow: - *GPIO5 GPIO6 GPIO7 Version - * 0 0 0 A - * 0 0 1 B - * ...... - * 1 1 1 H - */ -uint8_t board_id(void) -{ - void *gpiommioaddr; - u8 value = 0; - u8 boardrev = 0; - char boardid; - - gpiommioaddr = (void *)0xfed80000ul + 0x1500; - value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */ - boardrev = value & 1; - value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */ - boardrev |= (value & 1) << 1; - value = read8(gpiommioaddr + (5 << 2) + 2); /* agpio5: board_id0 */ - boardrev |= (value & 1) << 2; - - boardid = 'A' + boardrev; - - return boardid; -}

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coreboot-gerrit December 2016