coreboot-gerrit October 2016

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Patch set updated for coreboot: skylake: Use COMMON_FADT
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17138 -gerrit commit 315dbb16a8182c3aba495761ea8f1a0b29cc45cd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 17 19:47:51 2016 -0700 skylake: Use COMMON_FADT Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Set the ACPI revision to 5. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/fadt.c | 47 ------------------------------------ src/mainboard/google/glados/fadt.c | 47 ------------------------------------ src/mainboard/google/lars/fadt.c | 47 ------------------------------------ src/mainboard/intel/kblrvp/fadt.c | 47 ------------------------------------ src/mainboard/intel/kunimitsu/fadt.c | 47 ------------------------------------ src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/acpi.c | 5 +++- 7 files changed, 5 insertions(+), 236 deletions(-) diff --git a/src/mainboard/google/chell/fadt.c b/src/mainboard/google/chell/fadt.c deleted file mode 100644 index 92987f9..0000000 --- a/src/mainboard/google/chell/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/glados/fadt.c b/src/mainboard/google/glados/fadt.c deleted file mode 100644 index 92987f9..0000000 --- a/src/mainboard/google/glados/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/lars/fadt.c b/src/mainboard/google/lars/fadt.c deleted file mode 100644 index 05fea01..0000000 --- a/src/mainboard/google/lars/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/intel/kblrvp/fadt.c b/src/mainboard/intel/kblrvp/fadt.c deleted file mode 100644 index 49301e3..0000000 --- a/src/mainboard/intel/kblrvp/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/intel/kunimitsu/fadt.c b/src/mainboard/intel/kunimitsu/fadt.c deleted file mode 100644 index 05fea01..0000000 --- a/src/mainboard/intel/kunimitsu/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a5fb0e8..7591d66 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS + select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB select HAVE_HARD_RESET diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index ca7bafa..fc4f58c 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -223,12 +223,15 @@ unsigned long acpi_fill_madt(unsigned long current) return acpi_madt_irq_overrides(current); } -void acpi_fill_in_fadt(acpi_fadt_t *fadt) +void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); config_t *config = dev->chip_info; + /* Use ACPI 5.0 revision */ + fadt->header.revision = ACPI_FADT_REV_ACPI_5_0; + fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

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Patch set updated for coreboot: skylake: Add support for eSPI SMI events
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17134 -gerrit commit 9a3ca308b78a8fd3817b509671150c572fdbf05f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 19:58:27 2016 -0700 skylake: Add support for eSPI SMI events Add the necessary infrastructure to support eSPI SMI events, and a mainboard handler to pass control to the EC. BUG=chrome-os-partner:58666 TEST=tested on eve board with eSPI enabled, verified that lid close event from the EC during firmware will result in an SMI and shut down the system. Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/include/soc/pm.h | 1 + src/soc/intel/skylake/include/soc/smm.h | 2 ++ src/soc/intel/skylake/pmutil.c | 3 ++- src/soc/intel/skylake/smi.c | 3 ++- src/soc/intel/skylake/smihandler.c | 7 +++++++ 5 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 235ad89..91f037a 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -46,6 +46,7 @@ #define SMI_EN 0x30 #define XHCI_SMI_EN (1 << 31) #define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) #define GPIO_UNLOCK_SMI_EN (1 << 27) #define INTEL_USB2_EN (1 << 18) #define LEGACY_USB2_EN (1 << 17) diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 1beaaa4..71083b3 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -50,6 +50,8 @@ struct smm_relocation_params { /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); +/* Mainboard handler for eSPI SMIs */ +void mainboard_smi_espi_handler(void); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 31de242..e450ce8 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -173,7 +173,8 @@ static u32 print_smi_status(u32 smi_sts) [20] = "PCI_EXP_SMI", [21] = "MONITOR", [26] = "SPI", - [27] = "GPIO_UNLOCK" + [27] = "GPIO_UNLOCK", + [28] = "ESPI_SMI", }; if (!smi_sts) diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c index 77f3951..442607f 100644 --- a/src/soc/intel/skylake/smi.c +++ b/src/soc/intel/skylake/smi.c @@ -62,11 +62,12 @@ void southbridge_smm_enable_smi(void) * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) * No SMIs: * - on microcontroller writes (io 0x62/0x66) * - on TCO events */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS); } void southbridge_trigger_smi(void) diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 1834815..872cce1 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -361,6 +361,12 @@ static void southbridge_smi_gpi(void) gpi_clear_get_smi_status(&smi_sts); } +void __attribute__((weak)) mainboard_smi_espi_handler(void) { } +static void southbridge_smi_espi(void) +{ + mainboard_smi_espi_handler(); +} + static void southbridge_smi_mc(void) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -482,6 +488,7 @@ static smi_handler_t southbridge_smi[SMI_STS_BITS] = { [PM1_STS_BIT] = southbridge_smi_pm1, [GPE0_STS_BIT] = southbridge_smi_gpe0, [GPIO_STS_BIT] = southbridge_smi_gpi, + [ESPI_SMI_STS_BIT] = southbridge_smi_espi, [MCSMI_STS_BIT] = southbridge_smi_mc, [TCO_STS_BIT] = southbridge_smi_tco, [PERIODIC_STS_BIT] = southbridge_smi_periodic,

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Patch set updated for coreboot: skylake: Setup GPE in bootblock
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17135 -gerrit commit dc2347d4d96ecfb2acaffc5fd49ad422014a3231 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:03:56 2016 -0700 skylake: Setup GPE in bootblock Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/bootblock/pch.c | 3 ++ src/soc/intel/skylake/include/soc/pci_devs.h | 2 +- src/soc/intel/skylake/include/soc/pm.h | 3 ++ src/soc/intel/skylake/pmc.c | 39 +--------------------- src/soc/intel/skylake/pmutil.c | 48 ++++++++++++++++++++++++++++ 5 files changed, 56 insertions(+), 39 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 57b5fed..371dd63 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -301,6 +301,9 @@ void pch_early_init(void) /* Program SMBUS_BASE_ADDRESS and Enable it */ enable_smbus(); + /* Set up GPE configuration */ + pmc_gpe_init(); + soc_config_rtc(); enable_heci(); diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 476e2c6..974f1d8 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -23,7 +23,7 @@ #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 91f037a..0045fa0 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -187,6 +187,9 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Initialize GPEs */ +void pmc_gpe_init(void); + static inline int deep_s3_enabled(void) { uint32_t deep_s3_pol; diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index fd04287..23a289b 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -129,42 +129,6 @@ static void pch_rtc_init(void) cmos_init(rtc_failed); } -static void pmc_gpe_init(config_t *config) -{ - uint8_t *pmc_regs; - uint32_t gpio_cfg; - uint32_t gpio_cfg_reg; - const uint32_t gpio_cfg_mask = - (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW2_SHIFT); - - pmc_regs = pmc_mmio_regs(); - gpio_cfg = 0; - - /* Route the GPIOs to the GPE0 block. Determine that all values - * are different, and if they aren't use the reset values. */ - if (config->gpe0_dw0 == config->gpe0_dw1 || - config->gpe0_dw1 == config->gpe0_dw2) { - printk(BIOS_INFO, "PMC: Using default GPE route.\n"); - gpio_cfg = read32(pmc_regs + GPIO_CFG); - } else { - gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; - gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; - gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; - } - gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; - gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; - write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); - - /* Set the routes in the GPIO communities as well. */ - gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); - - /* Set GPE enables based on devictree. */ - enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, - config->gpe0_en_3, config->gpe0_en_4); -} - static void pch_power_options(void) { u16 reg16; @@ -172,7 +136,6 @@ static void pch_power_options(void) /*PMC Controller Device 0x1F, Func 02*/ device_t dev = PCH_DEV_PMC; /* Get the chip configuration */ - config_t *config = dev->chip_info; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* @@ -207,7 +170,7 @@ static void pch_power_options(void) printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ - pmc_gpe_init(config); + pmc_gpe_init(); } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index e450ce8..6ead7ed 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -19,6 +19,8 @@ * and the differences between PCH variants. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -27,6 +29,7 @@ #include <halt.h> #include <rules.h> #include <stdlib.h> +#include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -34,6 +37,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include "chip.h" /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -446,3 +450,47 @@ void poweroff(void) if (!ENV_SMM) halt(); } + +void pmc_gpe_init(void) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + uint8_t *pmc_regs; + uint32_t gpio_cfg; + uint32_t gpio_cfg_reg; + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT); + + /* Look up the device in devicetree */ + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + pmc_regs = pmc_mmio_regs(); + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. */ + gpio_cfg = 0; + if (config->gpe0_dw0 == config->gpe0_dw1 || + config->gpe0_dw1 == config->gpe0_dw2) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32(pmc_regs + GPIO_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + } + gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); + + /* Set GPE enables based on devictree. */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); +}

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Patch merged into coreboot/master: google/reef/variants/pyro: Use WCOM Touchscreen driver
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit 8be4fdfcc130e2d9cc113c51853b57a27b9333b0 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17093 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17093 for details. -gerrit

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Patch merged into coreboot/master: drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit 16e660560ab4892d8a3add2068b187b633c63361 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:42:45 2016 -0700 drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17092 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17092 for details. -gerrit

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Patch merged into coreboot/master: nb/x4x/gma.c: Remove writes to DP, FDI registers
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit f8a4f41d48acc9ecffc9d74185fad0cb8651f4da Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:49:35 2016 +0200 nb/x4x/gma.c: Remove writes to DP, FDI registers Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17111 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17111 for details. -gerrit

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Patch merged into coreboot/master: nb/gm45/gma.c: Remove writes to DP, FDI registers
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit 606b8bccb53e5bbc840d29657faaf333eff51e38 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:44:20 2016 +0200 nb/gm45/gma.c: Remove writes to DP, FDI registers Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17110 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17110 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/i945: Add PCI id for I945GC
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit 04be6b5949dae23ad989a35a2e6e6f750add6d04 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Oct 22 20:01:34 2016 +0200 nb/intel/i945: Add PCI id for I945GC Also drop an odd comment about the resource allocator which seems to work fine, with the right id. Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/17095 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17095 for details. -gerrit

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Patch set updated for coreboot: drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver
by Furquan Shaikh 26 Oct '16

26 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17092 -gerrit commit 1b6f933d50fcabd3776168eb246c19da2be815d1 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:42:45 2016 -0700 drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/wacom_ts/Kconfig | 3 ++ src/drivers/i2c/wacom_ts/Makefile.inc | 1 + src/drivers/i2c/wacom_ts/chip.h | 30 ++++++++++++++++++ src/drivers/i2c/wacom_ts/ts.c | 59 +++++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/src/drivers/i2c/wacom_ts/Kconfig b/src/drivers/i2c/wacom_ts/Kconfig new file mode 100644 index 0000000..50da3f1 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_I2C_WACOM_TS + bool + select DRIVERS_I2C_GENERIC diff --git a/src/drivers/i2c/wacom_ts/Makefile.inc b/src/drivers/i2c/wacom_ts/Makefile.inc new file mode 100644 index 0000000..9455099 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_WACOM_TS) += ts.c diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h new file mode 100644 index 0000000..b59f630 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_WACOM_TS_CHIP_H__ +#define __I2C_WACOM_TS_CHIP_H__ + +#include <drivers/i2c/generic/chip.h> + +#define WCOM50C1_HID "WCOM50C1" +#define PNP0C50_CID "PNP0C50" +#define WCOM_TS_DESC "WCOM Touchscreen" + +struct drivers_i2c_wacom_ts_config { + struct drivers_i2c_generic_config generic; + uint8_t hid_desc_reg_offset; +}; + +#endif /* __I2C_WACOM_TS_CHIP_H__ */ diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c new file mode 100644 index 0000000..ebc8883 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen_dsm.h> +#include <device/device.h> +#include <stdint.h> +#include "chip.h" + +static void i2c_wacom_ts_fill_dsm(struct device *dev) +{ + struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + struct dsm_i2c_hid_config dsm_config = { + .hid_desc_reg_offset = config->hid_desc_reg_offset, + }; + + acpigen_write_dsm_i2c_hid(&dsm_config); +} + +static void i2c_wacom_ts_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, &i2c_wacom_ts_fill_dsm); +} + +static const char *i2c_wacom_ts_acpi_name(struct device *dev) +{ + return "WCTS"; +} + +static struct device_operations i2c_wacom_ts_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &i2c_wacom_ts_acpi_name, + .acpi_fill_ssdt_generator = &i2c_wacom_ts_fill_ssdt_generator, +#endif +}; + +static void i2c_wacom_ts_enable(struct device *dev) +{ + dev->ops = &i2c_wacom_ts_ops; +} + +struct chip_operations drivers_i2c_wacom_ts_ops = { + CHIP_NAME("Wacom Touchscreen Device") + .enable_dev = &i2c_wacom_ts_enable +};

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Patch set updated for coreboot: google/reef/variants/pyro: Use WCOM Touchscreen driver
by Furquan Shaikh 26 Oct '16

26 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17093 -gerrit commit 38149f7665d252e731d90b584e3721474b43af69 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 ++++++++++------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d5d64c8..6045f47 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -40,6 +40,9 @@ config DRIVERS_I2C_DA7219 config DRIVERS_I2C_GENERIC default y +config DRIVERS_I2C_WACOM_TS + default y + config DRIVERS_PS2_KEYBOARD default y diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43ec2ed..a0ba584 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -131,12 +131,16 @@ chip soc/intel/apollolake end end # - I2C 2 device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" - device i2c 10 on end + chip drivers/i2c/wacom_ts + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_TS_DESC, + .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), + .probed = 1, + }" + register "hid_desc_reg_offset" = "0x1" + device i2c 0xA on end end end # - I2C 3 device pci 17.0 on

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coreboot-gerrit October 2016