coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: skylake: Use COMMON_FADT
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 135c2c48173d9ffb2476d204d8acc1b13d28859c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 17 19:47:51 2016 -0700 skylake: Use COMMON_FADT Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Set the ACPI revision to 5. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17138 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17138 for details. -gerrit

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Patch merged into coreboot/master: FILO: update STABLE
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 0d2bb80a86b3fbee9b93942a9f0dfac9f33f968b Author: Kevin Paul Herbert <kph(a)platinasystems.com> Date: Tue Jun 14 19:54:15 2016 -0700 FILO: update STABLE The STABLE build of FILO does not build anymore with the current HEAD of coreboot. However, the current HEAD of FILO does build with the current HEAD of coreboot. Update FILO STABLE to FILO HEAD. Change-Id: I4eece3aaada0dfdf4da106d5d260b5b361537558 Signed-off-by: Kevin Paul Herbert <kph(a)platinasystems.com> Reviewed-on: https://review.coreboot.org/15195 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/15195 for details. -gerrit

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Patch merged into coreboot/master: payload choice: Fix build of FILO
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 3e71dc591b0b6c831ff63d66a42792e859341a36 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 25 00:13:37 2016 +0300 payload choice: Fix build of FILO Actual build was missing libpayload path. Change-Id: I519869d2d64c66b3d1d557595c7d13c22cd40819 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17114 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17114 for details. -gerrit

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Patch set updated for coreboot: riscv: add the lowrisc/nexys4ddr mainboard
by Ronald G. Minnich 27 Oct '16

27 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17132 -gerrit commit df8ba6512eebc252efb2e702eb49c81379a4aca5 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Oct 25 19:11:07 2016 -0700 riscv: add the lowrisc/nexys4ddr mainboard This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/lowrisc/Kconfig | 16 ++++ src/mainboard/lowrisc/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Kconfig | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Makefile.inc | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/board_info.txt | 3 + src/mainboard/lowrisc/nexys4ddr/devicetree.cb | 20 +++++ src/mainboard/lowrisc/nexys4ddr/mainboard.c | 37 +++++++++ src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 31 ++++++++ src/mainboard/lowrisc/nexys4ddr/rom_media.c | 29 +++++++ src/mainboard/lowrisc/nexys4ddr/romstage.c | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/uart.c | 39 ++++++++++ src/mainboard/lowrisc/nexys4ddr/util.c | 103 +++++++++++++++++++++++++ 13 files changed, 376 insertions(+) diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig new file mode 100644 index 0000000..ba0fbe7 --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LOWRISC + +choice + prompt "Mainboard model" + +source "src/mainboard/lowrisc/*/Kconfig.name" + +endchoice + +source "src/mainboard/lowrisc/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "lowrisc" + +endif # VENDOR_LOWRISC diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name new file mode 100644 index 0000000..4c992fc --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LOWRISC + bool "lowrisc" diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig new file mode 100644 index 0000000..f0a3637 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_LOWRISC_NEXYS4DDR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_LOWRISC_LOWRISC + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_UART_8250MEM + select BOOT_DEVICE_NOT_SPI_FLASH + select UART_OVERRIDE_REFCLK + select UART_OVERRIDE_INPUT_CLOCK_DIVIDER + +config MAINBOARD_DIR + string + default lowrisc/nexys4ddr + +config MAINBOARD_PART_NUMBER + string + default "LOWRISC NEXYS4DDR" + +config MAX_CPUS + int + default 1 + +endif # BOARD_LOWRISC_NEXYS4DDR diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name new file mode 100644 index 0000000..f99b3cc --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LOWRISC_NEXYS4DDR + bool "nexys4ddr" diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc new file mode 100644 index 0000000..7af6ede --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +bootblock-y += uart.c +bootblock-y += util.c +bootblock-y += rom_media.c +romstage-y += romstage.c +romstage-y += uart.c +romstage-y += util.c +romstage-y += rom_media.c +ramstage-y += uart.c +ramstage-y += util.c +ramstage-y += rom_media.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt new file mode 100644 index 0000000..258cf6c --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/board_info.txt @@ -0,0 +1,3 @@ +Board name: lowrisc nexys4ddr +Category: eval +Board URL: http://www.lowrisc.org/docs/debug-v0.3/ diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb new file mode 100644 index 0000000..e3ce088 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c new file mode 100644 index 0000000..3b883ce --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> + +static void mainboard_enable(device_t dev) +{ + /* + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; + + if (!dev) + die("No dev0; die\n"); + + ram_resource(dev, 0, 0x80000000/KiB, ram_size/KiB); + + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld new file mode 100644 index 0000000..c0ef78f --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +#define START 0x80000000 + +SECTIONS +{ + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + PAGETABLES(START + 8M + 200K, 56K) + RAMSTAGE(START + 8M + 256K, 256K) +} diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c new file mode 100644 index 0000000..bdb05ab --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> + +/* + * 0x80000000 is the start of RAM. We currently need to load coreboot.rom into + * RAM. The actual "rom" code on the FPGAs is in a block ram. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c new file mode 100644 index 0000000..ff4a082 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/romstage.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> + +void main(void) +{ + // You currently can not call console_init from romstage. It brings + // in COREBOOT_EXTRA_VERSION, which is in .data, and we get a linker + // warning. I suspect the best fix is to have all the declarations + // in src/lib/version.c set up to be in the .text or .rodata + // section but that's a problem for another day. At some point + // we'd like to call console_init here. + // console_init(); + run_ramstage(); +} diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c new file mode 100644 index 0000000..89f9896 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/uart.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <spike_util.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t) 0x42000000; +} + +/* these are currently not quite right but they are here for reference + * and will be fixed soon. */ +// divisor = clk_freq / (16 * Baud) +unsigned int uart_input_clock_divider(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) % 0x100; +} + +// System clock 25 MHz, 115200 baud rate +unsigned int uart_platform_refclk(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) >> 8; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c new file mode 100644 index 0000000..32cdb6d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/util.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, + * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING + * LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS + * DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING + * DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS + * IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, + * UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + /* Ensure the other hart sees it. */ + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +}

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Patch set updated for coreboot: Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17153 -gerrit commit 1cf12775e2478d38dd473ec97426bb00f493b969 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:30:07 2016 +0200 Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig Change-Id: I51cf4f35bf2ea95c8c19ab885e6308535314b0af Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_1067x/Kconfig | 1 + src/northbridge/intel/gm45/Kconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index da8ddc5..12f04cc 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -6,5 +6,6 @@ config CPU_INTEL_MODEL_1067X select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 +# select UDELAY_LAPIC select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index d4f4390..6ee6558 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI - select UDELAY_LAPIC config CBFS_SIZE hex

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Patch set updated for coreboot: nb/intel/gm45: Use LAPIC udelay instead of custom version
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17152 -gerrit commit 3875a3716965de11ed3a2d540d477daac0cf34fa Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:31:41 2016 +0200 nb/intel/gm45: Use LAPIC udelay instead of custom version This change may slow down the raminit by maximum 200usec, but reuses the lapic udelay definition. Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/Kconfig | 2 +- src/northbridge/intel/gm45/Makefile.inc | 1 - src/northbridge/intel/gm45/delay.c | 10 ---------- src/northbridge/intel/gm45/delay.h | 24 ------------------------ src/northbridge/intel/gm45/raminit.c | 8 ++++---- 5 files changed, 5 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index d254b9e..d4f4390 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI - select UDELAY_TSC + select UDELAY_LAPIC config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 794b2b9..ac5810b 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y) romstage-y += early_init.c romstage-y += early_reset.c -romstage-y += delay.c romstage-y += raminit.c romstage-y += raminit_rcomp_calibration.c romstage-y += raminit_receive_enable_calibration.c diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index ad2e543..328c751 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -84,13 +84,3 @@ void udelay(const u32 us) { _udelay(us, 1, 0); } - -void ns100delay(const u32 ns100) -{ - _udelay(ns100, 10, 0); -} - -void udelay_from_reset(const u32 us) -{ - _udelay(us, 1, 1); -} diff --git a/src/northbridge/intel/gm45/delay.h b/src/northbridge/intel/gm45/delay.h deleted file mode 100644 index d84c5fb..0000000 --- a/src/northbridge/intel/gm45/delay.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__ -#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ - -#include <delay.h> - -void ns100delay(u32); -void udelay_from_reset(u32); - -#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */ diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 37b44cc..167ef24 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -24,7 +24,7 @@ #include <spd.h> #include <console/console.h> #include <lib.h> -#include "delay.h" +#include <delay.h> #include "gm45.h" #include "chip.h" @@ -916,15 +916,15 @@ static void rcomp_initialization(const stepping_t stepping, const int sff) static void dram_powerup(const int resume) { - udelay_from_reset(200); + udelay(200); MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21); if (!resume) { MCHBAR32(0x1434) |= (1 << 10); - ns100delay(2); + udelay(1); } MCHBAR32(0x1434) |= (1 << 6); if (!resume) { - ns100delay(1); + udelay(1); MCHBAR32(0x1434) |= (1 << 9); MCHBAR32(0x1434) &= ~(1 << 10); udelay(500);

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Patch set updated for coreboot: mb/lenovo/t400: use socket mPGA478MN instead of BGA945
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17155 -gerrit commit 549fe0f9097a1025ad093c050fd67ba32dcca688 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:36:02 2016 +0200 mb/lenovo/t400: use socket mPGA478MN instead of BGA945 The T400 features a socket P (mPGA478MN) and could potentially support model_6fx CPUs. Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/Kconfig | 2 +- src/mainboard/lenovo/t400/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 194e38c..47e7688 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_BGA956 + select CPU_INTEL_SOCKET_MPGA478MN select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 6bf25fa..867d7797 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/gm45 register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on - chip cpu/intel/socket_BGA956 + chip cpu/intel/socket_mPGA478MN device lapic 0 on end end chip cpu/intel/model_1067x

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Patch set updated for coreboot: cpu/intel/socket_mPGA478MN: Add socket P
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17154 -gerrit commit 47f07099bcd9b58484752b5655b26e53ca33e719 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:34:18 2016 +0200 cpu/intel/socket_mPGA478MN: Add socket P This mobile CPU socket supports model_6fx and model_1067x. Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_mPGA478MN/Kconfig | 18 ++++++++++++++++++ src/cpu/intel/socket_mPGA478MN/Makefile.inc | 14 ++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 806a08e..5df8002 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -31,6 +31,7 @@ source src/cpu/intel/socket_FCBGA559/Kconfig source src/cpu/intel/socket_mFCBGA479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig +source src/cpu/intel/socket_mPGA478MN/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 536b40e..1874075 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig new file mode 100644 index 0000000..7c4dbc5 --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Kconfig @@ -0,0 +1,18 @@ +config CPU_INTEL_SOCKET_MPGA478MN + bool + select CPU_INTEL_MODEL_1067X + select CPU_INTEL_MODEL_6FX + select MMX + select SSE + +if CPU_INTEL_SOCKET_MPGA478MN + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc new file mode 100644 index 0000000..fe6509b --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc @@ -0,0 +1,14 @@ +subdirt-y += ../model_6fx +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +romstage-y += ../car/romstage.c

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Patch set updated for coreboot: arch/x86/acpigen: Add OperationRegion & Field method.
by Naresh Solanki 27 Oct '16

27 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17113 -gerrit commit 4756d519a9963c8f5a694c91c2fedaececcd1a38 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Oct 25 00:51:24 2016 +0530 arch/x86/acpigen: Add OperationRegion & Field method. OperationRegion : This requires region name, region space, region length & region size packed as input. Field : This requires Operation region name & field list as input. Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/arch/x86/acpigen.c | 91 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 67 +++++++++++++++++++++++++++ 2 files changed, 158 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 42d4204..39247f1 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -351,6 +351,97 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(pblock_len); } + +void acpigen_write_opregion(struct opregion *opreg) +{ + /* OpregionOp */ + acpigen_emit_ext_op(OPREGION_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(opreg->name); + /* RegionSpace */ + acpigen_emit_byte(opreg->regionspace); + /* RegionOffset & RegionLen, it can be byte word or double word */ + acpigen_write_integer(opreg->regionoffset); + acpigen_write_integer(opreg->regionlen); +} + +static void acpigen_write_field_offset(u32 offset, u32 current_bit_pos) +{ + u32 diff_bits; + u32 i, j; + u8 emit[4]; + diff_bits = offset - current_bit_pos; + + if (offset < current_bit_pos) { + printk(BIOS_WARNING, "%s: Cannot move offset backward", + __func__); + return; + } + + /* Upper limit */ + if (diff_bits > 0xFFFFFFF) { + printk(BIOS_WARNING, "%s: Offset very large to encode", + __func__); + return; + } + + if (diff_bits < 0x40) { + emit[0] = diff_bits & 0x3F; + i = 1; + } else { + emit[0] = diff_bits & 0xF; + diff_bits >>= 4; + i = 1; + while (diff_bits) { + emit[i] = diff_bits & 0xFF; + i++; + diff_bits >>= 8; + } + } + /* Update bit 7:6 : Number of byte followed by emit[0] */ + emit[0] |= (i-1) << 6; + + acpigen_emit_byte(0); + for (j = 0; j < i; j++) + acpigen_emit_byte(emit[j]); +} + +void acpigen_write_field(const char *name, struct fieldlist *l, u8 flags) +{ + u16 i = 0; + u32 current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); + /* Field Flag */ + acpigen_emit_byte(flags); + + while (1) { + if (l[i].type == NAME_STRING) { + acpigen_emit_simple_namestring(l[i].name); + acpigen_emit_byte(l[i].bits); + current_bit_pos += l[i].bits; + } else if (l[i].type == OFFSET) { + acpigen_write_field_offset(l[i].bits, current_bit_pos); + current_bit_pos = l[i].bits; + } else { + /* break on FIELD_TYPE_MAX, if type is other than this + * then display error message. + */ + if (l[i].type != FIELD_TYPE_MAX) + printk(BIOS_ERR, "%s:Invalid field type 0x%X\n", + __func__, l[i].type); + break; + } + i++; + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 7c15a31..49251ca 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -53,6 +53,8 @@ enum { EXT_OP_PREFIX = 0x5B, SLEEP_OP = 0x22, DEBUG_OP = 0x31, + OPREGION_OP = 0x80, + FIELD_OP = 0x81, DEVICE_OP = 0x82, PROCESSOR_OP = 0x83, POWER_RES_OP = 0x84, @@ -84,6 +86,69 @@ enum { ONES_OP = 0xFF, }; +#define FIELDLIST_OFFSET(X) { .type = OFFSET, \ + .name = "",\ + .bits = X * 8, \ + } +#define FIELDLIST_NAMESTR(X, Y) { .type = NAME_STRING, \ + .name = X, \ + .bits = Y, \ + } + +#define FIELDLIST_END { .type = FIELD_TYPE_MAX,\ + .name = "", \ + .bits = 0, \ + } + +#define FIELD_ANYACC 0 +#define FIELD_BYTEACC 1 +#define FIELD_WORDACC 2 +#define FIELD_DWORDACC 3 +#define FIELD_QWORDACC 4 +#define FIELD_BUFFERACC 5 +#define FIELD_NOLOCK (0<<4) +#define FIELD_LOCK (1<<4) +#define FIELD_PRESERVE (0<<5) +#define FIELD_WRITEASONES (1<<5) +#define FIELD_WRITEASZEROS (2<<5) + +enum field_type { + OFFSET, + NAME_STRING, + FIELD_TYPE_MAX, +}; + +struct fieldlist { + enum field_type type; + const char *name; + u32 bits; +}; + +#define OPREGION(rname, space, offset, len) {.name = rname, \ + .regionspace = space, \ + .regionoffset = offset, \ + .regionlen = len, \ + } + +enum region_space { + SYSTEMMEMORY, + SYSTEMIO, + PCI_CONFIG, + EMBEDDEDCONTROL, + SMBUS, + CMOS, + PCIBARTARGET, + IPMI, + REGION_SPACE_MAX, +}; + +struct opregion { + const char *name; + enum region_space regionspace; + unsigned long regionoffset; + unsigned long regionlen; +}; + void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); @@ -176,6 +241,8 @@ void acpigen_write_return_byte(uint8_t arg); void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), size_t count, void *arg); +void acpigen_write_opregion(struct opregion *opreg); +void acpigen_write_field(const char *name, struct fieldlist *l, u8 flags); int get_cst_entries(acpi_cstate_t **); /*

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Patch set updated for coreboot: Makefile.inc: Explicitly disable PIE
by Paul Menzel 27 Oct '16

27 Oct '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17097 -gerrit commit 332a2ac528b4f0e3778c15f4ee187cd59ad6bca6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Oct 23 20:38:36 2016 +0200 Makefile.inc: Explicitly disable PIE Some distribution compilers enable Position Independent Executable (PIE) by default, causing a build failure. So explicitly disable PIE by passing the flag `-fno-pie`, to fix the build error. Change-Id: I1b7d7168e34c5c93c25bc03ffa49b2eeac0e76f8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index f5b7c4c..8389ba4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -356,7 +356,7 @@ CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototype CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -CFLAGS_common += -ffunction-sections -fdata-sections +CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ADAFLAGS_common += -gnatg -gnatp ADAFLAGS_common += -Wuninitialized -Wall -Werror

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coreboot-gerrit October 2016