coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panels
by Stefan Reinauer 27 Oct '16

27 Oct '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17108 -gerrit commit 20aee13942af5fcb8d1d3f347fa7db0fa68d7c44 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 17 17:29:09 2016 -0700 rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panels Some of our RK3399 devices have panel resolutions as high as 2400x1600. With 16bpp that barely still fit into an 8MB framebuffer, but then we changed it to 32bpp for better image quality... Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't be used at all on ARM64 devices, since libpayload is perfectly capable to dynamically allocate it with the right size based on EDID-information on this architecture. That will require some more elaborate work to be fixed with later patches. BRANCH=gru BUG=chrome-os-partner:58044 TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the lower half of the screen that overflowed our allocated framebuffer preserved from the last boot as soon as the backlight turns on. Change-Id: I00a63cfef35a8ee734543abbdb298344fb529283 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d2718efcacb50371624d9f6a3b586c298e8c2fec Original-Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/399966 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index ef8d29d..a441281 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -22,7 +22,7 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00100000, 1M) RAMSTAGE(0x00300000, 256K) DMA_COHERENT(0x10000000, 2M) - FRAMEBUFFER(0x10200000, 8M) + FRAMEBUFFER(0x10200000, 16M) /* 8K of special SRAM in PMU power domain. */ SYMBOL(pmu_sram, 0xFF3B0000)

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Patch set updated for coreboot: FILO: update STABLE
by Stefan Reinauer 27 Oct '16

27 Oct '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15195 -gerrit commit 57c7d74ea492eddd3e39e603d2edd70df4035b2e Author: Kevin Paul Herbert <kph(a)platinasystems.com> Date: Tue Jun 14 19:54:15 2016 -0700 FILO: update STABLE The STABLE build of FILO does not build anymore with the current HEAD of coreboot. However, the current HEAD of FILO does build with the current HEAD of coreboot. Update FILO STABLE to FILO HEAD. Change-Id: I4eece3aaada0dfdf4da106d5d260b5b361537558 Signed-off-by: Kevin Paul Herbert <kph(a)platinasystems.com> --- payloads/external/FILO/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index 2c85cec..283a6d4 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -1,6 +1,6 @@ TAG-$(CONFIG_FILO_MASTER)=origin/master NAME-$(CONFIG_FILO_MASTER)=MASTER -TAG-$(CONFIG_FILO_STABLE)=4dbb31a64fe5b1c7e3025ab34619220609897646 +TAG-$(CONFIG_FILO_STABLE)=22baa6bde9339029edfafa421b3d4a7be159edad NAME-$(CONFIG_FILO_STABLE)=STABLE project_git_repo=http://review.coreboot.org/p/filo.git

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Patch set updated for coreboot: cpu/intel/model_1067x: Select LAPIC_UDELAY
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17153 -gerrit commit 24cdc99eac6efdfcab67e6d7e89b56ae19130529 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:30:07 2016 +0200 cpu/intel/model_1067x: Select LAPIC_UDELAY The purpose of this change is to allow the gm45 northbridge to use the LAPIC udelay function. Change-Id: I51cf4f35bf2ea95c8c19ab885e6308535314b0af Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_1067x/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index da8ddc5..12f04cc 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -6,5 +6,6 @@ config CPU_INTEL_MODEL_1067X select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 +# select UDELAY_LAPIC select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS

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New patch to review for coreboot: mb/lenovo/t400: use socket mPGA478MN instead of BGA945
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17155 -gerrit commit df08733972b0e85dab81bb99346d92152e7ee51d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:36:02 2016 +0200 mb/lenovo/t400: use socket mPGA478MN instead of BGA945 The T400 features a socket P (mPGA478MN) and could potentially support model_6fx CPUs. Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/Kconfig | 2 +- src/mainboard/lenovo/t400/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 194e38c..47e7688 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_BGA956 + select CPU_INTEL_SOCKET_MPGA478MN select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 6bf25fa..867d7797 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/gm45 register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on - chip cpu/intel/socket_BGA956 + chip cpu/intel/socket_mPGA478MN device lapic 0 on end end chip cpu/intel/model_1067x

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New patch to review for coreboot: cpu/intel/socket_mPGA478MN: Add socket P
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17154 -gerrit commit e850ad56d84f79239e7010e57b1b6e6dcf686471 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:34:18 2016 +0200 cpu/intel/socket_mPGA478MN: Add socket P This mobile CPU socket supports model_6fx and model_1067x. Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_mPGA478MN/Kconfig | 18 ++++++++++++++++++ src/cpu/intel/socket_mPGA478MN/Makefile.inc | 14 ++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 806a08e..5df8002 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -31,6 +31,7 @@ source src/cpu/intel/socket_FCBGA559/Kconfig source src/cpu/intel/socket_mFCBGA479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig +source src/cpu/intel/socket_mPGA478MN/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 536b40e..1874075 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig new file mode 100644 index 0000000..7c4dbc5 --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Kconfig @@ -0,0 +1,18 @@ +config CPU_INTEL_SOCKET_MPGA478MN + bool + select CPU_INTEL_MODEL_1067X + select CPU_INTEL_MODEL_6FX + select MMX + select SSE + +if CPU_INTEL_SOCKET_MPGA478MN + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc new file mode 100644 index 0000000..fe6509b --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc @@ -0,0 +1,14 @@ +subdirt-y += ../model_6fx +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +romstage-y += ../car/romstage.c

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New patch to review for coreboot: cpu/intel/model_1067x: Select LAPIC_UDELAY
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17153 -gerrit commit bab03b1c4066201d8cce700a1f11c1288e68ba13 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:30:07 2016 +0200 cpu/intel/model_1067x: Select LAPIC_UDELAY Change-Id: I51cf4f35bf2ea95c8c19ab885e6308535314b0af Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_1067x/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index da8ddc5..12f04cc 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -6,5 +6,6 @@ config CPU_INTEL_MODEL_1067X select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 +# select UDELAY_LAPIC select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS

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New patch to review for coreboot: gm45/raminit.c: Use LAPIC udelay instead of custom version
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17152 -gerrit commit bed6660c916f53729d873530f26abc4f583a5354 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:31:41 2016 +0200 gm45/raminit.c: Use LAPIC udelay instead of custom version This change may slow down the raminit by maximum 200usec, but reuses the the lapic udelay definition. Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/gm45/Makefile.inc | 1 - src/northbridge/intel/gm45/raminit.c | 6 +++--- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index d254b9e..6ee6558 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI - select UDELAY_TSC config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 794b2b9..ac5810b 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y) romstage-y += early_init.c romstage-y += early_reset.c -romstage-y += delay.c romstage-y += raminit.c romstage-y += raminit_rcomp_calibration.c romstage-y += raminit_receive_enable_calibration.c diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 37b44cc..a2141cd 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -916,15 +916,15 @@ static void rcomp_initialization(const stepping_t stepping, const int sff) static void dram_powerup(const int resume) { - udelay_from_reset(200); + udelay(200); MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21); if (!resume) { MCHBAR32(0x1434) |= (1 << 10); - ns100delay(2); + udelay(1); } MCHBAR32(0x1434) |= (1 << 6); if (!resume) { - ns100delay(1); + udelay(1); MCHBAR32(0x1434) |= (1 << 9); MCHBAR32(0x1434) &= ~(1 << 10); udelay(500);

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Patch set updated for coreboot: skylake: Prepare GPE for use in bootblock
by Duncan Laurie 27 Oct '16

27 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17135 -gerrit commit f174d3020fbb54dfd10746224922a2146185b821 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:03:56 2016 -0700 skylake: Prepare GPE for use in bootblock Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/bootblock/pch.c | 3 ++ src/soc/intel/skylake/include/soc/pci_devs.h | 2 +- src/soc/intel/skylake/include/soc/pm.h | 3 ++ src/soc/intel/skylake/pmc.c | 39 +--------------------- src/soc/intel/skylake/pmutil.c | 48 ++++++++++++++++++++++++++++ 5 files changed, 56 insertions(+), 39 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 57b5fed..371dd63 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -301,6 +301,9 @@ void pch_early_init(void) /* Program SMBUS_BASE_ADDRESS and Enable it */ enable_smbus(); + /* Set up GPE configuration */ + pmc_gpe_init(); + soc_config_rtc(); enable_heci(); diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 476e2c6..974f1d8 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -23,7 +23,7 @@ #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 91f037a..0045fa0 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -187,6 +187,9 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Initialize GPEs */ +void pmc_gpe_init(void); + static inline int deep_s3_enabled(void) { uint32_t deep_s3_pol; diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index fd04287..23a289b 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -129,42 +129,6 @@ static void pch_rtc_init(void) cmos_init(rtc_failed); } -static void pmc_gpe_init(config_t *config) -{ - uint8_t *pmc_regs; - uint32_t gpio_cfg; - uint32_t gpio_cfg_reg; - const uint32_t gpio_cfg_mask = - (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW2_SHIFT); - - pmc_regs = pmc_mmio_regs(); - gpio_cfg = 0; - - /* Route the GPIOs to the GPE0 block. Determine that all values - * are different, and if they aren't use the reset values. */ - if (config->gpe0_dw0 == config->gpe0_dw1 || - config->gpe0_dw1 == config->gpe0_dw2) { - printk(BIOS_INFO, "PMC: Using default GPE route.\n"); - gpio_cfg = read32(pmc_regs + GPIO_CFG); - } else { - gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; - gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; - gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; - } - gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; - gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; - write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); - - /* Set the routes in the GPIO communities as well. */ - gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); - - /* Set GPE enables based on devictree. */ - enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, - config->gpe0_en_3, config->gpe0_en_4); -} - static void pch_power_options(void) { u16 reg16; @@ -172,7 +136,6 @@ static void pch_power_options(void) /*PMC Controller Device 0x1F, Func 02*/ device_t dev = PCH_DEV_PMC; /* Get the chip configuration */ - config_t *config = dev->chip_info; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* @@ -207,7 +170,7 @@ static void pch_power_options(void) printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ - pmc_gpe_init(config); + pmc_gpe_init(); } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index e450ce8..6ead7ed 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -19,6 +19,8 @@ * and the differences between PCH variants. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -27,6 +29,7 @@ #include <halt.h> #include <rules.h> #include <stdlib.h> +#include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -34,6 +37,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include "chip.h" /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -446,3 +450,47 @@ void poweroff(void) if (!ENV_SMM) halt(); } + +void pmc_gpe_init(void) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + uint8_t *pmc_regs; + uint32_t gpio_cfg; + uint32_t gpio_cfg_reg; + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT); + + /* Look up the device in devicetree */ + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + pmc_regs = pmc_mmio_regs(); + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. */ + gpio_cfg = 0; + if (config->gpe0_dw0 == config->gpe0_dw1 || + config->gpe0_dw1 == config->gpe0_dw2) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32(pmc_regs + GPIO_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + } + gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); + + /* Set GPE enables based on devictree. */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); +}

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Patch set updated for coreboot: skylake: Fix wake source reporting with Deep S3
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17137 -gerrit commit 6bb30c19891ca4b42e7dddff3b8c302a8d4f80c7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:07:22 2016 -0700 skylake: Fix wake source reporting with Deep S3 The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index d83c74b..ca7bafa 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -588,23 +588,40 @@ void southcluster_inject_dsdt(device_t device) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = dev->chip_info; struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; + uint32_t gpe0_std; int i; ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps == NULL) return -1; - /* PM1_EN state is lost in Deep S3 so enable basic wake events */ - pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS; + pm1_en = ps->pm1_en; + gpe0_std = ps->gpe0_en[3]; + + /* + * Chipset state in the suspend well (but not RTC) is lost in Deep S3 + * so enable Deep S3 wake events that are configured by the mainboard + */ + if (ps->prev_sleep_state == ACPI_S3 && config->deep_s3_enable) { + pm1_en |= PWRBTN_STS; /* Always enabled as wake source */ + if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN) + gpe0_std |= LAN_WAK_EN; + if (config->deep_sx_config & DSX_EN_WAKE_PIN) + pm1_en |= PCIEXPWAK_STS; + } + *pm1 = ps->pm1_sts & pm1_en; /* Mask off GPE0 status bits that are not enabled */ *gpe0 = &gpe0_sts[0]; - for (i = 0; i < GPE0_REG_MAX; i++) + for (i = 0; i < (GPE0_REG_MAX-1); i++) gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; + gpe0_sts[3] = ps->gpe0_sts[3] & gpe0_std; return GPE0_REG_MAX; }

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Patch set updated for coreboot: skylake: Support for early I2C TPM driver
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17136 -gerrit commit 88be359ccb78e255d587cd019cd799d01767170b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:05:31 2016 -0700 skylake: Support for early I2C TPM driver Add the SOC definition for acpi_get_gpe() so it can be used by the I2C TPM driver. Also add the I2C support code to verstage so it can get used by vboot. BUG=chrome-os-partner:58666 TEST=boot with I2C TPM on skylake board Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 3 ++- src/soc/intel/skylake/pmutil.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index bf429ef..1714572 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -30,7 +30,8 @@ bootblock-y += tsc_freq.c verstage-y += flash_controller.c verstage-y += monotonic_timer.c verstage-y += pch.c -verstage-$(CONFIG_UART_DEBUG) += uart_debug.c +verstage-y += pmutil.c +verstage-y += bootblock/i2c.c romstage-y += flash_controller.c romstage-y += gpio.c diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 6ead7ed..203a430 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -356,6 +356,26 @@ u32 clear_gpe_status(void) gpe0_sts_3_bits); } +/* Read and clear GPE status (defined in arch/acpi.h) */ +int acpi_get_gpe(int gpe) +{ + int bank; + uint32_t mask, sts; + + if (gpe < 0 || gpe > GPE0_WADT) + return -1; + + bank = gpe / 32; + mask = 1 << (gpe % 32); + + sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); + if (sts & mask) { + outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + return 1; + } + return 0; +} + /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) {

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coreboot-gerrit October 2016