coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

New patch to review for coreboot: util/xcompile/xcompile: Add a space before `&&`
by Paul Menzel 27 Oct '16

27 Oct '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17159 -gerrit commit 036d72d764cb484dbedabc970630e3c3528875a0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Oct 27 08:28:55 2016 +0200 util/xcompile/xcompile: Add a space before `&&` Change-Id: I07fd4d6f6db220e23da8daced6014ce39894c604 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 37e6404..90220f6 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -182,7 +182,7 @@ detect_special_flags() { testcc "$GCC" "$CFLAGS_GCC -fuse-ld=bfd" && CFLAGS_GCC="$CFLAGS_GCC -fuse-ld=bfd" && LINKER_SUFFIX='.bfd' - testcc "$GCC" "$CFLAGS_GCC -fno-stack-protector"&& + testcc "$GCC" "$CFLAGS_GCC -fno-stack-protector" && CFLAGS_GCC="$CFLAGS_GCC -fno-stack-protector" testcc "$GCC" "$CFLAGS_GCC -Wl,--build-id=none" && CFLAGS_GCC="$CFLAGS_GCC -Wl,--build-id=none"

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Patch set updated for coreboot: arch/x86/acpigen: Add OperationRegion & Field method.
by Naresh Solanki 27 Oct '16

27 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17113 -gerrit commit 156c31b86e6df73ceadbb1b048d9e8a002d14bdd Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Oct 25 00:51:24 2016 +0530 arch/x86/acpigen: Add OperationRegion & Field method. OperationRegion : This requires region name, region space, region length & region size packed as input. Field : This requires Operation region name & field list as input. Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/arch/x86/acpigen.c | 78 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 67 +++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 42d4204..cf2633d 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -351,6 +351,84 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(pblock_len); } + +void acpigen_write_opregion(struct opregion *opreg) +{ + /* OpregionOp */ + acpigen_emit_ext_op(OPREGION_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(opreg->name); + /* RegionSpace */ + acpigen_emit_byte(opreg->regionspace); + /* RegionOffset & RegionLen, it can be byte word or double word */ + acpigen_write_integer(opreg->regionoffset); + acpigen_write_integer(opreg->regionlen); +} + +static void acpigen_write_field_offset(u32 offset, u32 current_bit_pos) +{ + u32 diff_bits; + u32 i, j; + u8 emit[4]; + diff_bits = offset - current_bit_pos; + + if (offset < current_bit_pos) + return; + + /* Upper limit */ + if (diff_bits > 0xFFFFFFF) + return; + + emit[0] = diff_bits & 0xF; + diff_bits >>= 4; + i = 1; + + while (diff_bits) { + emit[i] = diff_bits & 0xFF; + i++; + diff_bits >>= 8; + } + + /* Update bit 7:6 : Number of byte followed by emit[0] */ + emit[0] |= (i-1) << 6; + + acpigen_emit_byte(0); + for (j = 0; j < i; j++) + acpigen_emit_byte(emit[j]); +} + +void acpigen_write_field(const char *name, struct fieldlist *l, u8 flags) +{ + u16 i = 0; + u32 current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); + /* Field Flag */ + acpigen_emit_byte(flags); + + while (1) { + if (l[i].type == NAME_STRING) { + acpigen_emit_simple_namestring(l[i].name); + acpigen_emit_byte(l[i].bits); + current_bit_pos += l[i].bits; + } else if (l[i].type == OFFSET) { + acpigen_write_field_offset(l[i].bits, current_bit_pos); + current_bit_pos = l[i].bits; + } else if (l[i].type == FIELD_TYPE_MAX) { + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", + __func__, l[i].type); + break; + } + i++; + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 7c15a31..db2c1a2 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -53,6 +53,8 @@ enum { EXT_OP_PREFIX = 0x5B, SLEEP_OP = 0x22, DEBUG_OP = 0x31, + OPREGION_OP = 0x80, + FIELD_OP = 0x81, DEVICE_OP = 0x82, PROCESSOR_OP = 0x83, POWER_RES_OP = 0x84, @@ -84,6 +86,69 @@ enum { ONES_OP = 0xFF, }; +#define FIELDLIST_OFFSET(X) { .type = OFFSET, \ + .name = "",\ + .bits = X * 8, \ + } +#define FIELDLIST_NAMESTR(X, Y) { .type = NAME_STRING, \ + .name = X, \ + .bits = Y, \ + } + +#define FIELDLIST_END { .type = FIELD_TYPE_MAX,\ + .name = "", \ + .bits = 0, \ + } + +#define FIELD_ANYACC 0 +#define FIELD_BYTEACC 1 +#define FIELD_WORDACC 2 +#define FIELD_DWORDACC 3 +#define FIELD_QWORDACC 4 +#define FIELD_BUFFERACC 5 +#define FIELD_NOLOCK (0<<4) +#define FIELD_LOCK (1<<4) +#define FIELD_PRESERVE (0<<5) +#define FIELD_WRITEASONES (1<<5) +#define FIELD_WRITEASZEROS (2<<5) + +enum field_type { + OFFSET, + NAME_STRING, + FIELD_TYPE_MAX, +}; + +struct fieldlist { + enum field_type type; + const char *name; + u32 bits; +}; + +#define OPREGION(rname, space, offset, len) {.name = rname, \ + .regionspace = space, \ + .regionoffset = offset, \ + .regionlen = len, \ + } + +enum region_space { + SYSTEMMEMORY, + SYSTEMIO, + PCI_CONFIG, + EMBEDDEDCONTROL, + SMBUS, + CMOS, + PCIBARTARGET, + IPMI, + REGION_SPACE_MAX, +}; + +struct opregion { + const char *name; + enum region_space regionspace; + unsigned long regionoffset; + unsigned long regionlen; +}; + void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); @@ -176,6 +241,8 @@ void acpigen_write_return_byte(uint8_t arg); void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), size_t count, void *arg); +void acpigen_write_opregion(struct opregion *opreg); +void acpigen_write_field(const char *name, struct fieldlist *l, u8 field); int get_cst_entries(acpi_cstate_t **); /*

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Patch set updated for coreboot: arch/x86/acpigen: Add OperationRegion & Field method.
by Naresh Solanki 27 Oct '16

27 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17113 -gerrit commit 7671fbbc09e710907635859acd7bae65913750fb Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Oct 25 00:51:24 2016 +0530 arch/x86/acpigen: Add OperationRegion & Field method. OperationRegion : This requires region name, region space, region length & region size packed as input. Field : This requires Operation region name & field list as input. Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/arch/x86/acpigen.c | 78 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 67 +++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 42d4204..db387c2 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -351,6 +351,84 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(pblock_len); } + +void acpigen_write_opregion(struct opregion *opreg) +{ + /* OpregionOp */ + acpigen_emit_ext_op(OPREGION_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(opreg->name); + /* RegionSpace */ + acpigen_emit_byte(opreg->regionspace); + /* RegionOffset & RegionLen, it can be byte word or double word */ + acpigen_write_integer(opreg->regionoffset); + acpigen_write_integer(opreg->regionlen); +} + +static void acpigen_write_field_offset(u32 offset, u32 current_bit_pos) +{ + u32 diff_bits; + u32 i, j; + u8 emit[4]; + diff_bits = offset - current_bit_pos; + + if (offset < current_bit_pos) + return; + + /* Upper limit */ + if (diff_bits > 0xFFFFFFF) + return; + + emit[0] = diff_bits & 0xF; + diff_bits >>= 4; + i = 1; + + while (diff_bits) { + emit[i] = diff_bits & 0xFF; + i++; + diff_bits >>= 8; + } + + /* Update bit 7:6 : Number of byte followed byt this */ + emit[0] |= (i-1) << 6; + + acpigen_emit_byte(0); + for (j = 0; j < i; j++) + acpigen_emit_byte(emit[j]); +} + +void acpigen_write_field(const char *name, struct fieldlist *l, u8 flags) +{ + u16 i = 0; + u32 current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); + /* Field Flag */ + acpigen_emit_byte(flags); + + while (1) { + if (l[i].type == NAME_STRING) { + acpigen_emit_simple_namestring(l[i].name); + acpigen_emit_byte(l[i].bits); + current_bit_pos += l[i].bits; + } else if (l[i].type == OFFSET) { + acpigen_write_field_offset(l[i].bits, current_bit_pos); + current_bit_pos = l[i].bits; + } else if (l[i].type == FIELD_TYPE_MAX) { + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", + __func__, l[i].type); + break; + } + i++; + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 7c15a31..db2c1a2 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -53,6 +53,8 @@ enum { EXT_OP_PREFIX = 0x5B, SLEEP_OP = 0x22, DEBUG_OP = 0x31, + OPREGION_OP = 0x80, + FIELD_OP = 0x81, DEVICE_OP = 0x82, PROCESSOR_OP = 0x83, POWER_RES_OP = 0x84, @@ -84,6 +86,69 @@ enum { ONES_OP = 0xFF, }; +#define FIELDLIST_OFFSET(X) { .type = OFFSET, \ + .name = "",\ + .bits = X * 8, \ + } +#define FIELDLIST_NAMESTR(X, Y) { .type = NAME_STRING, \ + .name = X, \ + .bits = Y, \ + } + +#define FIELDLIST_END { .type = FIELD_TYPE_MAX,\ + .name = "", \ + .bits = 0, \ + } + +#define FIELD_ANYACC 0 +#define FIELD_BYTEACC 1 +#define FIELD_WORDACC 2 +#define FIELD_DWORDACC 3 +#define FIELD_QWORDACC 4 +#define FIELD_BUFFERACC 5 +#define FIELD_NOLOCK (0<<4) +#define FIELD_LOCK (1<<4) +#define FIELD_PRESERVE (0<<5) +#define FIELD_WRITEASONES (1<<5) +#define FIELD_WRITEASZEROS (2<<5) + +enum field_type { + OFFSET, + NAME_STRING, + FIELD_TYPE_MAX, +}; + +struct fieldlist { + enum field_type type; + const char *name; + u32 bits; +}; + +#define OPREGION(rname, space, offset, len) {.name = rname, \ + .regionspace = space, \ + .regionoffset = offset, \ + .regionlen = len, \ + } + +enum region_space { + SYSTEMMEMORY, + SYSTEMIO, + PCI_CONFIG, + EMBEDDEDCONTROL, + SMBUS, + CMOS, + PCIBARTARGET, + IPMI, + REGION_SPACE_MAX, +}; + +struct opregion { + const char *name; + enum region_space regionspace; + unsigned long regionoffset; + unsigned long regionlen; +}; + void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); @@ -176,6 +241,8 @@ void acpigen_write_return_byte(uint8_t arg); void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), size_t count, void *arg); +void acpigen_write_opregion(struct opregion *opreg); +void acpigen_write_field(const char *name, struct fieldlist *l, u8 field); int get_cst_entries(acpi_cstate_t **); /*

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New patch to review for coreboot: Enable DMIC-4ch for Reef variant
by Sathyanarayana Nujella 27 Oct '16

27 Oct '16

Sathyanarayana Nujella (sathyanarayana.nujella(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17158 -gerrit commit 7609db864d657115fc0702cfd09ad60a650702f6 Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Wed Oct 26 17:35:39 2016 -0700 Enable DMIC-4ch for Reef variant Update KConfig to include DMIC-4ch BUG=chrome-os-partner:56918 BRANCH=none Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/Kconfig | 1 + src/mainboard/google/reef/variants/baseboard/nhlt.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 33c9a6b..6f67cb1 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -94,6 +94,7 @@ config HEAP_SIZE config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_DMIC_2CH_16B + select NHLT_DMIC_4CH_16B select NHLT_DA7219 select NHLT_MAX98357 diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index ef9ec6c..a27dd77 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -20,10 +20,13 @@ void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) { - /* 2 Channel DMIC array. */ + /* 2 & 4 Channel DMIC array. */ if (!nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + if (!nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Added 4CH DMIC array.\n"); + /* Dialog for Headset codec. * Headset codec is bi-directional but uses the same configuration * settings for render and capture endpoints.

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New patch to review for coreboot: Increase HEAP_SIZE
by Sathyanarayana Nujella 27 Oct '16

27 Oct '16

Sathyanarayana Nujella (sathyanarayana.nujella(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17157 -gerrit commit b3d59bb2a358347462679279e6f09540dc71ea08 Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Wed Oct 26 17:38:49 2016 -0700 Increase HEAP_SIZE When DMIC-4ch is enabled, out of memory error is happening. Increase HEAP_SIZE to avoid this error BUG=chrome-os-partner:56918 BRANCH=none Change-Id: Ic910f169f7ef4bb746cb273e276428713a884227 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 6045f47..33c9a6b 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -87,6 +87,10 @@ config UART_FOR_CONSOLE int default 2 +config HEAP_SIZE + hex + default 0x8000 + config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_DMIC_2CH_16B

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New patch to review for coreboot: Add support for DMIC-4ch in apollolake
by Sathyanarayana Nujella 27 Oct '16

27 Oct '16

Sathyanarayana Nujella (sathyanarayana.nujella(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17156 -gerrit commit 47cf9cf54f6622a17b38258de4d40d8f7e08587b Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Wed Oct 26 17:31:36 2016 -0700 Add support for DMIC-4ch in apollolake BUG=chrome-os-partner:56918 BRANCH=none Change-Id: If630ed53bb2cf00ccc441eb062b2e8c650d3cf01 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 7 +++++ src/soc/intel/apollolake/Makefile.inc | 5 ++++ src/soc/intel/apollolake/nhlt.c | 49 ++++++++++++++++++++++++++++++----- 3 files changed, 54 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 187214a..7daeff6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -217,6 +217,13 @@ config NHLT_DMIC_2CH_16B help Include DSP firmware settings for 2 channel 16B DMIC array. +config NHLT_DMIC_4CH_16B + bool + depends on ACPI_NHLT + default n + help + Include DSP firmware settings for 4 channel 16B DMIC array. + config NHLT_MAX98357 bool depends on ACPI_NHLT diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4f867e1..79d1d28 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -125,6 +125,7 @@ endif # DSP firmware settings files. NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin @@ -132,6 +133,10 @@ cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-type := raw +cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-type := raw + cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) $(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) $(MAX98357_RENDER)-type := raw diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c index 3670a13..7bd2205 100644 --- a/src/soc/intel/apollolake/nhlt.c +++ b/src/soc/intel/apollolake/nhlt.c @@ -50,6 +50,38 @@ static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { }, }; +static const struct nhlt_format_config dmic_4ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 4, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-4ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_dmic_array_config dmic_4ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED, +}; + +static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_4ch_mic_config, + .cfg_size = sizeof(dmic_4ch_mic_config), + .formats = dmic_4ch_formats, + .num_formats = ARRAY_SIZE(dmic_4ch_formats), + }, +}; + static const struct nhlt_format_config da7219_formats[] = { /* 48 KHz 24-bits per sample. */ { @@ -118,13 +150,16 @@ static const struct nhlt_endp_descriptor max98357_descriptors[] = { int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) { - if (num_channels != 2) { - printk(BIOS_ERR, "APL only supports 2CH DMIC array.\n"); - return -1; - } - - return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, - ARRAY_SIZE(dmic_2ch_descriptors)); + switch (num_channels) { + case 2: + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); + case 4: + return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, + ARRAY_SIZE(dmic_4ch_descriptors)); + default: + return -1; + } } int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink)

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Patch set updated for coreboot: cpu/intel/model_1067x: Select LAPIC_UDELAY
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17153 -gerrit commit 290c2d1ab1ae2c4f62084b2733428d6853b7027c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:30:07 2016 +0200 cpu/intel/model_1067x: Select LAPIC_UDELAY Change-Id: I51cf4f35bf2ea95c8c19ab885e6308535314b0af Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/model_1067x/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index da8ddc5..12f04cc 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -6,5 +6,6 @@ config CPU_INTEL_MODEL_1067X select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 +# select UDELAY_LAPIC select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS

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Patch set updated for coreboot: gm45/raminit.c: Use LAPIC udelay instead of custom version
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17152 -gerrit commit e41fdf9d4e6fd83b72b055771bcbbf30e59da597 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:31:41 2016 +0200 gm45/raminit.c: Use LAPIC udelay instead of custom version This change may slow down the raminit by maximum 200usec, but reuses the the lapic udelay definition. Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/gm45/Makefile.inc | 1 - src/northbridge/intel/gm45/delay.c | 10 ---------- src/northbridge/intel/gm45/delay.h | 24 ------------------------ src/northbridge/intel/gm45/raminit.c | 8 ++++---- 5 files changed, 4 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index d254b9e..6ee6558 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI - select UDELAY_TSC config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 794b2b9..ac5810b 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y) romstage-y += early_init.c romstage-y += early_reset.c -romstage-y += delay.c romstage-y += raminit.c romstage-y += raminit_rcomp_calibration.c romstage-y += raminit_receive_enable_calibration.c diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index ad2e543..328c751 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -84,13 +84,3 @@ void udelay(const u32 us) { _udelay(us, 1, 0); } - -void ns100delay(const u32 ns100) -{ - _udelay(ns100, 10, 0); -} - -void udelay_from_reset(const u32 us) -{ - _udelay(us, 1, 1); -} diff --git a/src/northbridge/intel/gm45/delay.h b/src/northbridge/intel/gm45/delay.h deleted file mode 100644 index d84c5fb..0000000 --- a/src/northbridge/intel/gm45/delay.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__ -#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ - -#include <delay.h> - -void ns100delay(u32); -void udelay_from_reset(u32); - -#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */ diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 37b44cc..167ef24 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -24,7 +24,7 @@ #include <spd.h> #include <console/console.h> #include <lib.h> -#include "delay.h" +#include <delay.h> #include "gm45.h" #include "chip.h" @@ -916,15 +916,15 @@ static void rcomp_initialization(const stepping_t stepping, const int sff) static void dram_powerup(const int resume) { - udelay_from_reset(200); + udelay(200); MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21); if (!resume) { MCHBAR32(0x1434) |= (1 << 10); - ns100delay(2); + udelay(1); } MCHBAR32(0x1434) |= (1 << 6); if (!resume) { - ns100delay(1); + udelay(1); MCHBAR32(0x1434) |= (1 << 9); MCHBAR32(0x1434) &= ~(1 << 10); udelay(500);

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Patch set updated for coreboot: mb/lenovo/t400: use socket mPGA478MN instead of BGA945
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17155 -gerrit commit 562a02b789e85e59758b064f5f8ab97745fe769d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:36:02 2016 +0200 mb/lenovo/t400: use socket mPGA478MN instead of BGA945 The T400 features a socket P (mPGA478MN) and could potentially support model_6fx CPUs. Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/Kconfig | 2 +- src/mainboard/lenovo/t400/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 194e38c..47e7688 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_BGA956 + select CPU_INTEL_SOCKET_MPGA478MN select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 6bf25fa..867d7797 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/gm45 register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on - chip cpu/intel/socket_BGA956 + chip cpu/intel/socket_mPGA478MN device lapic 0 on end end chip cpu/intel/model_1067x

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Patch set updated for coreboot: cpu/intel/socket_mPGA478MN: Add socket P
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17154 -gerrit commit 5203287b1ada7ebf1aac32695e4df39d2c5947ba Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 00:34:18 2016 +0200 cpu/intel/socket_mPGA478MN: Add socket P This mobile CPU socket supports model_6fx and model_1067x. Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_mPGA478MN/Kconfig | 18 ++++++++++++++++++ src/cpu/intel/socket_mPGA478MN/Makefile.inc | 14 ++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 806a08e..5df8002 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -31,6 +31,7 @@ source src/cpu/intel/socket_FCBGA559/Kconfig source src/cpu/intel/socket_mFCBGA479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig +source src/cpu/intel/socket_mPGA478MN/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 536b40e..1874075 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig new file mode 100644 index 0000000..7c4dbc5 --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Kconfig @@ -0,0 +1,18 @@ +config CPU_INTEL_SOCKET_MPGA478MN + bool + select CPU_INTEL_MODEL_1067X + select CPU_INTEL_MODEL_6FX + select MMX + select SSE + +if CPU_INTEL_SOCKET_MPGA478MN + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc new file mode 100644 index 0000000..fe6509b --- /dev/null +++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc @@ -0,0 +1,14 @@ +subdirt-y += ../model_6fx +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +romstage-y += ../car/romstage.c

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coreboot-gerrit October 2016