coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

Patch set updated for coreboot: drivers/intel/fsp2_0: Allow use of MRC cache data in recovery
by Andrey Petrov 27 Oct '16

27 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17165 -gerrit commit 8dc96256bb9d132cd7301c95bafe8050000c49c0 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 27 10:12:22 2016 -0700 drivers/intel/fsp2_0: Allow use of MRC cache data in recovery Add a configuration option to allow using MRC cache in recovery boot, off by default. This can be overridden by Chrome EC if it requests retrain. BUG=chrome-os-partner:56643 BRANCH=none TEST=invoke power-alt-refresh key combination, notice memory is retrained in recovery Change-Id: I31a87afc8a70c17e488c06e42da4acbb2dde3f5d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +++++++ src/drivers/intel/fsp2_0/memory_init.c | 9 +++++++-- src/soc/intel/apollolake/Kconfig | 4 ++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index c653148..75e3901 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -94,4 +94,11 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n +config FSP_RECOVERY_USE_MRCCACHE + bool "Use MRC cache in recovery boot" + depends on CACHE_MRC_SETTINGS + default n + help + Select yes if you want recovery boot to use MRC cache. + endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0a22ce..70379c3 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -113,12 +113,17 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - /* Don't use saved training data when recovery mode is enabled. */ - if (vboot_recovery_mode_enabled()) { + if (!IS_ENABLED(CONFIG_FSP_RECOVERY_USE_MRCCACHE)) { printk(BIOS_SPEW, "Recovery mode. Not using MRC cache.\n"); return; } + /* If recovery with full retrain is requested do not load cache */ + if (vboot_recovery_mode_memory_retrain()) { + printk(BIOS_SPEW, "Recovery with forced memory retrain.\n"); + return; + } + if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { printk(BIOS_SPEW, "MRC cache was not found\n"); return; diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 187214a..b6fbcb4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -260,4 +260,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config CONFIG_FSP_RECOVERY_USE_MRCCACHE + bool + default y + endif

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Patch set updated for coreboot: vboot: Add recovery mode with full memory retrain
by Andrey Petrov 27 Oct '16

27 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17164 -gerrit commit df9f9c4d2252be33e0cbe61224b6622d67d350eb Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 27 10:11:18 2016 -0700 vboot: Add recovery mode with full memory retrain BUG=chrome-os-partner:56643 BRANCH=none TEST=invoke power-alt-refresh key combination, notice memory is retrained in recovery Change-Id: I2f6ff7eac5f6c7af198cd1a43902cdd9ca6e66c0 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/vboot/bootmode.c | 7 +++++++ src/vboot/vboot_common.h | 1 + 2 files changed, 8 insertions(+) diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c index 12a4dc0..c851c72 100644 --- a/src/vboot/bootmode.c +++ b/src/vboot/bootmode.c @@ -22,6 +22,7 @@ #include <vboot/misc.h> #include <vboot/vbnv.h> #include <vboot/vboot_common.h> +#include <ec/google/chromeec/ec.h> static int vb2_get_recovery_reason_shared_data(void) { @@ -162,6 +163,12 @@ int vboot_recovery_mode_enabled(void) return !!vboot_check_recovery_request(); } +int vboot_recovery_mode_memory_retrain(void) +{ + return !!((google_chromeec_get_switches() & + EC_SWITCH_RECOVERY_MEM_RETRAIN)); +} + int vboot_developer_mode_enabled(void) { if (!IS_ENABLED(CONFIG_VBOOT)) diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index 59fd44c..956b54c 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -107,5 +107,6 @@ void verstage_mainboard_init(void); /* Check boot modes */ int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); +int vboot_recovery_mode_memory_retrain(void); #endif /* __VBOOT_VBOOT_COMMON_H__ */

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Patch set updated for coreboot: ec/google/chromeec: Add new recovery mode switch
by Andrey Petrov 27 Oct '16

27 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17166 -gerrit commit 4e41e539484447f9221f9a298f15ef7f021e3768 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 27 10:13:11 2016 -0700 ec/google/chromeec: Add new recovery mode switch BUG=chrome-os-partner:56643 BRANCH=none TEST=invoke power-alt-refresh key combination, notice memory is retrained in recovery Change-Id: I3e95e3b1a84cacfc107de65eea5778c385523d3e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/ec/google/chromeec/ec_commands.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4a551c2..edba259 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -185,6 +185,8 @@ #define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ #define EC_SWITCH_IGNORE0 0x20 +/* Recovery requested with full memory retrain */ +#define EC_SWITCH_RECOVERY_MEM_RETRAIN 0x40 /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */

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New patch to review for coreboot: soc/apollolake: Add soc core init
by Ravishankar Sarawadi 27 Oct '16

27 Oct '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17168 -gerrit commit ce7c89f4f2121e3697210c505a8fb71f3a48c9a8 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Fri Sep 9 14:08:50 2016 -0700 soc/apollolake: Add soc core init Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926 --- src/soc/intel/apollolake/cpu.c | 23 ++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/cpu.h | 13 +++++++++++++ src/soc/intel/apollolake/include/soc/iomap.h | 7 ++++++- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e67842c..bd5cff5 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,11 +25,32 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <reg_script.h> #include <soc/cpu.h> +#include <soc/iomap.h> #include <soc/smm.h> +static const struct reg_script core_msr_script[] = { + /* Enable C-state and IO/MWAIT redirect */ + REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, + (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK + | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), + /* Power Management I/O base address for I/O trapping to C-states */ + REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, + (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_SCRIPT_END +}; + +static void soc_core_init(device_t cpu) +{ + /* Set core MSRs */ + reg_script_run(core_msr_script); +} + static struct device_operations cpu_dev_ops = { - .init = DEVICE_NOOP, + .init = soc_core_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index bffe4bc..e94972d 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -54,6 +54,19 @@ void apollolake_init_cpus(struct device *dev); */ #define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK 0x400 +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK 0x8000 + +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_POWER_CTL 0x1fc + #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 621b0a6..d5d8f87 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -27,7 +27,12 @@ #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 -#define R_ACPI_PM1_TMR 0x8 +#define R_ACPI_PM1_TMR 0x8 + +/* CST Range (R/W) IO port block size */ +#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 +/* ACPI PMIO Offset to C-state register*/ +#define ACPI_PMIO_CST_REG (ACPI_PMIO_BASE + 0x14) /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000

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New patch to review for coreboot: mainboard/google/reef: allow variants to override NHLT OEM strings
by Aaron Durbin 27 Oct '16

27 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17167 -gerrit commit 6a917a75a65fd61164e0694f57106363129a58b2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 27 13:24:06 2016 -0500 mainboard/google/reef: allow variants to override NHLT OEM strings In certain cases a board variant may need to override the NHLT OEM strings in the main NHLT table. Therefore, provide that path. BUG=chrome-os-partner:56918 Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/mainboard.c | 11 ++++++++++- .../reef/variants/baseboard/include/baseboard/variants.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 3f23a77..4d4ef53 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -41,12 +41,19 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +void __attribute__((weak)) variant_nhlt_oem_strings(const char **oem_id, + const char **oem_table_id) +{ +} + static unsigned long mainboard_write_acpi_tables( device_t device, unsigned long current, acpi_rsdp_t *rsdp) { uintptr_t start_addr; uintptr_t end_addr; struct nhlt *nhlt; + const char *oem_id = NULL; + const char *oem_table_id = NULL; start_addr = current; @@ -56,8 +63,10 @@ static unsigned long mainboard_write_acpi_tables( return start_addr; variant_nhlt_init(nhlt); + variant_nhlt_oem_strings(&oem_id, &oem_table_id); - end_addr = nhlt_soc_serialize(nhlt, start_addr); + end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, + oem_id, oem_table_id); if (end_addr != start_addr) acpi_add_table(rsdp, (void *)start_addr); diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index 9f2ed06..31ee3d0 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -42,6 +42,8 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); /* Seed the NHLT tables with the board specific information. */ struct nhlt; +void variant_nhlt_oem_strings(const char **oem_id, + const char **oem_table_id); void variant_nhlt_init(struct nhlt *nhlt); #endif /* BASEBOARD_VARIANTS_H */

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New patch to review for coreboot: ec/google/chromeec: Add new recovery mode switch
by Andrey Petrov 27 Oct '16

27 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17166 -gerrit commit c99b4bc51c4596c886cde7995719d8ea66c7da1e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 27 10:13:11 2016 -0700 ec/google/chromeec: Add new recovery mode switch BUG=chrome-os-partner:56643 BRANCH=none TEST=invoke power-alt-refresh key combination, notice memory is retrained in recovery Change-Id: I3e95e3b1a84cacfc107de65eea5778c385523d3e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/ec/google/chromeec/ec_commands.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4a551c2..edba259 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -185,6 +185,8 @@ #define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ #define EC_SWITCH_IGNORE0 0x20 +/* Recovery requested with full memory retrain */ +#define EC_SWITCH_RECOVERY_MEM_RETRAIN 0x40 /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */

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New patch to review for coreboot: drivers/intel/fsp2_0: Allow use of MRC cache data in recovery
by Andrey Petrov 27 Oct '16

27 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17165 -gerrit commit bb40003680503b4301d569eff898fc7e6b4fac0f Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 27 10:12:22 2016 -0700 drivers/intel/fsp2_0: Allow use of MRC cache data in recovery Add a configuration option to allow using MRC cache in recovery boot, off by default. This can be overridden by Chrome EC if it requests retrain. BUG=chrome-os-partner:56643 BRANCH=none TEST=invoke power-alt-refresh key combination, notice memory is retrained in recovery Change-Id: I31a87afc8a70c17e488c06e42da4acbb2dde3f5d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +++++++ src/drivers/intel/fsp2_0/memory_init.c | 9 +++++++-- src/soc/intel/apollolake/Kconfig | 4 ++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index c653148..75e3901 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -94,4 +94,11 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n +config FSP_RECOVERY_USE_MRCCACHE + bool "Use MRC cache in recovery boot" + depends on CACHE_MRC_SETTINGS + default n + help + Select yes if you want recovery boot to use MRC cache. + endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0a22ce..70379c3 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -113,12 +113,17 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - /* Don't use saved training data when recovery mode is enabled. */ - if (vboot_recovery_mode_enabled()) { + if (!IS_ENABLED(CONFIG_FSP_RECOVERY_USE_MRCCACHE)) { printk(BIOS_SPEW, "Recovery mode. Not using MRC cache.\n"); return; } + /* If recovery with full retrain is requested do not load cache */ + if (vboot_recovery_mode_memory_retrain()) { + printk(BIOS_SPEW, "Recovery with forced memory retrain.\n"); + return; + } + if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { printk(BIOS_SPEW, "MRC cache was not found\n"); return; diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 187214a..b6fbcb4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -260,4 +260,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config CONFIG_FSP_RECOVERY_USE_MRCCACHE + bool + default y + endif

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New patch to review for coreboot: vboot: Add recovery mode with full memory retrain
by Andrey Petrov 27 Oct '16

27 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17164 -gerrit commit 6841aeb3b8293d8a66531071a71f57ea45babb38 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 27 10:11:18 2016 -0700 vboot: Add recovery mode with full memory retrain BUG=chrome-os-partner:56643 BRANCH=none TEST=invoke power-alt-refresh key combination, notice memory is retrained in recovery Change-Id: I2f6ff7eac5f6c7af198cd1a43902cdd9ca6e66c0 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/vboot/bootmode.c | 6 ++++++ src/vboot/vboot_common.h | 1 + 2 files changed, 7 insertions(+) diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c index 12a4dc0..6637cab 100644 --- a/src/vboot/bootmode.c +++ b/src/vboot/bootmode.c @@ -22,6 +22,7 @@ #include <vboot/misc.h> #include <vboot/vbnv.h> #include <vboot/vboot_common.h> +#include <ec/google/chromeec/ec.h> static int vb2_get_recovery_reason_shared_data(void) { @@ -162,6 +163,11 @@ int vboot_recovery_mode_enabled(void) return !!vboot_check_recovery_request(); } +int vboot_recovery_mode_memory_retrain(void) +{ + return !!((google_chromeec_get_switches() & EC_SWITCH_RECOVERY_MEM_RETRAIN)); +} + int vboot_developer_mode_enabled(void) { if (!IS_ENABLED(CONFIG_VBOOT)) diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index 59fd44c..956b54c 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -107,5 +107,6 @@ void verstage_mainboard_init(void); /* Check boot modes */ int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); +int vboot_recovery_mode_memory_retrain(void); #endif /* __VBOOT_VBOOT_COMMON_H__ */

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New patch to review for coreboot: mainboard/google/reef: update comment for DMIC config usage
by Aaron Durbin 27 Oct '16

27 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17163 -gerrit commit 2498207eab0e0d5dab5094b08fe13ea96d3740f1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 27 12:11:15 2016 -0500 mainboard/google/reef: update comment for DMIC config usage Going forward GPIO_17 is used to determine the configuration of the board w.r.t. the number of DMICs on the board. BUG=chrome-os-partner:56918 Change-Id: I03edb880e0649977030c1b87219ebebac631a519 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 976a504..c9fa3d3 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -289,7 +289,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* 1 vs 4 DMIC config */ PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */

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Patch merged into coreboot/master: Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 46dd467648564a48cd40de8ffb75270197c19f0c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Oct 25 17:11:16 2016 +0200 Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU On QEMU using SeaVGABIOS breaks some bootloaders, e.g. ISOLINUX does not work and GRUB works but is forced in txtmode, instead of graphical mode. Change-Id: If31d4e5ed19cbeed3f8f9dbc23cc738dd55986e5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17122 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17122 for details. -gerrit

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coreboot-gerrit October 2016