coreboot-gerrit October 2016

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New patch to review for coreboot: mainboard/intel/kblrvp: Update gpio.h
by Naresh Solanki 28 Oct '16

28 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17161 -gerrit commit ab4484ef6c0413b00d586820753f62fdbbfb7df1 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Oct 27 20:28:23 2016 +0530 mainboard/intel/kblrvp: Update gpio.h 1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/gpio.h | 240 +++++++++++++----------------- src/mainboard/intel/kblrvp/mainboard.c | 62 -------- src/mainboard/intel/kblrvp/spd/spd.h | 16 +- src/mainboard/intel/kblrvp/spd/spd_util.c | 18 +-- 4 files changed, 110 insertions(+), 226 deletions(-) diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h index 0e03080..5f66f03 100644 --- a/src/mainboard/intel/kblrvp/gpio.h +++ b/src/mainboard/intel/kblrvp/gpio.h @@ -20,183 +20,154 @@ #include <soc/gpe.h> #include <soc/gpio.h> -/* EC in RW */ -#define GPIO_EC_IN_RW GPP_C6 -/* BIOS Flash Write Protect */ -#define GPIO_PCH_WP GPP_C23 - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C13 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_C15 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK -/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ -#define GPE_WLAN_WAKE GPE0_DW0_16 - -/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ -#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 -/* Input device interrupt configuration */ -#define TOUCHPAD_INT_L GPP_B3_IRQ -#define TOUCHSCREEN_INT_L GPP_E7_IRQ -#define MIC_INT_L GPP_F10_IRQ /* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ #define EC_SCI_GPI GPE0_DW2_16 #define EC_SMI_GPI GPP_E15 -/* - * GPP_E3 is AUDIO_DB_ID. - * It is a dual purpose GPIO, used for Audio Daughter - * Board Identification & to control the shutdown mode pin - * of the Maxim amp. - */ -#define AUDIO_DB_ID GPP_E3 -/* SD controller needs additional card detect GPIO to support RTD3 */ -#define GPIO_SD_CARD_DETECT GPP_A7 #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), +/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), /* EC_HID_INT */ PAD_CFG_NC(GPP_A11), /* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), /* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* TOUCHPAD WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), -/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0), +/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1), +/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), +/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), +/* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* CLK_REQ_SLOT4 */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* CLK_REQ_SLOT5 */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP), +/* GSPI0_CS# */ /* GPP_B15 */ /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* TBT_CIO */ PAD_CFG_NC(GPP_B17), +/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES), +/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), -/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), -/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), -/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), -/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), -/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), -/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), -/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), +/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), +/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), +/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), -/* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), +/* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP), +/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), +/* SATA_DEVSLP2 */ /* GPP_E6 */ /* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), +/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -208,7 +179,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), +/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -218,24 +189,23 @@ static const struct pad_config gpio_table[] = { /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* GPD7 */ PAD_CFG_NC(GPD7), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index fe4fb3a..cd6c3f9 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -26,73 +26,12 @@ #include "ec.h" #include "gpio.h" -static const char *oem_id_maxim = "INTEL"; -static const char *oem_table_id_maxim = "SCRDMAX"; - static void mainboard_init(device_t dev) { if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); } -static uint8_t select_audio_codec(void) -{ - int audio_db_sel = gpio_get(AUDIO_DB_ID); - - return audio_db_sel; -} - -static unsigned long mainboard_write_acpi_tables( - device_t device, unsigned long current, acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - const char *oem_id = NULL; - const char *oem_table_id = NULL; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - /* 2 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - - - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); - - if (select_audio_codec()) { - /* ADI Smart Amps for left and right. */ - if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) - printk(BIOS_ERR, "Couldn't add ssm4567.\n"); - } else { - /* MAXIM Smart Amps for left and right. */ - if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) - printk(BIOS_ERR, "Couldn't add max98357.\n"); - - oem_id = oem_id_maxim; - oem_table_id = oem_table_id_maxim; - } - - /* NAU88l25 Headset codec. */ - if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Couldn't add headset codec.\n"); - - end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, - oem_id, oem_table_id); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - /* * mainboard_enable is executed as first thing after * enumerate_buses(). @@ -100,7 +39,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index e04d13c..065df7b 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -38,22 +38,8 @@ #define SAMSUNG_SINGLE_CHAN 0x4 #define MIC_SINGLE_CHAN 0x5 -/* PCH_MEM_CFG[3:0] */ -#define MAX_MEMORY_CONFIG 0x10 #define RCOMP_TARGET_PARAMS 0x5 -#define K4E6E304EE_MEM_ID 0x3 - -static inline int get_spd_index(void) -{ - /* PCH_MEM_CFG[3:0] */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} + void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index fc0581c..f29f1e33 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -54,22 +54,12 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { int mem_cfg_id; - mem_cfg_id = get_spd_index(); + mem_cfg_id = 0; /* Rcomp target */ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { 100, 40, 40, 23, 40 }; - /* Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF */ - static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 40, 21, 40 }; - - - if (mem_cfg_id == K4E6E304EE_MEM_ID) { - memcpy(rcomp_strength_ptr, StrengthendRcompTarget, - sizeof(StrengthendRcompTarget)); - } else { - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); - } + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } @@ -79,7 +69,7 @@ uintptr_t mainboard_get_spd_data(void) int spd_index, spd_span; size_t spd_file_len; - spd_index = get_spd_index(); + spd_index = 0; printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ @@ -106,7 +96,7 @@ int mainboard_has_dual_channel_mem(void) { int spd_index; - spd_index = get_spd_index(); + spd_index = 0; if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN && spd_index != MIC_SINGLE_CHAN) {

1 0

New patch to review for coreboot: nb/intel/i945/gma.c: Homogenize code for PCI IDs.
by HAOUAS Elyes 28 Oct '16

28 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17174 -gerrit commit 01fd0064767608b62af2b681b5d0637938a6be8a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 28 10:56:59 2016 +0200 nb/intel/i945/gma.c: Homogenize code for PCI IDs. Change-Id: Ic01565cb730c49a5fe77c8f4990276970964f101 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/gma.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index aefec8f..d64fca7 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -748,16 +748,26 @@ static struct device_operations gma_func1_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 }; +static const unsigned short i945_gma_func0_ids[] = { + 0x2772, + 0x27a2, + 0x27ae, + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x27a6, + 0 +}; static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, };

1 0

New patch to review for coreboot: sb/nvidia/mcp55: Remove whitespace
by HAOUAS Elyes 28 Oct '16

28 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17173 -gerrit commit 25d7a30dd45ce80c5f9a000f995e709be0e2afa6 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 28 10:18:04 2016 +0200 sb/nvidia/mcp55: Remove whitespace Change-Id: Id35803b9fe22375ac0e0d11ae0f1e9b2f3795b0d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/nvidia/mcp55/early_setup_car.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 7f1d03b..c98c28a 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -150,7 +150,8 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) { - static const unsigned int ctrl_conf_1[] = { + +static const unsigned int ctrl_conf_1[] = { RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000, RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200, @@ -197,9 +198,9 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ - }; +}; - static const unsigned int ctrl_conf_1_1[] = { +static const unsigned int ctrl_conf_1_1[] = { RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003, RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001, @@ -209,9 +210,9 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A, RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000, RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, - }; +}; - static const unsigned int ctrl_conf_mcp55_only[] = { +static const unsigned int ctrl_conf_mcp55_only[] = { RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000, @@ -265,16 +266,16 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2), #endif - }; +}; - static const unsigned int ctrl_conf_master_only[] = { +static const unsigned int ctrl_conf_master_only[] = { RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000, /* Master MCP55???? YHLU */ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2), - }; +}; - static const unsigned int ctrl_conf_2[] = { +static const unsigned int ctrl_conf_2[] = { /* I didn't put PCI-E related stuff here. */ RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0, @@ -290,7 +291,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #endif - }; +}; int j, i;

1 0

Patch set updated for coreboot: nb/amd/amdmct/mct: Remove commented code
by HAOUAS Elyes 28 Oct '16

28 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17172 -gerrit commit d8d51efe6cb8fe73e775049985cae178969f0df7 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 28 09:56:29 2016 +0200 nb/amd/amdmct/mct: Remove commented code Change-Id: Id0c62cebfceaf083f1bb39514b06b32c55128b85 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdmct/mct/mct_d.c | 8 -------- src/northbridge/amd/amdmct/mct/mctardk4.c | 3 --- src/northbridge/amd/amdmct/mct/mctcsi_d.c | 2 -- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 2 -- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 1 - src/northbridge/amd/amdmct/mct/mctsrc2p.c | 7 +------ 6 files changed, 1 insertion(+), 22 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index d3ae2a3..62fc626 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1356,7 +1356,6 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, val |= dword; Set_NB32(dev, reg, val); } -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); print_tx("AutoCycTiming: Status ", pDCTstat->Status); print_tx("AutoCycTiming: ErrStatus ", pDCTstat->ErrStatus); @@ -1723,8 +1722,6 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, mct_EarlyArbEn_D(pMCTstat, pDCTstat); mctHookAfterAutoCfg(); -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("AutoConfig: Status ", pDCTstat->Status); print_tx("AutoConfig: ErrStatus ", pDCTstat->ErrStatus); print_tx("AutoConfig: ErrCode ", pDCTstat->ErrCode); @@ -1858,8 +1855,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, reg = 0x80 + reg_off; /* Bank Addressing Register */ Set_NB32(dev, reg, BankAddrReg); -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("SPDSetBanks: Status ", pDCTstat->Status); print_tx("SPDSetBanks: ErrStatus ", pDCTstat->ErrStatus); print_tx("SPDSetBanks: ErrCode ", pDCTstat->ErrCode); @@ -2035,8 +2030,6 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, mct_AfterStitchMemory(pMCTstat, pDCTstat, dct); } -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("StitchMemory: Status ", pDCTstat->Status); print_tx("StitchMemory: ErrStatus ", pDCTstat->ErrStatus); print_tx("StitchMemory: ErrCode ", pDCTstat->ErrCode); @@ -2399,7 +2392,6 @@ static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i) u8 *p; p = pDCTstat->DIMMAddr; - //mct_BeforeGetDIMMAddress(); return p[i]; } diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 7e1d91a..8815943 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -30,9 +30,6 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), &pDCTstat->_2Tmode); -// print_tx("1 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); -// print_tx("1 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); - if (pDCTstat->MAdimms[dct] == 1) pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ else diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index 4841b73..1c86239 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -132,8 +132,6 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, print_t("InterleaveBanks_D: Banks Interleaved "); } /* DoIntlv */ -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("InterleaveBanks_D: Status ", pDCTstat->Status); print_tx("InterleaveBanks_D: ErrStatus ", pDCTstat->ErrStatus); print_tx("InterleaveBanks_D: ErrCode ", pDCTstat->ErrCode); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index e0c7761..6363162 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -437,8 +437,6 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, u8 dqsDelay_end; u8 tmp, valid; -// print_tx("TrainDQSPos: Node_ID", pDCTstat->Node_ID); -// print_tx("TrainDQSPos: Direction", pDCTstat->Direction); /* MutualCSPassW: each byte represents a bitmap of pass/fail per * ByteLane. The indext within MutualCSPassW is the delay value diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index c1b1133..bfd103b 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -61,7 +61,6 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, p[i] = val; } -// pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel); return MaxValue; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index c7c92ac..7454f53 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -60,12 +60,9 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; -// print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel); -// print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver); + for (i = 0; i < bn; i++) { val = p[i]; -// print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); -// print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); if (val > max) { max = val; } @@ -123,9 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ - //val += Pass1MemClkDly; val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES - //val += 0x02; p[i] = val; pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); }

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New patch to review for coreboot: nb/amd/amdmct/mct: Remove commented code
by HAOUAS Elyes 28 Oct '16

28 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17172 -gerrit commit 18b0b965e29c575c9bab495d802cc5d622d7e75b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 28 09:56:29 2016 +0200 nb/amd/amdmct/mct: Remove commented code Change-Id: Id0c62cebfceaf083f1bb39514b06b32c55128b85 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- 3rdparty/blobs | 2 +- 3rdparty/vboot | 2 +- src/northbridge/amd/amdmct/mct/mct_d.c | 8 -------- src/northbridge/amd/amdmct/mct/mctardk4.c | 3 --- src/northbridge/amd/amdmct/mct/mctcsi_d.c | 2 -- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 2 -- src/northbridge/amd/amdmct/mct/mctsrc1p.c | 1 - src/northbridge/amd/amdmct/mct/mctsrc2p.c | 7 +------ 8 files changed, 3 insertions(+), 24 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8ad2d63..b0eeddd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8ad2d6385652e14b6f0d35ab9b474c31ddeb1773 +Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2 diff --git a/3rdparty/vboot b/3rdparty/vboot index ea72ee4..46b77fb 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit ea72ee454aea5e0f378275fe7114cf683b7db938 +Subproject commit 46b77fb2f04941c869c3a98cd17e9209c36b2917 diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index d3ae2a3..62fc626 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1356,7 +1356,6 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, val |= dword; Set_NB32(dev, reg, val); } -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); print_tx("AutoCycTiming: Status ", pDCTstat->Status); print_tx("AutoCycTiming: ErrStatus ", pDCTstat->ErrStatus); @@ -1723,8 +1722,6 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, mct_EarlyArbEn_D(pMCTstat, pDCTstat); mctHookAfterAutoCfg(); -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("AutoConfig: Status ", pDCTstat->Status); print_tx("AutoConfig: ErrStatus ", pDCTstat->ErrStatus); print_tx("AutoConfig: ErrCode ", pDCTstat->ErrCode); @@ -1858,8 +1855,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, reg = 0x80 + reg_off; /* Bank Addressing Register */ Set_NB32(dev, reg, BankAddrReg); -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("SPDSetBanks: Status ", pDCTstat->Status); print_tx("SPDSetBanks: ErrStatus ", pDCTstat->ErrStatus); print_tx("SPDSetBanks: ErrCode ", pDCTstat->ErrCode); @@ -2035,8 +2030,6 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, mct_AfterStitchMemory(pMCTstat, pDCTstat, dct); } -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("StitchMemory: Status ", pDCTstat->Status); print_tx("StitchMemory: ErrStatus ", pDCTstat->ErrStatus); print_tx("StitchMemory: ErrCode ", pDCTstat->ErrCode); @@ -2399,7 +2392,6 @@ static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i) u8 *p; p = pDCTstat->DIMMAddr; - //mct_BeforeGetDIMMAddress(); return p[i]; } diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 7e1d91a..8815943 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -30,9 +30,6 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), &pDCTstat->_2Tmode); -// print_tx("1 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); -// print_tx("1 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); - if (pDCTstat->MAdimms[dct] == 1) pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ else diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index 4841b73..1c86239 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -132,8 +132,6 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, print_t("InterleaveBanks_D: Banks Interleaved "); } /* DoIntlv */ -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("InterleaveBanks_D: Status ", pDCTstat->Status); print_tx("InterleaveBanks_D: ErrStatus ", pDCTstat->ErrStatus); print_tx("InterleaveBanks_D: ErrCode ", pDCTstat->ErrCode); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index e0c7761..6363162 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -437,8 +437,6 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, u8 dqsDelay_end; u8 tmp, valid; -// print_tx("TrainDQSPos: Node_ID", pDCTstat->Node_ID); -// print_tx("TrainDQSPos: Direction", pDCTstat->Direction); /* MutualCSPassW: each byte represents a bitmap of pass/fail per * ByteLane. The indext within MutualCSPassW is the delay value diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index c1b1133..bfd103b 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -61,7 +61,6 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, p[i] = val; } -// pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel); return MaxValue; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index c7c92ac..7454f53 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -60,12 +60,9 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; -// print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel); -// print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver); + for (i = 0; i < bn; i++) { val = p[i]; -// print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); -// print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); if (val > max) { max = val; } @@ -123,9 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ - //val += Pass1MemClkDly; val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES - //val += 0x02; p[i] = val; pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); }

1 0

Patch set updated for coreboot: riscv: add the lowrisc/nexys4ddr mainboard
by Ronald G. Minnich 28 Oct '16

28 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17132 -gerrit commit 561fab6f267f9f3589bbf08ca690bd529d9f6b61 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Oct 25 19:11:07 2016 -0700 riscv: add the lowrisc/nexys4ddr mainboard This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/lowrisc/Kconfig | 16 ++++ src/mainboard/lowrisc/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Kconfig | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Makefile.inc | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/board_info.txt | 3 + src/mainboard/lowrisc/nexys4ddr/devicetree.cb | 20 +++++ src/mainboard/lowrisc/nexys4ddr/mainboard.c | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 31 ++++++++ src/mainboard/lowrisc/nexys4ddr/rom_media.c | 30 +++++++ src/mainboard/lowrisc/nexys4ddr/romstage.c | 47 +++++++++++ src/mainboard/lowrisc/nexys4ddr/uart.c | 40 ++++++++++ src/mainboard/lowrisc/nexys4ddr/util.c | 103 +++++++++++++++++++++++++ 13 files changed, 398 insertions(+) diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig new file mode 100644 index 0000000..ba0fbe7 --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LOWRISC + +choice + prompt "Mainboard model" + +source "src/mainboard/lowrisc/*/Kconfig.name" + +endchoice + +source "src/mainboard/lowrisc/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "lowrisc" + +endif # VENDOR_LOWRISC diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name new file mode 100644 index 0000000..4c992fc --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LOWRISC + bool "lowrisc" diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig new file mode 100644 index 0000000..f0a3637 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_LOWRISC_NEXYS4DDR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_LOWRISC_LOWRISC + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_UART_8250MEM + select BOOT_DEVICE_NOT_SPI_FLASH + select UART_OVERRIDE_REFCLK + select UART_OVERRIDE_INPUT_CLOCK_DIVIDER + +config MAINBOARD_DIR + string + default lowrisc/nexys4ddr + +config MAINBOARD_PART_NUMBER + string + default "LOWRISC NEXYS4DDR" + +config MAX_CPUS + int + default 1 + +endif # BOARD_LOWRISC_NEXYS4DDR diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name new file mode 100644 index 0000000..f99b3cc --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LOWRISC_NEXYS4DDR + bool "nexys4ddr" diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc new file mode 100644 index 0000000..69519b1 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +bootblock-y += uart.c +bootblock-y += util.c +bootblock-y += rom_media.c +romstage-y += romstage.c +romstage-y += uart.c +romstage-y += util.c +romstage-y += rom_media.c +ramstage-y += uart.c +ramstage-y += util.c +ramstage-y += rom_media.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt new file mode 100644 index 0000000..b5ba419 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/board_info.txt @@ -0,0 +1,3 @@ +Board name: lowrisc nexys4ddr +Category: eval +Board URL: "Tutorial for the debug preview of lowrisc" in a search engine diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb new file mode 100644 index 0000000..e857276 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c new file mode 100644 index 0000000..1ceb97d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> +#include <symbols.h> + +static void mainboard_enable(device_t dev) +{ + /* + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; + + if (!dev) + die("No dev0; die\n"); + + ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size / KiB); + + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld new file mode 100644 index 0000000..0348c47 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +#define START 0x80000000 + +SECTIONS +{ + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + PAGETABLES(START + 8M + 200K, 56K) + RAMSTAGE(START + 8M + 256K, 256K) +} diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c new file mode 100644 index 0000000..7d4ed00 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> +#include <symbols.h> + +/* + * _dram is the start of RAM. We currently need to load coreboot.rom into + * RAM. The actual "rom" code on the FPGAs is in a block ram. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c new file mode 100644 index 0000000..411c851 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <console/console.h> + +void main(void) +{ + // You currently can not call console_init from romstage. As + // best I can tell, it brings in in COREBOOT_EXTRA_VERSION, + // which is in .data, and we get a linker warning. I suspect + // the best fix is to have all the declarations in + // src/lib/version.c set up to be in the .text or .rodata + // section but that's a problem for another day. At some point + // we'd like to call console_init here. + // + // The actual error is this: + // LINK cbfs/fallback/romstage.debug + // /home/rminnich/projects/riscv/coreboot/util/crossgcc/ + // xgcc/bin/riscv64-elf-ld.bfd: + // build/cbfs/fallback/romstage.debug: warning: + // allocated section `.data' not in segment + // OBJCOPY cbfs/fallback/romstage.elf + // /home/rminnich/projects/riscv/coreboot/util/crossgcc/ + // xgcc/bin/riscv64-elf-objcopy: + // build/cbfs/fallback/stVkYAzb: warning: allocated section + // `.data' not in segment + // /home/rminnich/projects/riscv/coreboot/util/crossgcc/ + // xgcc/bin/riscv64-elf-objcopy: + // build/cbfs/fallback/stk7I96a: warning: allocated section + // '.data' not in segment + + // console_init(); + run_ramstage(); +} diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c new file mode 100644 index 0000000..e3c233f80 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/uart.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <spike_util.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t) 0x42000000; +} + +/* these are currently not quite right but they are here for reference + * and will be fixed when lowrisc gives us a standard clock + * and set of values. */ +// divisor = clk_freq / (16 * Baud) +unsigned int uart_input_clock_divider(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) % 0x100; +} + +// System clock 25 MHz, 115200 baud rate +unsigned int uart_platform_refclk(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) >> 8; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c new file mode 100644 index 0000000..32cdb6d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/util.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, + * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING + * LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS + * DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING + * DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS + * IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, + * UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + /* Ensure the other hart sees it. */ + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +}

1 0

Patch set updated for coreboot: riscv: add the lowrisc/nexys4ddr mainboard
by Ronald G. Minnich 28 Oct '16

28 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17132 -gerrit commit 2cfb4ab3b20bb4e43db79b93d2e52e8b224c6e5a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Oct 25 19:11:07 2016 -0700 riscv: add the lowrisc/nexys4ddr mainboard This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far. With the suggested changes this no longer builds so I'm hoping someone can explain them a little better. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/lowrisc/Kconfig | 16 ++++ src/mainboard/lowrisc/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Kconfig | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Makefile.inc | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/board_info.txt | 3 + src/mainboard/lowrisc/nexys4ddr/devicetree.cb | 20 +++++ src/mainboard/lowrisc/nexys4ddr/mainboard.c | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 31 ++++++++ src/mainboard/lowrisc/nexys4ddr/rom_media.c | 30 +++++++ src/mainboard/lowrisc/nexys4ddr/romstage.c | 29 +++++++ src/mainboard/lowrisc/nexys4ddr/uart.c | 40 ++++++++++ src/mainboard/lowrisc/nexys4ddr/util.c | 103 +++++++++++++++++++++++++ 13 files changed, 380 insertions(+) diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig new file mode 100644 index 0000000..ba0fbe7 --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LOWRISC + +choice + prompt "Mainboard model" + +source "src/mainboard/lowrisc/*/Kconfig.name" + +endchoice + +source "src/mainboard/lowrisc/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "lowrisc" + +endif # VENDOR_LOWRISC diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name new file mode 100644 index 0000000..4c992fc --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LOWRISC + bool "lowrisc" diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig new file mode 100644 index 0000000..f0a3637 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_LOWRISC_NEXYS4DDR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_LOWRISC_LOWRISC + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_UART_8250MEM + select BOOT_DEVICE_NOT_SPI_FLASH + select UART_OVERRIDE_REFCLK + select UART_OVERRIDE_INPUT_CLOCK_DIVIDER + +config MAINBOARD_DIR + string + default lowrisc/nexys4ddr + +config MAINBOARD_PART_NUMBER + string + default "LOWRISC NEXYS4DDR" + +config MAX_CPUS + int + default 1 + +endif # BOARD_LOWRISC_NEXYS4DDR diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name new file mode 100644 index 0000000..f99b3cc --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LOWRISC_NEXYS4DDR + bool "nexys4ddr" diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc new file mode 100644 index 0000000..69519b1 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +bootblock-y += uart.c +bootblock-y += util.c +bootblock-y += rom_media.c +romstage-y += romstage.c +romstage-y += uart.c +romstage-y += util.c +romstage-y += rom_media.c +ramstage-y += uart.c +ramstage-y += util.c +ramstage-y += rom_media.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt new file mode 100644 index 0000000..b5ba419 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/board_info.txt @@ -0,0 +1,3 @@ +Board name: lowrisc nexys4ddr +Category: eval +Board URL: "Tutorial for the debug preview of lowrisc" in a search engine diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb new file mode 100644 index 0000000..e857276 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c new file mode 100644 index 0000000..e74b438 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> +#include <symbols.h> + +static void mainboard_enable(device_t dev) +{ + /* + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; + + if (!dev) + die("No dev0; die\n"); + + ram_resource(dev, 0, _dram, ram_size/KiB); + + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld new file mode 100644 index 0000000..0348c47 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +#define START 0x80000000 + +SECTIONS +{ + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + PAGETABLES(START + 8M + 200K, 56K) + RAMSTAGE(START + 8M + 256K, 256K) +} diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c new file mode 100644 index 0000000..7d4ed00 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> +#include <symbols.h> + +/* + * _dram is the start of RAM. We currently need to load coreboot.rom into + * RAM. The actual "rom" code on the FPGAs is in a block ram. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c new file mode 100644 index 0000000..a606ad6 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <console/console.h> + +void main(void) +{ + // You currently can not call console_init from romstage. It brings + // in COREBOOT_EXTRA_VERSION, which is in .data, and we get a linker + // warning. I suspect the best fix is to have all the declarations + // in src/lib/version.c set up to be in the .text or .rodata + // section but that's a problem for another day. At some point + // we'd like to call console_init here. + console_init(); + run_ramstage(); +} diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c new file mode 100644 index 0000000..e3c233f80 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/uart.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <spike_util.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t) 0x42000000; +} + +/* these are currently not quite right but they are here for reference + * and will be fixed when lowrisc gives us a standard clock + * and set of values. */ +// divisor = clk_freq / (16 * Baud) +unsigned int uart_input_clock_divider(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) % 0x100; +} + +// System clock 25 MHz, 115200 baud rate +unsigned int uart_platform_refclk(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) >> 8; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c new file mode 100644 index 0000000..32cdb6d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/util.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, + * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING + * LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS + * DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING + * DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS + * IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, + * UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + /* Ensure the other hart sees it. */ + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +}

1 0

Patch set updated for coreboot: riscv: Move SBI call implementations under arch/riscv/
by Jonathan Neuschäfer 28 Oct '16

28 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17057 -gerrit commit 46fc2c5001ed972df48476b017f2fd2d225a0d4d Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Oct 28 00:25:02 2016 +0200 riscv: Move SBI call implementations under arch/riscv/ Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu with a linux payload. It worked as much as before (Linux didn't boot, but it successfully made some SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 2 +- src/arch/riscv/include/mcall.h | 70 ++++++++++++++++ src/arch/riscv/include/spike_util.h | 70 ---------------- src/arch/riscv/mcall.c | 100 +++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 2 +- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 - src/mainboard/emulation/qemu-riscv/qemu_util.c | 100 ----------------------- src/mainboard/emulation/spike-riscv/Makefile.inc | 3 - src/mainboard/emulation/spike-riscv/spike_util.c | 100 ----------------------- src/mainboard/emulation/spike-riscv/uart.c | 1 - 10 files changed, 172 insertions(+), 279 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index cf6ce99..1fe8f7c 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -34,6 +34,7 @@ $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += misc.c @@ -89,7 +90,6 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = -ramstage-y += trap_handler.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h new file mode 100644 index 0000000..a43b9cf --- /dev/null +++ b/src/arch/riscv/include/mcall.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MCALL_H +#define _MCALL_H + +#include <arch/encoding.h> +#include <atomic.h> +#include <stdint.h> + +#define HLS_SIZE 64 +#define MENTRY_FRAME_SIZE HLS_SIZE + +typedef struct { + unsigned long base; + unsigned long size; + unsigned long node_id; +} memory_block_info; + +typedef struct { + unsigned long dev; + unsigned long cmd; + unsigned long data; + unsigned long sbi_private_data; +} sbi_device_message; + + +typedef struct { + sbi_device_message* device_request_queue_head; + unsigned long device_request_queue_size; + sbi_device_message* device_response_queue_head; + sbi_device_message* device_response_queue_tail; + + int hart_id; + int ipi_pending; +} hls_t; + +#define MACHINE_STACK_TOP() ({ \ + register uintptr_t sp asm ("sp"); \ + (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) + +// hart-local storage, at top of stack +#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) +#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) + +#define MACHINE_STACK_SIZE RISCV_PGSIZE + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p); +uintptr_t mcall_console_putchar(uint8_t ch); +uintptr_t mcall_dev_req(sbi_device_message *m); +uintptr_t mcall_dev_resp(void); +uintptr_t mcall_set_timer(unsigned long long when); +uintptr_t mcall_clear_ipi(void); +uintptr_t mcall_send_ipi(uintptr_t recipient); +uintptr_t mcall_shutdown(void); +void hls_init(uint32_t hart_id); // need to call this before launching linux + +#endif diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/spike_util.h deleted file mode 100644 index 175ee6c..0000000 --- a/src/arch/riscv/include/spike_util.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SPIKE_UTIL_H -#define _SPIKE_UTIL_H - -#include <arch/encoding.h> -#include <atomic.h> -#include <stdint.h> - -#define HLS_SIZE 64 -#define MENTRY_FRAME_SIZE HLS_SIZE - -typedef struct { - unsigned long base; - unsigned long size; - unsigned long node_id; -} memory_block_info; - -typedef struct { - unsigned long dev; - unsigned long cmd; - unsigned long data; - unsigned long sbi_private_data; -} sbi_device_message; - - -typedef struct { - sbi_device_message* device_request_queue_head; - unsigned long device_request_queue_size; - sbi_device_message* device_response_queue_head; - sbi_device_message* device_response_queue_tail; - - int hart_id; - int ipi_pending; -} hls_t; - -#define MACHINE_STACK_TOP() ({ \ - register uintptr_t sp asm ("sp"); \ - (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) - -// hart-local storage, at top of stack -#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) -#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) - -#define MACHINE_STACK_SIZE RISCV_PGSIZE - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p); -uintptr_t mcall_console_putchar(uint8_t ch); -uintptr_t mcall_dev_req(sbi_device_message *m); -uintptr_t mcall_dev_resp(void); -uintptr_t mcall_set_timer(unsigned long long when); -uintptr_t mcall_clear_ipi(void); -uintptr_t mcall_send_ipi(uintptr_t recipient); -uintptr_t mcall_shutdown(void); -void hls_init(uint32_t hart_id); // need to call this before launching linux - -#endif diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c new file mode 100644 index 0000000..b571fbc --- /dev/null +++ b/src/arch/riscv/mcall.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <mcall.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +} diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..8a7b513 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -17,7 +17,7 @@ #include <arch/exception.h> #include <arch/sbi.h> #include <console/console.h> -#include <spike_util.h> +#include <mcall.h> #include <string.h> #include <vm.h> diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 4fbe401..36f1fca 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -13,14 +13,11 @@ ## GNU General Public License for more details. bootblock-y += uart.c -bootblock-y += qemu_util.c bootblock-y += rom_media.c romstage-y += romstage.c -romstage-y += qemu_util.c romstage-y += uart.c romstage-y += rom_media.c ramstage-y += uart.c -ramstage-y += qemu_util.c ramstage-y += rom_media.c bootblock-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c deleted file mode 100644 index c97a61f..0000000 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#include <arch/barrier.h> -#include <arch/errno.h> -#include <atomic.h> -#include <console/console.h> -#include <spike_util.h> -#include <string.h> -#include <vm.h> - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) -{ - if (id == 0) { - mprv_write_ulong(&info->base, 2U*GiB); - - /* TODO: Return the correct value */ - mprv_write_ulong(&info->size, 1*GiB); - return 0; - } - - return -1; -} - -uintptr_t mcall_send_ipi(uintptr_t recipient) -{ - die("mcall_send_ipi is currently not implemented"); - return 0; -} - -uintptr_t mcall_clear_ipi(void) -{ - // only clear SSIP if no other events are pending - if (HLS()->device_response_queue_head == NULL) { - clear_csr(mip, MIP_SSIP); - mb(); - } - - return atomic_swap(&HLS()->ipi_pending, 0); -} - -uintptr_t mcall_shutdown(void) -{ - die("mcall_shutdown is currently not implemented"); - return 0; -} - -uintptr_t mcall_set_timer(unsigned long long when) -{ - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); - return 0; -} - -uintptr_t mcall_dev_req(sbi_device_message *m) -{ - die("mcall_dev_req is currently not implemented"); - return 0; -} - -uintptr_t mcall_dev_resp(void) -{ - die("mcall_dev_resp is currently not implemented"); - return 0; -} - -void hls_init(uint32_t hart_id) -{ - memset(HLS(), 0, sizeof(*HLS())); - HLS()->hart_id = hart_id; -} - -uintptr_t mcall_console_putchar(uint8_t ch) -{ - do_putchar(ch); - return 0; -} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index e3c9481..36f1fca 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -13,14 +13,11 @@ ## GNU General Public License for more details. bootblock-y += uart.c -bootblock-y += spike_util.c bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += uart.c -romstage-y += spike_util.c romstage-y += rom_media.c ramstage-y += uart.c -ramstage-y += spike_util.c ramstage-y += rom_media.c bootblock-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c deleted file mode 100644 index c97a61f..0000000 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#include <arch/barrier.h> -#include <arch/errno.h> -#include <atomic.h> -#include <console/console.h> -#include <spike_util.h> -#include <string.h> -#include <vm.h> - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) -{ - if (id == 0) { - mprv_write_ulong(&info->base, 2U*GiB); - - /* TODO: Return the correct value */ - mprv_write_ulong(&info->size, 1*GiB); - return 0; - } - - return -1; -} - -uintptr_t mcall_send_ipi(uintptr_t recipient) -{ - die("mcall_send_ipi is currently not implemented"); - return 0; -} - -uintptr_t mcall_clear_ipi(void) -{ - // only clear SSIP if no other events are pending - if (HLS()->device_response_queue_head == NULL) { - clear_csr(mip, MIP_SSIP); - mb(); - } - - return atomic_swap(&HLS()->ipi_pending, 0); -} - -uintptr_t mcall_shutdown(void) -{ - die("mcall_shutdown is currently not implemented"); - return 0; -} - -uintptr_t mcall_set_timer(unsigned long long when) -{ - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); - return 0; -} - -uintptr_t mcall_dev_req(sbi_device_message *m) -{ - die("mcall_dev_req is currently not implemented"); - return 0; -} - -uintptr_t mcall_dev_resp(void) -{ - die("mcall_dev_resp is currently not implemented"); - return 0; -} - -void hls_init(uint32_t hart_id) -{ - memset(HLS(), 0, sizeof(*HLS())); - HLS()->hart_id = hart_id; -} - -uintptr_t mcall_console_putchar(uint8_t ch) -{ - do_putchar(ch); - return 0; -} diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 8513849..57647fe 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -17,7 +17,6 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> -#include <spike_util.h> uintptr_t uart_platform_base(int idx) {

1 0

New patch to review for coreboot: util/board_status/to-wiki: replace unicode with html entities
by Martin Roth 28 Oct '16

28 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17171 -gerrit commit 4def1817091bbdb5408bfbd47b14e5d02d288b3f Author: Martin Roth <martinroth(a)google.com> Date: Thu Oct 27 16:39:05 2016 -0700 util/board_status/to-wiki: replace unicode with html entities After the wiki update, the supported motherboard page wasn't printing any cells that contained unicode characters. There's probably another way to fix it that can be enabled, but changing the unicode characters to html entity encoding fixes the problem in the script. Change-Id: I8346275f4a8e8a075b65268d8daaab1d86299b2b Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/to-wiki/towiki.sh | 86 ++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 2e458c6..57a76f4 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -220,66 +220,66 @@ EOF vendor_board_dir="$COREBOOT_DIR"/src/mainboard/"$venboard"; northbridge="$(sed -n "/^[[:space:]]*select NORTHBRIDGE_/ s,^[[:space:]]*select NORTHBRIDGE_,,p" "$vendor_board_dir/Kconfig")" - northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_PI_$.*$,AMD \1 (PI),g;s,INTEL_FSP_$.*$,Intel® \1 (FSP),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel®,g;')" + northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_PI_$.*$,AMD \1 (PI),g;s,INTEL_FSP_$.*$,Intel© \1 (FSP),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel©,g;')" southbridge="$(sed -n "/[[:space:]]*select SOUTHBRIDGE_/ s,[[:space:]]*select SOUTHBRIDGE_$[^ ]*$.*$,\1,p" "$vendor_board_dir/Kconfig"|grep -v SKIP_|grep -v DISABLE_)" - southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" + southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel©,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" - superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" + superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC©,g;s,NUVOTON,Nuvoton ,g')" cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY"|grep -v CPU_MICROCODE_CBFS_NONE)" case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" socket_nice="?";; AMD_GEODE_*) - cpu_nice="AMD Geode™ ${cpu#AMD_GEODE_}"; - socket_nice="—";; + cpu_nice="AMD Geode™ ${cpu#AMD_GEODE_}"; + socket_nice="–";; AMD_SOCKET_754) - cpu_nice="AMD Sempron™ / Athlon™ 64 / Turion™ 64"; + cpu_nice="AMD Sempron™ / Athlon™ 64 / Turion™ 64"; socket_nice="Socket 754";; AMD_SOCKET_ASB2) - cpu_nice="AMD Turion™ II Neo/Athlon™ II Neo"; + cpu_nice="AMD Turion™ II Neo/Athlon™ II Neo"; socket_nice="ASB2 (BGA812)";; AMD_SOCKET_S1G1) - cpu_nice="AMD Turion™ / X2 Sempron™"; + cpu_nice="AMD Turion™ / X2 Sempron™"; socket_nice="Socket S1G1";; AMD_SOCKET_G34|AMD_SOCKET_G34_NON_AGESA) - cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; + cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; socket_nice="Socket G34";; AMD_SOCKET_C32|AMD_SOCKET_C32_NON_AGESA) - cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; + cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; socket_nice="Socket C32";; AMD_SOCKET_AM2) cpu_nice="?"; socket_nice="Socket AM2" ;; AMD_SOCKET_AM3) - cpu_nice="AMD Athlon™ 64 / FX / X2"; + cpu_nice="AMD Athlon™ 64 / FX / X2"; socket_nice="Socket AM3" ;; AMD_SOCKET_AM2R2) - cpu_nice="AMD Athlon™ 64 / X2 / FX, Sempron™"; + cpu_nice="AMD Athlon™ 64 / X2 / FX, Sempron™"; socket_nice="Socket AM2+" ;; AMD_SOCKET_F) - cpu_nice="AMD Opteron™"; + cpu_nice="AMD Opteron™"; socket_nice="Socket F" ;; AMD_SOCKET_F_1207) - cpu_nice="AMD Opteron™"; + cpu_nice="AMD Opteron™"; socket_nice="Socket F 1207" ;; AMD_SOCKET_940) - cpu_nice="AMD Opteron™"; + cpu_nice="AMD Opteron™"; socket_nice="Socket 940" ;; AMD_SOCKET_939) - cpu_nice="AMD Athlon™ 64 / FX / X2"; + cpu_nice="AMD Athlon™ 64 / FX / X2"; socket_nice="Socket 939" ;; AMD_SC520) - cpu_nice="AMD Élan™SC520"; - socket_nice="—";; + cpu_nice="AMD Elan™SC520"; + socket_nice="–";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; socket_nice="?";; @@ -296,93 +296,93 @@ EOF cpu_nice="TI AM335X"; socket_nice="?";; INTEL_SLOT_1) - cpu_nice="Intel® Pentium® II/III, Celeron®"; + cpu_nice="Intel© Pentium© II/III, Celeron©"; socket_nice="Slot 1";; INTEL_SOCKET_MPGA604) - cpu_nice="Intel® Xeon®"; + cpu_nice="Intel© Xeon©"; socket_nice="Socket 604";; INTEL_SOCKET_MFCPGA478) - cpu_nice="Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M"; + cpu_nice="Intel© Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron© M"; socket_nice="Socket mPGA478";; INTEL_SOCKET_LGA771) - cpu_nice="Intel Xeon™ 5000 series"; + cpu_nice="Intel Xeon™ 5000 series"; socket_nice="Socket LGA771";; INTEL_SOCKET_PGA370) - cpu_nice="Intel® Pentium® III-800, Celeron®" + cpu_nice="Intel© Pentium© III-800, Celeron©" socket_nice="Socket 370";; INTEL_SOCKET_MPGA479M) - cpu_nice="Intel® Mobile Celeron" + cpu_nice="Intel© Mobile Celeron" socket_nice="Socket 479" ;; INTEL_HASWELL) - cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7" + cpu_nice="Intel© 4th Gen (Haswell) Core i3/i5/i7" socket_nice="?" ;; INTEL_FSP_RANGELEY) - cpu_nice="Intel® Atom Rangeley (FSP)" + cpu_nice="Intel© Atom Rangeley (FSP)" socket_nice="?" ;; INTEL_SOCKET_RPGA989|INTEL_SOCKET_LGA1155|INTEL_SOCKET_RPGA988B) socket_nice="`echo $socket | sed 's,INTEL_SOCKET_,Socket ,g'`" case $northbridge in INTEL_HASWELL) - cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7";; + cpu_nice="Intel© 4th Gen (Haswell) Core i3/i5/i7";; INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE) - cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7";; + cpu_nice="Intel© 3rd Gen (Ivybridge) Core i3/i5/i7";; INTEL_SANDYBRIDGE) - cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7";; + cpu_nice="Intel© 2nd Gen (Sandybridge) Core i3/i5/i7";; *) cpu_nice="$northbridge";; esac ;; INTEL_SOCKET_441) - cpu_nice="Intel® Atom™ 230"; + cpu_nice="Intel© Atom™ 230"; socket_nice="Socket 441";; INTEL_SOCKET_BGA956) case $northbridge in INTEL_GM45) - cpu_nice="Intel® Core 2 Duo (Penryn)" + cpu_nice="Intel© Core 2 Duo (Penryn)" socket_nice="Socket P";; *) - cpu_nice="Intel® Pentium® M"; + cpu_nice="Intel© Pentium© M"; socket_nice="BGA956";; esac ;; INTEL_SOCKET_FC_PGA370) - cpu_nice="Intel® Pentium® III / Celeron®"; + cpu_nice="Intel© Pentium© III / Celeron©"; socket_nice="Socket 370" ;; INTEL_EP80579) - cpu_nice="Intel® EP80579"; - socket_nice="Intel® EP80579" + cpu_nice="Intel© EP80579"; + socket_nice="Intel© EP80579" ;; INTEL_SOCKET_MFCBGA479) - cpu_nice="Intel® Mobile Celeron" + cpu_nice="Intel© Mobile Celeron" socket_nice="Socket 479";; VIA_C3) - cpu_nice="VIA C3™"; + cpu_nice="VIA C3™"; socket_nice="?" ;; VIA_C7) - cpu_nice="VIA C7™"; + cpu_nice="VIA C7™"; socket_nice="?" ;; VIA_NANO) - cpu_nice="VIA Nano™"; + cpu_nice="VIA Nano™"; socket_nice="?" ;; QEMU_X86) cpu_nice="QEMU x86"; - socket_nice="—" + socket_nice="–" ;; "") case $northbridge in INTEL_NEHALEM) - cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7" + cpu_nice="Intel© 1st Gen (Nehalem) Core i3/i5/i7" socket_nice="?";; RDC_R8610) cpu_nice="RDC 8610" - socket_nice="—";; + socket_nice="–";; AMD_AGESA_*|AMD_PI_*) cpu_nice="$northbridge_nice" socket_nice="?";; @@ -479,7 +479,7 @@ EOF if [ "$vendor_cooperation_page" != "" ]; then echo "| [[$vendor_cooperation_page|$vendor_cooperation_score]]" elif [ "$vendor_cooperation_score" = "" ]; then - echo "| —" + echo "| –" else echo "| $vendor_cooperation_score" fi

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Patch set updated for coreboot: ifdtool: refactor VSCC table parsing
by Alexander Couzens 28 Oct '16

28 Oct '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16569 -gerrit commit f350049b3f9add4b83fad0abce57560328991e88 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Sep 10 13:30:32 2016 +0200 ifdtool: refactor VSCC table parsing - move into own files - use structs instead of bit operations Change-Id: I15780068ff5827bc4381a2e951e1c4384dd4c18e Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/ifdtool/Makefile | 2 +- util/ifdtool/ifdtool.c | 77 +---------------------------------------------- util/ifdtool/ifdtool.h | 11 ------- util/ifdtool/vtba.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++ util/ifdtool/vtba.h | 59 ++++++++++++++++++++++++++++++++++++ 5 files changed, 143 insertions(+), 88 deletions(-) diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index 77547ef..945b501 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -21,7 +21,7 @@ PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W -Werror LDFLAGS = -OBJS = ifdtool.o +OBJS = vtba.o ifdtool.o all: dep $(PROGRAM) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 74588e1..94a81ee 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -22,6 +22,7 @@ #include <sys/types.h> #include <sys/stat.h> #include "ifdtool.h" +#include "vtba.h" #ifndef O_BINARY #define O_BINARY 0 @@ -518,82 +519,6 @@ static void dump_fmsba(fmsba_t * fmsba) printf("????: 0x%08x\n", fmsba->data[3]); } -static void dump_jid(uint32_t jid) -{ - printf(" SPI Componend Device ID 1: 0x%02x\n", - (jid >> 16) & 0xff); - printf(" SPI Componend Device ID 0: 0x%02x\n", - (jid >> 8) & 0xff); - printf(" SPI Componend Vendor ID: 0x%02x\n", - jid & 0xff); -} - -static void dump_vscc(uint32_t vscc) -{ - printf(" Lower Erase Opcode: 0x%02x\n", - vscc >> 24); - printf(" Lower Write Enable on Write Status: 0x%02x\n", - vscc & (1 << 20) ? 0x06 : 0x50); - printf(" Lower Write Status Required: %s\n", - vscc & (1 << 19) ? "Yes" : "No"); - printf(" Lower Write Granularity: %d bytes\n", - vscc & (1 << 18) ? 64 : 1); - printf(" Lower Block / Sector Erase Size: "); - switch ((vscc >> 16) & 0x3) { - case 0: - printf("256 Byte\n"); - break; - case 1: - printf("4KB\n"); - break; - case 2: - printf("8KB\n"); - break; - case 3: - printf("64KB\n"); - break; - } - - printf(" Upper Erase Opcode: 0x%02x\n", - (vscc >> 8) & 0xff); - printf(" Upper Write Enable on Write Status: 0x%02x\n", - vscc & (1 << 4) ? 0x06 : 0x50); - printf(" Upper Write Status Required: %s\n", - vscc & (1 << 3) ? "Yes" : "No"); - printf(" Upper Write Granularity: %d bytes\n", - vscc & (1 << 2) ? 64 : 1); - printf(" Upper Block / Sector Erase Size: "); - switch (vscc & 0x3) { - case 0: - printf("256 Byte\n"); - break; - case 1: - printf("4KB\n"); - break; - case 2: - printf("8KB\n"); - break; - case 3: - printf("64KB\n"); - break; - } -} - -static void dump_vtba(vtba_t *vtba, int vtl) -{ - int i; - int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8; - - printf("ME VSCC table:\n"); - for (i = 0; i < num; i++) { - printf(" JID%d: 0x%08x\n", i, vtba->entry[i].jid); - dump_jid(vtba->entry[i].jid); - printf(" VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc); - dump_vscc(vtba->entry[i].vscc); - } - printf("\n"); -} - static void dump_oem(uint8_t *oem) { int i, j; diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 7878712..2b5da4f 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -120,17 +120,6 @@ typedef struct { uint32_t data[8]; } __attribute__((packed)) fmsba_t; -// ME VSCC -typedef struct { - uint32_t jid; - uint32_t vscc; -} vscc_t; - -typedef struct { - // Actual number of entries specified in vtl - vscc_t entry[8]; -} vtba_t; - typedef struct { int base, limit, size; } region_t; diff --git a/util/ifdtool/vtba.c b/util/ifdtool/vtba.c new file mode 100644 index 0000000..1fe5b6d --- /dev/null +++ b/util/ifdtool/vtba.c @@ -0,0 +1,82 @@ +/* + * vscc table tool + * + * Copyright (C) 2016 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <sys/types.h> + +#include "vtba.h" + + +static void dump_jid(struct jid *jid) +{ + printf(" SPI Componend Device ID 1: 0x%02x\n", + jid->device_id1); + printf(" SPI Componend Device ID 0: 0x%02x\n", + jid->device_id0); + printf(" SPI Componend Vendor ID: 0x%02x\n", + jid->vendor); +} + +static void dump_vscc_entry(const char *prefix, struct vscc_entry *entry) +{ + printf(" %s Erase Opcode: 0x%02x\n", + prefix, entry->erase_opcode); + printf(" %s Write Enable on Write Status: 0x%02x\n", + prefix, entry->write_enable_on_write_status ? 0x06 : 0x50); + printf(" %s Write Status Required: %s\n", + prefix, entry->status_required ? "Yes" : "No"); + printf(" %s Write Granularity: %d bytes\n", + prefix, entry->granularity ? 64 : 1); + printf(" %s Block / Sector Erase Size: ", prefix); + switch ((enum sector_size) entry->sector_size) { + case SECTOR_256B: + printf("256 Byte\n"); + break; + case SECTOR_4KB: + printf("4KB\n"); + break; + case SECTOR_8KB: + printf("8KB\n"); + break; + case SECTOR_64KB: + printf("64KB\n"); + break; + default: + printf("Unknown %x\n", entry->sector_size); + } +} + +static void dump_vscc(struct vscc *vscc) +{ + dump_vscc_entry("Lower", &vscc->lower); + dump_vscc_entry("Upper", &vscc->upper); +} + +void dump_vtba(vtba_t *vtba, int vtl) +{ + int i; + int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8; + + printf("ME VSCC table:\n"); + for (i = 0; i < num; i++) { + printf(" JID%d: 0x%08x\n", + i, (*((uint32_t *) &vtba->entry[i].jid))); + dump_jid(&vtba->entry[i].jid); + printf(" VSCC%d: 0x%08x\n", + i, (*((uint32_t *) &vtba->entry[i].vscc))); + dump_vscc(&vtba->entry[i].vscc); + } + printf("\n"); +} diff --git a/util/ifdtool/vtba.h b/util/ifdtool/vtba.h new file mode 100644 index 0000000..3814c90 --- /dev/null +++ b/util/ifdtool/vtba.h @@ -0,0 +1,59 @@ +/* + * ifdtool - dump Intel Firmware Descriptor information + * + * Copyright (C) 2016 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> + +// ME VSCC + +enum sector_size { + SECTOR_256B = 0, + SECTOR_4KB, + SECTOR_8KB, + SECTOR_64KB, +}; + +/* 16 bit */ +struct vscc_entry { + int sector_size:2; + int granularity:1; + int status_required:1; + int write_enable_on_write_status:1; + int blank:3; + uint8_t erase_opcode; +} __attribute__((packed)); + +struct vscc { + struct vscc_entry upper; + struct vscc_entry lower; +} __attribute__((packed)); + +struct jid { + uint8_t vendor; + uint8_t device_id0; + uint8_t device_id1; + uint8_t blank; +} __attribute__((packed)); + +struct vss_combined { + struct jid jid; + struct vscc vscc; +} __attribute__((packed)); + +typedef struct { + // Actual number of entries specified in vtl + struct vss_combined entry[8]; +} vtba_t; + +void dump_vtba(vtba_t *vtba, int vtl);

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coreboot-gerrit October 2016