coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: northbridge/amd: Update 00670F00 asl for reduced hardware
by Marc Jones 28 Oct '16

28 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17144 -gerrit commit 4eb427035cac9610656715d4c41892f9e2f79bd9 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 17:57:08 2016 -0400 northbridge/amd: Update 00670F00 asl for reduced hardware Remove the language associated with the Carrizo Gfx PCIe bridges. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748) Change-Id: I8b67a646f98667d500fcee5da8389c10483488da Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- .../amd/pi/00670F00/acpi/northbridge.asl | 36 +--------------------- 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl index cde5182..e5cf34f 100644 --- a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -94,38 +95,3 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -/* GFX 1 */ -Device(PBR9) { - Name(_ADR, 0x00030002) -} /* end PBR8 */ - -/* GFX 2 */ -Device(PBRA) { - Name(_ADR, 0x00030003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSA) } /* APIC mode */ - Return (PSA) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 3 */ -Device(PBRB) { - Name(_ADR, 0x00030004) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSB) } /* APIC mode */ - Return (PSB) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 4 */ -Device(PBRC) { - Name(_ADR, 0x00030005) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSC) } /* APIC mode */ - Return (PSC) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */

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Patch set updated for coreboot: util/amdfwtool: Add PSP2 options to optstring
by Marc Jones 28 Oct '16

28 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17147 -gerrit commit fd396df9240fa2b4b977350e0eef3bb3f93ba1fe Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 21:05:45 2016 -0600 util/amdfwtool: Add PSP2 options to optstring Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de) Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 5f815ab..3af0078 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -300,7 +300,12 @@ uint32_t integrate_psp_firmwares(void *base, uint32_t pos, uint32_t *pspdir, amd return pos; } -static const char *optstring = "x:i:g:p:b:s:r:k:o:n:d:t:u:w:m:h"; +#if PSP2 +static const char *optstring = "x:i:g:p:b:s:r:k:c:n:d:t:u:w:m:P:B:S:R:K:C:N:D:T:U:W:M:o:h"; +#else +static const char *optstring = "x:i:g:p:b:s:r:k:c:n:d:t:u:w:m:o:h"; +#endif + static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, {"imc", required_argument, 0, 'i' },

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Patch set updated for coreboot: util/amdfwtool: Fix duplicate long option name
by Marc Jones 28 Oct '16

28 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17146 -gerrit commit c3f2262886fafab16aca313dbbff5d96a729843d Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 14:49:41 2016 -0600 util/amdfwtool: Fix duplicate long option name Make the PSP2 smufirmware2 name unique so the command-line option gets picked up. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: <marcj303(a)gmail.com> (cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624) Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 2 +- util/amdfwtool/amdfwtool.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 291e25f..59e4240 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -177,7 +177,7 @@ OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs) OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2) OPT_2PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPBTLDR_FILE), --bootloader2) -OPT_2SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FILE), --smufirmware2) +OPT_2SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FILE), --smufirmware_2) OPT_2PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPRCVR_FILE), --recovery2) OPT_2PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_2PUBSIGNEDKEY_FILE), --rtmpubkey2) OPT_2PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSCUREOS_FILE), --secureos2) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 3dff2ac..5f815ab 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -323,7 +323,7 @@ static struct option long_options[] = { #if PSP2 {"pubkey2", required_argument, 0, 'P' }, {"bootloader2", required_argument, 0, 'B' }, - {"smufirmware2", required_argument, 0, 'S' }, + {"smufirmware_2", required_argument, 0, 'S' }, {"recovery2", required_argument, 0, 'R' }, {"rtmpubkey2", required_argument, 0, 'K' }, {"secureos2", required_argument, 0, 'C' },

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Patch set updated for coreboot: amd/hudson: Add PSP2 build for combo BIOS
by Marc Jones 28 Oct '16

28 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17149 -gerrit commit e1092fcb9106066b3361c188367b22d7783b22f6 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:50:25 2016 -0600 amd/hudson: Add PSP2 build for combo BIOS The Stoney processor can use multiple directory structures. Turn this feature on in the makefile. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e) Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 66 ++++++++++++++++++++++++------ 1 file changed, 53 insertions(+), 13 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 59e4240..53a1a4f0 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -161,19 +161,18 @@ OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_TRUSTLETKEY_FILE), --trustl OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_SMUFIRMWARE2_FILE), --smufirmware2) OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs) -#TODO: Set PSP2 Firmware. The setting below is just for testing. -#CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE) -#CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE) -#CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE) -#CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE) -#CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE) -#CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE) -#CONFIG_2PSPNVRAM_FILE =$(CONFIG_PSPNVRAM_FILE) -#CONFIG_2PSPSECUREDEBUG_FILE =$(CONFIG_PSPSECUREDEBUG_FILE) -#CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE) -#CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE) -#CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE) -#CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE) +CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE) +CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE) +CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE) +CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE) +CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE) +CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE) +CONFIG_2PSPNVRAM_FILE =$(CONFIG_PSPNVRAM_FILE) +CONFIG_2PSPSECUREDEBUG_FILE =$(CONFIG_PSPSECUREDEBUG_FILE) +CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE) +CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE) +CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE) +CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE) OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2) OPT_2PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPBTLDR_FILE), --bootloader2) @@ -203,9 +202,50 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_PSPTRUSTLETS_FILE)) \ $(call strip_quotes, $(CONFIG_TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(CONFIG_SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(CONFIG_2AMD_PUBKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_2PUBSIGNEDKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPBTLDR_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUFWM_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPRCVR_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPNVRAM_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUSCS_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPTRUSTLETS_FILE)) \ + $(call strip_quotes, $(CONFIG_2TRUSTLETKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUFIRMWARE2_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + echo "$(AMDFWTOOL) \ + $(OPT_HUDSON_XHCI_FWM_FILE) \ + $(OPT_HUDSON_IMC_FWM_FILE) \ + $(OPT_HUDSON_GEC_FWM_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUSCS_FILE) \ + $(OPT_2AMD_PUBKEY_FILE) \ + $(OPT_2PSPBTLDR_FILE) \ + $(OPT_2SMUFWM_FILE) \ + $(OPT_2PSPRCVR_FILE) \ + $(OPT_2PUBSIGNEDKEY_FILE) \ + $(OPT_2PSPSCUREOS_FILE) \ + $(OPT_2PSPNVRAM_FILE) \ + $(OPT_2PSPSECUREDEBUG_FILE) \ + $(OPT_2PSPTRUSTLETS_FILE) \ + $(OPT_2TRUSTLETKEY_FILE) \ + $(OPT_2SMUFIRMWARE2_FILE) \ + $(OPT_2SMUSCS_FILE) \ + --output $@" $(AMDFWTOOL) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \

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Patch set updated for coreboot: util/amdfwtool: Increase space used for structures
by Marc Jones 28 Oct '16

28 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17148 -gerrit commit 41f4198a1bc46d3032a842787bfdf5a78351ad12 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 22:55:54 2016 -0600 util/amdfwtool: Increase space used for structures Double the space for psp2dir to 0x200. Based on advice from AMD, increase the region containing the signature to 4K. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639) Change-Id: If60132f913928bab0c2fe4aacedf342080929599 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 3af0078..ef8795b 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -538,7 +538,7 @@ int main(int argc, char **argv) } } - current = ALIGN(current, 0x100); + current = ALIGN(current, 0x1000); current = integrate_firmwares(rom, current, amd_romsig, amd_fw_table); if (pspflag == 1) { @@ -555,7 +555,7 @@ int main(int argc, char **argv) current = ALIGN(current, 0x10000); /* PSP2 dir */ psp2dir = rom + current; amd_romsig[5] = current + ROM_BASE_ADDRESS; - current += 0x100; /* Add conservative size of psp2dir. */ + current += 0x200; /* Add conservative size of psp2dir. */ #if PSP_COMBO /* TODO: remove the hardcode. */

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New patch to review for coreboot: lib/program.ld: add .sdata sections
by Aaron Durbin 28 Oct '16

28 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17180 -gerrit commit f57af91d78e2605c54e117f62e29a78f0791c7c2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 12:24:48 2016 -0500 lib/program.ld: add .sdata sections Ron reported some toolchain emitting .sdata sections. Let's ensure we catch objects in those sections instead of getting dropped on the floor for architectures which emit those sections. Change-Id: I0680228f8424f99611914ef5fc31adf5d3891eee Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/program.ld | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lib/program.ld b/src/lib/program.ld index 4668aea..1526aad 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -100,6 +100,8 @@ *(.data); *(.data.*); + *(.sdata); + *(.sdata.*); #ifdef __PRE_RAM__ PROVIDE(_preram_cbmem_console = .);

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Patch set updated for coreboot: riscv: add the lowrisc/nexys4ddr mainboard
by Ronald G. Minnich 28 Oct '16

28 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17132 -gerrit commit 608b12c5e2f895f2f52f8e75d1342cccaaddf6d0 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Oct 25 19:11:07 2016 -0700 riscv: add the lowrisc/nexys4ddr mainboard This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far due to PTE version issues with lowrisc. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/lowrisc/Kconfig | 16 ++++ src/mainboard/lowrisc/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Kconfig | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Makefile.inc | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/board_info.txt | 3 + src/mainboard/lowrisc/nexys4ddr/devicetree.cb | 20 +++++ src/mainboard/lowrisc/nexys4ddr/mainboard.c | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 31 ++++++++ src/mainboard/lowrisc/nexys4ddr/rom_media.c | 30 +++++++ src/mainboard/lowrisc/nexys4ddr/romstage.c | 23 ++++++ src/mainboard/lowrisc/nexys4ddr/uart.c | 40 ++++++++++ src/mainboard/lowrisc/nexys4ddr/util.c | 103 +++++++++++++++++++++++++ 13 files changed, 374 insertions(+) diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig new file mode 100644 index 0000000..ba0fbe7 --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LOWRISC + +choice + prompt "Mainboard model" + +source "src/mainboard/lowrisc/*/Kconfig.name" + +endchoice + +source "src/mainboard/lowrisc/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "lowrisc" + +endif # VENDOR_LOWRISC diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name new file mode 100644 index 0000000..4c992fc --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LOWRISC + bool "lowrisc" diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig new file mode 100644 index 0000000..f0a3637 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_LOWRISC_NEXYS4DDR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_LOWRISC_LOWRISC + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_UART_8250MEM + select BOOT_DEVICE_NOT_SPI_FLASH + select UART_OVERRIDE_REFCLK + select UART_OVERRIDE_INPUT_CLOCK_DIVIDER + +config MAINBOARD_DIR + string + default lowrisc/nexys4ddr + +config MAINBOARD_PART_NUMBER + string + default "LOWRISC NEXYS4DDR" + +config MAX_CPUS + int + default 1 + +endif # BOARD_LOWRISC_NEXYS4DDR diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name new file mode 100644 index 0000000..f99b3cc --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LOWRISC_NEXYS4DDR + bool "nexys4ddr" diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc new file mode 100644 index 0000000..69519b1 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +bootblock-y += uart.c +bootblock-y += util.c +bootblock-y += rom_media.c +romstage-y += romstage.c +romstage-y += uart.c +romstage-y += util.c +romstage-y += rom_media.c +ramstage-y += uart.c +ramstage-y += util.c +ramstage-y += rom_media.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt new file mode 100644 index 0000000..a305030 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/board_info.txt @@ -0,0 +1,3 @@ +Board name: lowrisc nexys4ddr +Category: eval +Board URL: https://www.google.com/search?q=Tutorial+for+the+debug+preview+of+lowRISC&o… diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb new file mode 100644 index 0000000..e857276 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c new file mode 100644 index 0000000..1ceb97d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> +#include <symbols.h> + +static void mainboard_enable(device_t dev) +{ + /* + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; + + if (!dev) + die("No dev0; die\n"); + + ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size / KiB); + + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld new file mode 100644 index 0000000..0348c47 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +#define START 0x80000000 + +SECTIONS +{ + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + PAGETABLES(START + 8M + 200K, 56K) + RAMSTAGE(START + 8M + 256K, 256K) +} diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c new file mode 100644 index 0000000..7d4ed00 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> +#include <symbols.h> + +/* + * _dram is the start of RAM. We currently need to load coreboot.rom into + * RAM. The actual "rom" code on the FPGAs is in a block ram. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c new file mode 100644 index 0000000..1509efb --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/romstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <console/console.h> + +void main(void) +{ + console_init(); + run_ramstage(); +} diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c new file mode 100644 index 0000000..e3c233f80 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/uart.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <spike_util.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t) 0x42000000; +} + +/* these are currently not quite right but they are here for reference + * and will be fixed when lowrisc gives us a standard clock + * and set of values. */ +// divisor = clk_freq / (16 * Baud) +unsigned int uart_input_clock_divider(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) % 0x100; +} + +// System clock 25 MHz, 115200 baud rate +unsigned int uart_platform_refclk(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) >> 8; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c new file mode 100644 index 0000000..32cdb6d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/util.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, + * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING + * LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS + * DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING + * DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS + * IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, + * UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + /* Ensure the other hart sees it. */ + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +}

1 0

Patch merged into coreboot/master: mainboard/google/reef: allow variants to override NHLT OEM strings
by gerrit＠coreboot.org 28 Oct '16

28 Oct '16

the following patch was just integrated into master: commit 083e2e4ec4a78a19f0b00e54c649830151c18f4d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 27 13:24:06 2016 -0500 mainboard/google/reef: allow variants to override NHLT OEM strings In certain cases a board variant may need to override the NHLT OEM strings in the main NHLT table. Therefore, provide that path. BUG=chrome-os-partner:56918 Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17167 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> See https://review.coreboot.org/17167 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/google/reef: update comment for DMIC config usage
by gerrit＠coreboot.org 28 Oct '16

28 Oct '16

the following patch was just integrated into master: commit 558c8a57b9f4d7391304e7b50f3ee393c436015e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 27 12:11:15 2016 -0500 mainboard/google/reef: update comment for DMIC config usage Going forward GPIO_17 is used to determine the configuration of the board w.r.t. the number of DMICs on the board. BUG=chrome-os-partner:56918 Change-Id: I03edb880e0649977030c1b87219ebebac631a519 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17163 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17163 for details. -gerrit

1 0

Patch set updated for coreboot: eve: Add new board
by Duncan Laurie 28 Oct '16

28 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17177 -gerrit commit a2dcf8ed9fbff276e837f6ef789b564bd7e1a78b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 28 09:13:52 2016 -0700 eve: Add new board Add the eve board files using kabylake and FSP 2.0. BUG=chrome-os-partner:58666 TEST=build and boot on eve board Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/Kconfig | 70 +++++ src/mainboard/google/eve/Kconfig.name | 2 + src/mainboard/google/eve/Makefile.inc | 32 +++ src/mainboard/google/eve/acpi/dptf.asl | 97 +++++++ src/mainboard/google/eve/acpi/ec.asl | 0 src/mainboard/google/eve/acpi/superio.asl | 0 src/mainboard/google/eve/acpi_tables.c | 14 + src/mainboard/google/eve/board_info.txt | 6 + src/mainboard/google/eve/boardid.c | 27 ++ src/mainboard/google/eve/bootblock.c | 30 +++ src/mainboard/google/eve/chromeos.c | 86 +++++++ src/mainboard/google/eve/chromeos.fmd | 38 +++ src/mainboard/google/eve/devicetree.cb | 286 +++++++++++++++++++++ src/mainboard/google/eve/dsdt.asl | 70 +++++ src/mainboard/google/eve/ec.c | 43 ++++ src/mainboard/google/eve/ec.h | 74 ++++++ src/mainboard/google/eve/gpio.h | 232 +++++++++++++++++ src/mainboard/google/eve/mainboard.c | 35 +++ src/mainboard/google/eve/ramstage.c | 23 ++ src/mainboard/google/eve/romstage.c | 49 ++++ src/mainboard/google/eve/smihandler.c | 58 +++++ src/mainboard/google/eve/spd/Makefile.inc | 39 +++ src/mainboard/google/eve/spd/empty.spd.hex | 16 ++ .../eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex | 16 ++ .../google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex | 16 ++ src/mainboard/google/eve/spd/spd.c | 116 +++++++++ src/mainboard/google/eve/spd/spd.h | 35 +++ 27 files changed, 1510 insertions(+) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig new file mode 100644 index 0000000..b9cf652 --- /dev/null +++ b/src/mainboard/google/eve/Kconfig @@ -0,0 +1,70 @@ +if BOARD_GOOGLE_EVE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_16384 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select I2C_TPM + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_USES_FSP2_0 + select MMCONF_SUPPORT + select SOC_INTEL_SKYLAKE + select TPM2 + +config CHROMEOS + select LID_SWITCH + +config DRIVERS_I2C_GENERIC + def_bool y + +config DRIVERS_PS2_KEYBOARD + default y + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config DRIVER_TPM_I2C_IRQ + int + default 64 # GPE0_DW2_00 (GPP_E0) + +config EC_GOOGLE_CHROMEEC_BOARDNAME + string + default "eve" + +config GBB_HWID + string + depends on CHROMEOS + default "EVE TEST 1394" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "google/eve" + +config MAINBOARD_PART_NUMBER + string + default "Eve" + +config MAINBOARD_FAMILY + string + default "Google_Eve" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/google/eve/Kconfig.name b/src/mainboard/google/eve/Kconfig.name new file mode 100644 index 0000000..88cc6d3 --- /dev/null +++ b/src/mainboard/google/eve/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_EVE + bool "Eve" diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc new file mode 100644 index 0000000..8723e0c --- /dev/null +++ b/src/mainboard/google/eve/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c + +romstage-y += boardid.c + +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += boardid.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl new file mode 100644 index 0000000..6433090 --- /dev/null +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Ambient" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Charger" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "DRAM" +#define DPTF_TSR2_PASSIVE 50 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_TSR3_SENSOR_ID 4 +#define DPTF_TSR3_SENSOR_NAME "eMMC" +#define DPTF_TSR3_PASSIVE 50 +#define DPTF_TSR3_CRITICAL 75 + +#undef DPTF_ENABLE_FAN_CONTROL +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xbb8, "mA", 0 }, /* 3000mA (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Ambient */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Charger */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on DRAM */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, + + /* CPU Effect on eMMC */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on eMMC (TSR3) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2500, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 250 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 7000, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/eve/acpi/ec.asl b/src/mainboard/google/eve/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/eve/acpi/superio.asl b/src/mainboard/google/eve/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/eve/acpi_tables.c b/src/mainboard/google/eve/acpi_tables.c new file mode 100644 index 0000000..7782851 --- /dev/null +++ b/src/mainboard/google/eve/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/google/eve/board_info.txt b/src/mainboard/google/eve/board_info.txt new file mode 100644 index 0000000..0c4de9e --- /dev/null +++ b/src/mainboard/google/eve/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Eve +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/eve/boardid.c b/src/mainboard/google/eve/boardid.c new file mode 100644 index 0000000..e33c094 --- /dev/null +++ b/src/mainboard/google/eve/boardid.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +} diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c new file mode 100644 index 0000000..2c524f4 --- /dev/null +++ b/src/mainboard/google/eve/bootblock.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <gpio.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c new file mode 100644 index 0000000..63615b3 --- /dev/null +++ b/src/mainboard/google/eve/chromeos.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <rules.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "gpio.h" +#include "ec.h" + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, + gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_lid_switch(void) +{ + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); +} + +int get_developer_mode_switch(void) +{ + /* No physical developer mode switch. */ + return 0; +} + +int get_recovery_mode_switch(void) +{ + /* Check if the EC has posted the keyboard recovery event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int clear_recovery_mode_switch(void) +{ + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd new file mode 100644 index 0000000..58b6127 --- /dev/null +++ b/src/mainboard/google/eve/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0xe00000 { + RW_SECTION_A@0x0 0x3f0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3dffc0 + RW_FWID_A@0x3effc0 0x40 + } + RW_SECTION_B@0x3f0000 0x3f0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3dffc0 + RW_FWID_B@0x3effc0 0x40 + } + RW_MRC_CACHE@0x7e0000 0x10000 + RW_ELOG@0x7f0000 0x4000 + RW_SHARED@0x7f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x7f8000 0x2000 + RW_NVRAM@0x7fa000 0x6000 + RW_LEGACY(CBFS)@0x800000 0x200000 + WP_RO@0xa00000 0x400000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb new file mode 100644 index 0000000..d825acf --- /dev/null +++ b/src/mainboard/google/eve/devicetree.cb @@ -0,0 +1,286 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable" = "1" + register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "XdciEnable" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "FspSkipMpInit" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "SendVrMbxCmd" = "1" # IMVP8 workaround + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root port 1. + register "PcieRpEnable[0]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + # RP 1 uses SRCCLKREQ1# + register "PcieRpClkReqNumber[0]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_FLEX" # Camera + register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_LONG" # Type-C Port 2 + register "usb2_ports[6]" = "USB2_PORT_MID" # Type-A Port + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + + register "i2c[0].voltage" = "I2C_VOLTAGE_3V3" # Touchscreen + register "i2c[1].voltage" = "I2C_VOLTAGE_3V3" # TPM + register "i2c[2].voltage" = "I2C_VOLTAGE_1V8" # Touchpad + register "i2c[3].voltage" = "I2C_VOLTAGE_1V8" # Display + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # Audio + + # Enable I2C1 bus early for TPM access + register "i2c[1].early_init" = "1" + register "i2c[1].speed" = "I2C_SPEED_FAST" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + register "dptf_enable" = "1" + register "tdp_pl2_override" = "7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ATML0001"" + register "desc" = ""Atmel Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + device i2c 4b on end + end + chip drivers/i2c/generic + register "hid" = ""ATML0001"" + register "desc" = ""Atmel Touchscreen Bootloader"" + register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + device i2c 27 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPP_E0_IRQ)" + device i2c 50 on end + end + end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""ATML0000"" + register "desc" = ""Atmel Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 4a on end + end + chip drivers/i2c/generic + register "hid" = ""ATML0000"" + register "desc" = ""Atmel Touchpad Bootloader"" + register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 26 on end + end + end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl new file mode 100644 index 0000000..2882d50 --- /dev/null +++ b/src/mainboard/google/eve/dsdt.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" +#include "gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* Some generic macros */ + #include <soc/intel/skylake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/skylake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/skylake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + #include "acpi/dptf.asl" + } +} diff --git a/src/mainboard/google/eve/ec.c b/src/mainboard/google/eve/ec.c new file mode 100644 index 0000000..868714a --- /dev/null +++ b/src/mainboard/google/eve/ec.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} diff --git a/src/mainboard/google/eve/ec.h b/src/mainboard/google/eve/ec.h new file mode 100644 index 0000000..6666a70 --- /dev/null +++ b/src/mainboard/google/eve/ec.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include "gpio.h" +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h new file mode 100644 index 0000000..8fffe96 --- /dev/null +++ b/src/mainboard/google/eve/gpio.h @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* Power rail control signals. */ +#define EN_PP3300_DX_TOUCH GPP_C22 +#define EN_PP3300_DX_CAM GPP_D12 + +#ifndef __ACPI__ +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */ +/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ +/* ESPI_RESET# */ +/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */ +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */ +/* VRALERT# */ PAD_CFG_NC(GPP_B2), +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */ +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ +/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NC(GPP_B14), +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* DSP */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* DSP */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* DSP */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* DSP */ +/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */ +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */ +/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), + +/* SMBCLK */ PAD_CFG_NC(GPP_C0), +/* SMBDATA */ PAD_CFG_NC(GPP_C1), +/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SML0CLK */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), +/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */ +/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */ +/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ +/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ +/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ + +/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* TOUCHPAD_SPI */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), +/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ +/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */ +/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 1, DEEP), /* TOUCHSCREEN_STOP_L */ +/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), + +/* The next 4 pads are for bit banging the amplifiers, default to I2S */ +/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* TOUCHPAD */ +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* TOUCHPAD */ +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* DISPLAY */ +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* DISPLAY */ +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* TP109 */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NC(GPP_G0), +/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), +/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), +/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), +/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), +/* SD_CD# */ PAD_CFG_NC(GPP_G5), +/* SD_CLK */ PAD_CFG_NC(GPP_G6), +/* SD_WP */ PAD_CFG_NC(GPP_G7), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */ +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */ +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +}; + +#endif + +#endif diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c new file mode 100644 index 0000000..bffc9e6 --- /dev/null +++ b/src/mainboard/google/eve/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <device/device.h> +#include <ec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/eve/ramstage.c b/src/mainboard/google/eve/ramstage.c new file mode 100644 index 0000000..be3676a --- /dev/null +++ b/src/mainboard/google/eve/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c new file mode 100644 index 0000000..4ae87fd --- /dev/null +++ b/src/mainboard/google/eve/romstage.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <stddef.h> +#include <fsp/soc_binding.h> +#include <soc/romstage.h> +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 1, 0, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 3, 2, 7, 6 } }; + /* Rcomp resistor */ + const u16 rcomp_resistor[] = { 200, 81, 162 }; + /* Rcomp target */ + const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + + memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); + memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; +} diff --git a/src/mainboard/google/eve/smihandler.c b/src/mainboard/google/eve/smihandler.c new file mode 100644 index 0000000..c02a369 --- /dev/null +++ b/src/mainboard/google/eve/smihandler.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/smm.h> +#include "ec.h" +#include "gpio.h" + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +static void mainboard_gpio_smi_sleep(u8 slp_typ) +{ + int i; + + /* Power down the rails on any sleep type. */ + gpio_t active_high_signals[] = { + EN_PP3300_DX_TOUCH, + EN_PP3300_DX_CAM, + }; + + for (i = 0; i < ARRAY_SIZE(active_high_signals); i++) + gpio_set(active_high_signals[i], 0); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); + + mainboard_gpio_smi_sleep(slp_typ); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc new file mode 100644 index 0000000..f63cc8b --- /dev/null +++ b/src/mainboard/google/eve/spd/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## Copyright (C) 2016 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += samsung_dimm_K4E8E324EB # 0b0001 +SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += empty # 0b0011 +SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b0100 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/eve/spd/empty.spd.hex b/src/mainboard/google/eve/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/eve/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex b/src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex new file mode 100644 index 0000000..2f66a2a --- /dev/null +++ b/src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 80 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4A 54 4D 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex b/src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex new file mode 100644 index 0000000..7d72967 --- /dev/null +++ b/src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 32 34 45 42 2D 45 47 43 46 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c new file mode 100644 index 0000000..bac5107 --- /dev/null +++ b/src/mainboard/google/eve/spd/spd.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <string.h> + +#include "../gpio.h" +#include "spd.h" + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); + spd_index = 1; + } + + spd_index *= SPD_LEN; + mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); + + return (uintptr_t)(spd_file + spd_index); +} diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h new file mode 100644 index 0000000..9c2b26b --- /dev/null +++ b/src/mainboard/google/eve/spd/spd.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 +#define SPD_MANU_OFF 148 + +uintptr_t mainboard_get_spd_data(void); + +#endif

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coreboot-gerrit October 2016