coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

Patch merged into filo/master: Clean up after moving to libpayload's timer drivers
by gerrit＠coreboot.org 29 Oct '16

29 Oct '16

the following patch was just integrated into master: commit 3ea238bc75aead9aad2be88eaf693d0a207e2bff Author: Nico Huber <nico.h(a)gmx.de> Date: Tue Oct 25 20:32:44 2016 +0200 Clean up after moving to libpayload's timer drivers Change-Id: I6acf113758d603f4316c3f71ba3e245f78f65609 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/17126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17126 for details. -gerrit

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New patch to review for coreboot: chromeec: Update Chrome EC submodule
by Duncan Laurie 29 Oct '16

29 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17185 -gerrit commit f9e9e7fdc654feb8de3aa627c63bdcbc5aa2f12c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 28 16:07:57 2016 -0700 chromeec: Update Chrome EC submodule Update to Chromium TOT with ea1a8699e96425806abdd532d04da254ae093f6e Change-Id: I28b9f415a4d55442c294abd27c344a91608a06c0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- 3rdparty/chromeec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 0ef87a7..ea1a869 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 0ef87a741c2be6f5688ea1bea618085a3907cf5c +Subproject commit ea1a8699e96425806abdd532d04da254ae093f6e

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Patch set updated for coreboot: lib/prog_loaders: use common ramstage_cache_invalid()
by Aaron Durbin 29 Oct '16

29 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17184 -gerrit commit 8356e06b66eb037fc1c6e5c01d498dfbb79c81f6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 17:32:24 2016 -0500 lib/prog_loaders: use common ramstage_cache_invalid() All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/romstage.c | 10 ---------- src/drivers/intel/fsp1_1/romstage.c | 7 ------- src/drivers/intel/fsp2_0/stage_cache.c | 7 ------- src/include/program_loading.h | 3 --- src/lib/prog_loaders.c | 11 ++++++++++- src/soc/intel/baytrail/romstage/romstage.c | 8 -------- src/soc/intel/broadwell/romstage/romstage.c | 8 -------- 7 files changed, 10 insertions(+), 44 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8b62d43..f823c55 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -264,13 +264,3 @@ void asmlinkage romstage_after_car(void) /* Load the ramstage. */ run_ramstage(); } - - -#if IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - reset_system(); -#endif -} -#endif diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index a95e5e6..97379b2 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -380,13 +380,6 @@ __attribute__((weak)) void raminit(struct romstage_params *params) die("ERROR - No RAM initialization specified!\n"); } -void ramstage_cache_invalid(void) -{ - if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) - /* Perform cold reset on invalid ramstage cache. */ - hard_reset(); -} - /* Display the memory configuration */ __attribute__((weak)) void report_memory_config(void) { diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 4469a7f..434eae9 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -28,10 +28,3 @@ void stage_cache_external_region(void **base, size_t *size) *size = 0; } } - -void ramstage_cache_invalid(void) -{ - if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) - /* Perform cold reset on invalid ramstage cache. */ - hard_reset(); -} diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 3958fda..08687f3 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -167,9 +167,6 @@ void run_romstage(void); /* Run ramstage from romstage. */ void run_ramstage(void); -/* Called when the stage cache couldn't load ramstage on resume. */ -void ramstage_cache_invalid(void); - /* Determine where stack for ramstage loader is located. */ enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; uintptr_t romstage_ram_stack_base(size_t size, int src); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index c0dcd60..09933ae 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -22,6 +22,7 @@ #include <halt.h> #include <lib.h> #include <program_loading.h> +#include <reset.h> #include <romstage_handoff.h> #include <rmodule.h> #include <rules.h> @@ -74,7 +75,15 @@ void __attribute__((weak)) stage_cache_add(int stage_id, const struct prog *stage) {} void __attribute__((weak)) stage_cache_load_stage(int stage_id, struct prog *stage) {} -void __attribute__((weak)) ramstage_cache_invalid(void) {} + +static void ramstage_cache_invalid(void) +{ + printk(BIOS_ERR, "ramstage cache invalid.\n"); + if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) { + hard_reset(); + halt(); + } +} static void run_ramstage_from_resume(struct romstage_handoff *handoff, struct prog *ramstage) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 2b51744..9cf110e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -333,14 +333,6 @@ static void *setup_stack_and_mttrs(void) return slot; } -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - /* Perform cold reset on invalid ramstage cache. */ - cold_reset(); -#endif -} - int get_sw_write_protect_state(void) { u8 status; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f2b28a5..44df88c 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -133,14 +133,6 @@ void asmlinkage romstage_after_car(void) while (1); } -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - /* Perform cold reset on invalid ramstage cache. */ - reset_system(); -#endif -} - int get_sw_write_protect_state(void) { u8 status;

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New patch to review for coreboot: lib/prog_loaders: use common ramstage_cache_invalid()
by Aaron Durbin 29 Oct '16

29 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17184 -gerrit commit 8f011f21de643cab71bcf9df33238a6180b68148 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 17:32:24 2016 -0500 lib/prog_loaders: use common ramstage_cache_invalid() All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/romstage.c | 10 ---------- src/drivers/intel/fsp1_1/romstage.c | 7 ------- src/drivers/intel/fsp2_0/stage_cache.c | 7 ------- src/include/program_loading.h | 3 --- src/lib/prog_loaders.c | 10 +++++++++- src/soc/intel/baytrail/romstage/romstage.c | 8 -------- src/soc/intel/broadwell/romstage/romstage.c | 8 -------- 7 files changed, 9 insertions(+), 44 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8b62d43..f823c55 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -264,13 +264,3 @@ void asmlinkage romstage_after_car(void) /* Load the ramstage. */ run_ramstage(); } - - -#if IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - reset_system(); -#endif -} -#endif diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index a95e5e6..97379b2 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -380,13 +380,6 @@ __attribute__((weak)) void raminit(struct romstage_params *params) die("ERROR - No RAM initialization specified!\n"); } -void ramstage_cache_invalid(void) -{ - if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) - /* Perform cold reset on invalid ramstage cache. */ - hard_reset(); -} - /* Display the memory configuration */ __attribute__((weak)) void report_memory_config(void) { diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 4469a7f..434eae9 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -28,10 +28,3 @@ void stage_cache_external_region(void **base, size_t *size) *size = 0; } } - -void ramstage_cache_invalid(void) -{ - if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) - /* Perform cold reset on invalid ramstage cache. */ - hard_reset(); -} diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 3958fda..08687f3 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -167,9 +167,6 @@ void run_romstage(void); /* Run ramstage from romstage. */ void run_ramstage(void); -/* Called when the stage cache couldn't load ramstage on resume. */ -void ramstage_cache_invalid(void); - /* Determine where stack for ramstage loader is located. */ enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; uintptr_t romstage_ram_stack_base(size_t size, int src); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index c0dcd60..b187b0c 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -74,7 +74,15 @@ void __attribute__((weak)) stage_cache_add(int stage_id, const struct prog *stage) {} void __attribute__((weak)) stage_cache_load_stage(int stage_id, struct prog *stage) {} -void __attribute__((weak)) ramstage_cache_invalid(void) {} + +static void ramstage_cache_invalid(void) +{ + printk(BIOS_ERR, "ramstage cache invalid.\n"); + if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) { + hard_reset(); + halt(); + } +} static void run_ramstage_from_resume(struct romstage_handoff *handoff, struct prog *ramstage) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 2b51744..9cf110e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -333,14 +333,6 @@ static void *setup_stack_and_mttrs(void) return slot; } -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - /* Perform cold reset on invalid ramstage cache. */ - cold_reset(); -#endif -} - int get_sw_write_protect_state(void) { u8 status; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f2b28a5..44df88c 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -133,14 +133,6 @@ void asmlinkage romstage_after_car(void) while (1); } -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - /* Perform cold reset on invalid ramstage cache. */ - reset_system(); -#endif -} - int get_sw_write_protect_state(void) { u8 status;

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Patch set updated for coreboot: lib/program.ld: add .sdata sections
by Aaron Durbin 29 Oct '16

29 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17180 -gerrit commit e28c471039d3c48e9da9bbd0d712ec544195064e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 12:24:48 2016 -0500 lib/program.ld: add .sdata sections Ron reported some toolchain emitting .sdata sections. Let's ensure we catch objects in those sections instead of getting dropped on the floor for architectures which emit those sections. Change-Id: I0680228f8424f99611914ef5fc31adf5d3891eee Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/program.ld | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lib/program.ld b/src/lib/program.ld index 4668aea..1526aad 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -100,6 +100,8 @@ *(.data); *(.data.*); + *(.sdata); + *(.sdata.*); #ifdef __PRE_RAM__ PROVIDE(_preram_cbmem_console = .);

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Patch merged into coreboot/master: soc/intel/common: Add reset.c to postcar
by gerrit＠coreboot.org 29 Oct '16

29 Oct '16

the following patch was just integrated into master: commit 566feddeceb421ba6480bcee94f87bc4c95c6196 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 28 14:55:46 2016 -0700 soc/intel/common: Add reset.c to postcar ramstage_cache_invalid which was added in I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112) requires hard_reset to be defined in postcar stage. BUG=None BRANCH=None TEST=Compiles successfully for reef. Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17182 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17182 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
by Lijian Zhao 29 Oct '16

29 Oct '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17181 -gerrit commit c273ca711f8fb20434e838b83745640e7af51066 Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Fri Oct 28 11:01:09 2016 -0700 soc/intel/apollolake: Add pmc_ipc device support A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 62 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 65 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000..20b5a32 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 +#define PMIO_LIMIT 0x480 + +scope (\_SB) { + + Device (IPC1) + { + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) + Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) + Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) + IO (Decode16, ACPI_PMIO_BASE, PMIO_LIMIT, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (PMC_SRAM_BASE_0, SBAS) + + Return (^RBUF) + } + } + +} \ No newline at end of file diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 1c10f1a..e3ee1ae 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -46,5 +46,8 @@ Scope (\_SB) /* eMMC */ #include "scs.asl" +/* PMC IPC controller */ +#include "pmc_ipc.asl" + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

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Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
by Lijian Zhao 29 Oct '16

29 Oct '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17181 -gerrit commit c6e859e47706e6620ff861132e4366bec6bc4120 Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Fri Oct 28 11:01:09 2016 -0700 soc/intel/apollolake: Add pmc_ipc device support A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 62 +++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000..20b5a32 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 +#define PMIO_LIMIT 0x480 + +scope (\_SB) { + + Device (IPC1) + { + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) + Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) + Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) + IO (Decode16, ACPI_PMIO_BASE, PMIO_LIMIT, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (PMC_SRAM_BASE_0, SBAS) + + Return (^RBUF) + } + } + +} \ No newline at end of file

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Patch merged into coreboot/master: Documentation: Add documentation for GPIO toggling in ACPI AML
by gerrit＠coreboot.org 29 Oct '16

29 Oct '16

the following patch was just integrated into master: commit 4ef7491b2213555ad71920035b5d08e7798024fb Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 25 12:36:17 2016 -0700 Documentation: Add documentation for GPIO toggling in ACPI AML This document provides information about the different functions that a driver can use for generating ACPI code for toggling GPIO. These functions are expected to be implemented by the SoC. It also defines the different constraints on use of Local variables in ACPI code while implementing these functions. BUG=chrome-os-partner:55988 Change-Id: Ibc03d766afb6d7b75bc0dc9f79920b561f1c4a78 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17128 for details. -gerrit

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New patch to review for coreboot: riscv: bandaid for the new toolchain
by Ronald G. Minnich 29 Oct '16

29 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17183 -gerrit commit d03efe767c76fecd98b2531b2d6c8ea3cae67250 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Oct 28 15:08:59 2016 -0700 riscv: bandaid for the new toolchain Post a new toolchain build, the mhartid register value is wrong. Until such time as the bitstreams and toolchain can find a way to agree, just hardcode it. This gets spike running again. Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/bootblock.S | 6 +++++- src/arch/riscv/trap_handler.c | 2 +- src/arch/riscv/trap_util.S | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 63df92b..c54c0e2 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -32,7 +32,11 @@ _start: # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - csrr a0, mhartid + // Once again, the docs and toolchain disagree. + // Rather than get fancy I'll just lock this down + // until it all stabilizes. + //csrr a0, mhartid + csrr a0, 0xf14 call hls_init # poison the stack diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..8c69366 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -29,7 +29,7 @@ void handle_supervisor_call(trapframe *tf) { switch(call) { case SBI_ECALL_HART_ID: printk(BIOS_DEBUG, "Getting hart id...\n"); - returnValue = read_csr(mhartid); + returnValue = read_csr(0xf14);//mhartid); break; case SBI_ECALL_NUM_HARTS: /* TODO: parse the hardware-supplied config string and diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 5ee0fdd..3357959 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -119,7 +119,9 @@ trap_entry: # SMP isn't supported yet, to avoid overwriting the same stack with different # harts that handle traps at the same time. - csrr sp, mhartid + # someday this gets fixed. + //csrr sp, mhartid + csrr sp, 0xf14 .Lsmp_hang: bnez sp, .Lsmp_hang

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coreboot-gerrit October 2016