coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

1 participants
1281 discussions

New patch to review for coreboot: skylake: Add GPIO macro for confuring inverted APIC input
by Duncan Laurie 28 Oct '16

28 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17176 -gerrit commit 79328231c752d370fff432ba3e1dc67f04b9e68d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 28 09:07:49 2016 -0700 skylake: Add GPIO macro for confuring inverted APIC input Add a GPIO macro that allows a pin to be routed to the APIC with the input inverted. This allows a normal interrupt to get used as a GPE during firmware and still be used as a perhiperal interrupt in the kernel. BUG=chrome-os-partner:58666 TEST=boot en eve and use TPM IRQ in firmware and OS Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/include/soc/gpio.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index d86af0f..c520af7 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -144,6 +144,11 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES)) +/* General purpose input passed through to IOxAPIC as inverted input. */ +#define PAD_CFG_GPI_APIC_INVERT(pad_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, YES)) + /* General purpose input routed to SCI. This assumes edge triggered events. */ #define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \ _PAD_CFG_ATTRS(pad_, term_, \

1 0

Patch set updated for coreboot: riscv: add the lowrisc/nexys4ddr mainboard
by Ronald G. Minnich 28 Oct '16

28 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17132 -gerrit commit 5290f9206f224119ab3b4d47a06bb087f9de6eeb Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Oct 25 19:11:07 2016 -0700 riscv: add the lowrisc/nexys4ddr mainboard This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/lowrisc/Kconfig | 16 ++++ src/mainboard/lowrisc/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Kconfig | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Makefile.inc | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/board_info.txt | 3 + src/mainboard/lowrisc/nexys4ddr/devicetree.cb | 20 +++++ src/mainboard/lowrisc/nexys4ddr/mainboard.c | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 31 ++++++++ src/mainboard/lowrisc/nexys4ddr/rom_media.c | 30 +++++++ src/mainboard/lowrisc/nexys4ddr/romstage.c | 47 +++++++++++ src/mainboard/lowrisc/nexys4ddr/uart.c | 40 ++++++++++ src/mainboard/lowrisc/nexys4ddr/util.c | 103 +++++++++++++++++++++++++ 13 files changed, 398 insertions(+) diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig new file mode 100644 index 0000000..ba0fbe7 --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LOWRISC + +choice + prompt "Mainboard model" + +source "src/mainboard/lowrisc/*/Kconfig.name" + +endchoice + +source "src/mainboard/lowrisc/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "lowrisc" + +endif # VENDOR_LOWRISC diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name new file mode 100644 index 0000000..4c992fc --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LOWRISC + bool "lowrisc" diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig new file mode 100644 index 0000000..f0a3637 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_LOWRISC_NEXYS4DDR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_LOWRISC_LOWRISC + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_UART_8250MEM + select BOOT_DEVICE_NOT_SPI_FLASH + select UART_OVERRIDE_REFCLK + select UART_OVERRIDE_INPUT_CLOCK_DIVIDER + +config MAINBOARD_DIR + string + default lowrisc/nexys4ddr + +config MAINBOARD_PART_NUMBER + string + default "LOWRISC NEXYS4DDR" + +config MAX_CPUS + int + default 1 + +endif # BOARD_LOWRISC_NEXYS4DDR diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name new file mode 100644 index 0000000..f99b3cc --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LOWRISC_NEXYS4DDR + bool "nexys4ddr" diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc new file mode 100644 index 0000000..69519b1 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +bootblock-y += uart.c +bootblock-y += util.c +bootblock-y += rom_media.c +romstage-y += romstage.c +romstage-y += uart.c +romstage-y += util.c +romstage-y += rom_media.c +ramstage-y += uart.c +ramstage-y += util.c +ramstage-y += rom_media.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt new file mode 100644 index 0000000..a305030 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/board_info.txt @@ -0,0 +1,3 @@ +Board name: lowrisc nexys4ddr +Category: eval +Board URL: https://www.google.com/search?q=Tutorial+for+the+debug+preview+of+lowRISC&o… diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb new file mode 100644 index 0000000..e857276 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c new file mode 100644 index 0000000..1ceb97d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> +#include <symbols.h> + +static void mainboard_enable(device_t dev) +{ + /* + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; + + if (!dev) + die("No dev0; die\n"); + + ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size / KiB); + + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld new file mode 100644 index 0000000..0348c47 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +#define START 0x80000000 + +SECTIONS +{ + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + PAGETABLES(START + 8M + 200K, 56K) + RAMSTAGE(START + 8M + 256K, 256K) +} diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c new file mode 100644 index 0000000..7d4ed00 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> +#include <symbols.h> + +/* + * _dram is the start of RAM. We currently need to load coreboot.rom into + * RAM. The actual "rom" code on the FPGAs is in a block ram. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c new file mode 100644 index 0000000..411c851 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> +#include <console/console.h> + +void main(void) +{ + // You currently can not call console_init from romstage. As + // best I can tell, it brings in in COREBOOT_EXTRA_VERSION, + // which is in .data, and we get a linker warning. I suspect + // the best fix is to have all the declarations in + // src/lib/version.c set up to be in the .text or .rodata + // section but that's a problem for another day. At some point + // we'd like to call console_init here. + // + // The actual error is this: + // LINK cbfs/fallback/romstage.debug + // /home/rminnich/projects/riscv/coreboot/util/crossgcc/ + // xgcc/bin/riscv64-elf-ld.bfd: + // build/cbfs/fallback/romstage.debug: warning: + // allocated section `.data' not in segment + // OBJCOPY cbfs/fallback/romstage.elf + // /home/rminnich/projects/riscv/coreboot/util/crossgcc/ + // xgcc/bin/riscv64-elf-objcopy: + // build/cbfs/fallback/stVkYAzb: warning: allocated section + // `.data' not in segment + // /home/rminnich/projects/riscv/coreboot/util/crossgcc/ + // xgcc/bin/riscv64-elf-objcopy: + // build/cbfs/fallback/stk7I96a: warning: allocated section + // '.data' not in segment + + // console_init(); + run_ramstage(); +} diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c new file mode 100644 index 0000000..e3c233f80 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/uart.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <spike_util.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t) 0x42000000; +} + +/* these are currently not quite right but they are here for reference + * and will be fixed when lowrisc gives us a standard clock + * and set of values. */ +// divisor = clk_freq / (16 * Baud) +unsigned int uart_input_clock_divider(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) % 0x100; +} + +// System clock 25 MHz, 115200 baud rate +unsigned int uart_platform_refclk(void) +{ + return (25 * 1000 * 1000u / (16u * 115200u)) >> 8; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c new file mode 100644 index 0000000..32cdb6d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/util.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, + * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING + * LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS + * DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING + * DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS + * IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, + * UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + /* Ensure the other hart sees it. */ + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +}

1 0

Patch merged into coreboot/master: soc/intel/skylake: put back uart_debug.c into verstage
by gerrit＠coreboot.org 28 Oct '16

28 Oct '16

the following patch was just integrated into master: commit ffddf7beb455759e3d3962475deca52b88b19d5a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 09:54:02 2016 -0500 soc/intel/skylake: put back uart_debug.c into verstage uart_debug.c was accidentally dropped in verstage in 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 (https://review.coreboot.org/17136). Fix that. Change-Id: If37a028550d419bada80d157c4de02fd82d26c89 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17175 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17175 for details. -gerrit

1 0

Patch merged into coreboot/master: pcengines/apu1: Add RS485 configuration
by gerrit＠coreboot.org 28 Oct '16

28 Oct '16

the following patch was just integrated into master: commit e1c36aecd8c5ad580595da58e180b06195df5f00 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 13 15:01:15 2015 +0300 pcengines/apu1: Add RS485 configuration In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/14998 for details. -gerrit

1 0

New patch to review for coreboot: soc/intel/skylake: put back uart_debug.c into verstage
by Aaron Durbin 28 Oct '16

28 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17175 -gerrit commit 01fa1cecaa00480d9b3ed31f51db4b07ef2bf223 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 09:54:02 2016 -0500 soc/intel/skylake: put back uart_debug.c into verstage uart_debug.c was accidentally dropped in verstage in 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 (https://review.coreboot.org/17136). Fix that. Change-Id: If37a028550d419bada80d157c4de02fd82d26c89 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 1714572..32eb708 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -30,6 +30,7 @@ bootblock-y += tsc_freq.c verstage-y += flash_controller.c verstage-y += monotonic_timer.c verstage-y += pch.c +verstage-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-y += pmutil.c verstage-y += bootblock/i2c.c

1 0

Patch set updated for coreboot: nb/intel/i945/gma.c: Homogenize code for PCI IDs.
by HAOUAS Elyes 28 Oct '16

28 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17174 -gerrit commit 727b394c740de6aab71d6fcb8dff6aab6e0c68a0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 28 10:56:59 2016 +0200 nb/intel/i945/gma.c: Homogenize code for PCI IDs. Change-Id: Ic01565cb730c49a5fe77c8f4990276970964f101 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/gma.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index aefec8f..cce1fe9 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -748,16 +748,26 @@ static struct device_operations gma_func1_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 }; +static const unsigned short i945_gma_func0_ids[] = { + 0x2772, /* 82945G/GZ Integrated Graphics Controller */ + 0x27a2, /* Mobile 945GM/GMS Express Integrated Graphics Controller*/ + 0x27ae, /* Mobile 945GSE Express Integrated Graphics Controller */ + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x27a6, /* Mobile 945GM/GMS/GME Express Integrated Graphics Controller */ + 0 +}; static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, };

1 0

Patch set updated for coreboot: nb/intel/i945/gma.c: Homogenize code for PCI IDs.
by HAOUAS Elyes 28 Oct '16

28 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17174 -gerrit commit 040c3f72665ac0c6cb830a4dea0e853bf38a6fb6 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 28 10:56:59 2016 +0200 nb/intel/i945/gma.c: Homogenize code for PCI IDs. Change-Id: Ic01565cb730c49a5fe77c8f4990276970964f101 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/gma.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index aefec8f..cce1fe9 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -748,16 +748,26 @@ static struct device_operations gma_func1_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 }; +static const unsigned short i945_gma_func0_ids[] = { + 0x2772, /* 82945G/GZ Integrated Graphics Controller */ + 0x27a2, /* Mobile 945GM/GMS Express Integrated Graphics Controller*/ + 0x27ae, /* Mobile 945GSE Express Integrated Graphics Controller */ + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x27a6, /* Mobile 945GM/GMS/GME Express Integrated Graphics Controller */ + 0 +}; static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, };

1 0

Patch set updated for coreboot: nb/x4x/raminit.c: Improve crossclock table cosmetics
by Arthur Heymans 28 Oct '16

28 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17170 -gerrit commit be0811a23881e5292de554cec9adc85f196efbfc Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 23:56:08 2016 +0200 nb/x4x/raminit.c: Improve crossclock table cosmetics Change-Id: I3f692c55fdff99aa9eb41eaaea79a41ac93be590 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 87 ++++++++++++++++++++------------ 1 file changed, 55 insertions(+), 32 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index cd5b3b2..fbd6191 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -175,39 +175,62 @@ static void clkcross_ddr2(struct sysinfo *s) u8 i, j; MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); -#define TAB_M667F800 {0x1f1f1f1f, 0x1a07070b, 0x0, 0x10000000, 0x20010208, \ - 0x04080000, 0x10010002, 0x0, 0x0, 0x02000000, \ - 0x04000100, 0x08000000, 0x10200204} -#define TAB_M800F800 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x08010204, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, 0x0, 0x04080102} -#define TAB_M667F1067 {0x6d5b1f1f, 0x0f0f0f0f, 0x0, 0x20000000, 0x80020410, \ - 0x02040008, 0x10000100, 0x0, 0x0, 0x04000000, \ - 0x08000102, 0x20000000, 0x40010208} -#define TAB_M800F1067 {0x07070707, 0x06030303, 0x0, 0x0, 0x08010200, \ - 0x0, 0x04000102, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M1067F1067 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M667F1333 {0x05050303, 0xffffffff, 0xffff0000, 0x0, 0x08020000, \ - 0x0, 0x00020001, 0x0, 0x0, 0x0, 0x08010204, \ - 0x0, 0x04010000} -#define TAB_M800F1333 {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x0, 0x10020400, \ - 0x02000000, 0x00040100, 0x0, 0x0, 0x04080000, \ - 0x00100102, 0x0, 0x08100200} -#define TAB_M1067F1333 {0x0f0f0f0f, 0x5b1f1f6d, 0x0, 0x0, 0x08010204, \ - 0x04000000, 0x00080102, 0x0, 0x0, 0x02000408, \ - 0x00100001, 0x0, 0x04080102} -#define TAB_M1333F1333 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x04080102, 0x0, 0x0, 0x0, 0x0, 0x0, 0x02040801} - static const u32 clkxtab[6][3][13] = { - {{}, {}, {}}, // MEMCLK 400 N/A - {{}, {}, {}}, // MEMCLK 533 N/A - {TAB_M667F800, TAB_M667F1067, TAB_M667F1333, }, - {TAB_M800F800, TAB_M800F1067, TAB_M800F1333, }, - {{}, TAB_M1067F1067, TAB_M1067F1333, }, - {{}, {}, TAB_M1333F1333, }, + /* MEMCLK 400 N/A */ + {{}, {}, {} }, + /* MEMCLK 533 N/A */ + {{}, {}, {} }, + /* MEMCLK 667 + * FSB 800 */ + {{0x1f1f1f1f, 0x1a07070b, 0x00000000, 0x10000000, + 0x20010208, 0x04080000, 0x10010002, 0x00000000, + 0x00000000, 0x02000000, 0x04000100, 0x08000000, + 0x10200204}, + /* FSB 1067 */ + {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, + 0x80020410, 0x02040008, 0x10000100, 0x00000000, + 0x00000000, 0x04000000, 0x08000102, 0x20000000, + 0x40010208}, + /* FSB 1333 */ + {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, + 0x08020000, 0x00000000, 0x00020001, 0x00000000, + 0x00000000, 0x00000000, 0x08010204, 0x00000000, + 0x04010000} }, + /* MEMCLK 800 + * FSB 800 */ + {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, + 0x08010204, 0x00000000, 0x08010204, 0x0000000, + 0x00000000, 0x00000000, 0x00020001, 0x0000000, + 0x04080102}, + /* FSB 1067 */ + {0x07070707, 0x06030303, 0x00000000, 0x00000000, + 0x08010200, 0x00000000, 0x04000102, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, + 0x10020400, 0x02000000, 0x00040100, 0x00000000, + 0x00000000, 0x04080000, 0x00100102, 0x00000000, + 0x08100200} }, + /* MEMCLK 1067 */ + {{}, + /* FSB 1067 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x08010204, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, + 0x08010204, 0x04000000, 0x00080102, 0x00000000, + 0x00000000, 0x02000408, 0x00100001, 0x00000000, + 0x04080102} }, + /* MEMCLK 1333 */ + {{}, {}, + /* FSB 1333 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x04080102, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x02040801} } }; i = (u8)s->selected_timings.mem_clk;

1 0

Patch set updated for coreboot: nb/x4x/raminit.c: Improvement crossclock table cosmetics
by Arthur Heymans 28 Oct '16

28 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17170 -gerrit commit 47be64a25c6788c5d8eb5c93c469ed2f197bc6b4 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 23:56:08 2016 +0200 nb/x4x/raminit.c: Improvement crossclock table cosmetics Change-Id: I3f692c55fdff99aa9eb41eaaea79a41ac93be590 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 87 ++++++++++++++++++++------------ 1 file changed, 55 insertions(+), 32 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index cd5b3b2..fbd6191 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -175,39 +175,62 @@ static void clkcross_ddr2(struct sysinfo *s) u8 i, j; MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); -#define TAB_M667F800 {0x1f1f1f1f, 0x1a07070b, 0x0, 0x10000000, 0x20010208, \ - 0x04080000, 0x10010002, 0x0, 0x0, 0x02000000, \ - 0x04000100, 0x08000000, 0x10200204} -#define TAB_M800F800 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x08010204, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, 0x0, 0x04080102} -#define TAB_M667F1067 {0x6d5b1f1f, 0x0f0f0f0f, 0x0, 0x20000000, 0x80020410, \ - 0x02040008, 0x10000100, 0x0, 0x0, 0x04000000, \ - 0x08000102, 0x20000000, 0x40010208} -#define TAB_M800F1067 {0x07070707, 0x06030303, 0x0, 0x0, 0x08010200, \ - 0x0, 0x04000102, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M1067F1067 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M667F1333 {0x05050303, 0xffffffff, 0xffff0000, 0x0, 0x08020000, \ - 0x0, 0x00020001, 0x0, 0x0, 0x0, 0x08010204, \ - 0x0, 0x04010000} -#define TAB_M800F1333 {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x0, 0x10020400, \ - 0x02000000, 0x00040100, 0x0, 0x0, 0x04080000, \ - 0x00100102, 0x0, 0x08100200} -#define TAB_M1067F1333 {0x0f0f0f0f, 0x5b1f1f6d, 0x0, 0x0, 0x08010204, \ - 0x04000000, 0x00080102, 0x0, 0x0, 0x02000408, \ - 0x00100001, 0x0, 0x04080102} -#define TAB_M1333F1333 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x04080102, 0x0, 0x0, 0x0, 0x0, 0x0, 0x02040801} - static const u32 clkxtab[6][3][13] = { - {{}, {}, {}}, // MEMCLK 400 N/A - {{}, {}, {}}, // MEMCLK 533 N/A - {TAB_M667F800, TAB_M667F1067, TAB_M667F1333, }, - {TAB_M800F800, TAB_M800F1067, TAB_M800F1333, }, - {{}, TAB_M1067F1067, TAB_M1067F1333, }, - {{}, {}, TAB_M1333F1333, }, + /* MEMCLK 400 N/A */ + {{}, {}, {} }, + /* MEMCLK 533 N/A */ + {{}, {}, {} }, + /* MEMCLK 667 + * FSB 800 */ + {{0x1f1f1f1f, 0x1a07070b, 0x00000000, 0x10000000, + 0x20010208, 0x04080000, 0x10010002, 0x00000000, + 0x00000000, 0x02000000, 0x04000100, 0x08000000, + 0x10200204}, + /* FSB 1067 */ + {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, + 0x80020410, 0x02040008, 0x10000100, 0x00000000, + 0x00000000, 0x04000000, 0x08000102, 0x20000000, + 0x40010208}, + /* FSB 1333 */ + {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, + 0x08020000, 0x00000000, 0x00020001, 0x00000000, + 0x00000000, 0x00000000, 0x08010204, 0x00000000, + 0x04010000} }, + /* MEMCLK 800 + * FSB 800 */ + {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, + 0x08010204, 0x00000000, 0x08010204, 0x0000000, + 0x00000000, 0x00000000, 0x00020001, 0x0000000, + 0x04080102}, + /* FSB 1067 */ + {0x07070707, 0x06030303, 0x00000000, 0x00000000, + 0x08010200, 0x00000000, 0x04000102, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, + 0x10020400, 0x02000000, 0x00040100, 0x00000000, + 0x00000000, 0x04080000, 0x00100102, 0x00000000, + 0x08100200} }, + /* MEMCLK 1067 */ + {{}, + /* FSB 1067 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x08010204, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, + 0x08010204, 0x04000000, 0x00080102, 0x00000000, + 0x00000000, 0x02000408, 0x00100001, 0x00000000, + 0x04080102} }, + /* MEMCLK 1333 */ + {{}, {}, + /* FSB 1333 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x04080102, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x02040801} } }; i = (u8)s->selected_timings.mem_clk;

1 0

New patch to review for coreboot: mainboard/intel/kblrvp: Update onboard memory specific configs
by Naresh Solanki 28 Oct '16

28 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17162 -gerrit commit f0adbd63c8c3d8bcf186a7f8d2839c024a21d2de Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Oct 27 21:18:25 2016 +0530 mainboard/intel/kblrvp: Update onboard memory specific configs 1. Update dq, dqs map & Rcomp strength & Rcomp traget. 2. Fix rvp3.sp3.hex byte 2 to 0x1F. Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/spd/rvp3.spd.hex | 4 ++-- src/mainboard/intel/kblrvp/spd/spd_util.c | 20 +++++--------------- 2 files changed, 7 insertions(+), 17 deletions(-) diff --git a/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex index e032411..9be3298 100644 --- a/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex +++ b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex @@ -1,4 +1,4 @@ -24 20 F1 0E 14 11 95 00 00 00 00 03 0B 23 00 00 +24 20 0F 0E 14 11 95 00 00 00 00 03 0B 23 00 00 00 00 0A FF 54 00 00 00 78 00 90 A8 90 10 04 E0 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -13,4 +13,4 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index f29f1e33..cc88301 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -28,8 +28,8 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr) const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } @@ -37,8 +37,8 @@ void mainboard_fill_dqs_map_data(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 6, 5, 4, 7 }, - { 2, 3, 0, 1, 6, 7, 4, 5 } }; + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); } @@ -94,15 +94,5 @@ uintptr_t mainboard_get_spd_data(void) int mainboard_has_dual_channel_mem(void) { - int spd_index; - - spd_index = 0; - - if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN - && spd_index != MIC_SINGLE_CHAN) { - printk(BIOS_INFO, - "Dual channel SPD detected writing second channel\n"); - return 1; - } - return 0; + return 1; }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2016