coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

1 participants
1281 discussions

Patch set updated for coreboot: nb/x4x/raminit.c: Cosmetic improvement of crossclock table
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17170 -gerrit commit 8ce37d13d404a58ecd418e6b7adcc4608589b293 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 23:56:08 2016 +0200 nb/x4x/raminit.c: Cosmetic improvement of crossclock table Change-Id: I3f692c55fdff99aa9eb41eaaea79a41ac93be590 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 87 ++++++++++++++++++++------------ 1 file changed, 55 insertions(+), 32 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index cd5b3b2..fbd6191 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -175,39 +175,62 @@ static void clkcross_ddr2(struct sysinfo *s) u8 i, j; MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); -#define TAB_M667F800 {0x1f1f1f1f, 0x1a07070b, 0x0, 0x10000000, 0x20010208, \ - 0x04080000, 0x10010002, 0x0, 0x0, 0x02000000, \ - 0x04000100, 0x08000000, 0x10200204} -#define TAB_M800F800 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x08010204, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, 0x0, 0x04080102} -#define TAB_M667F1067 {0x6d5b1f1f, 0x0f0f0f0f, 0x0, 0x20000000, 0x80020410, \ - 0x02040008, 0x10000100, 0x0, 0x0, 0x04000000, \ - 0x08000102, 0x20000000, 0x40010208} -#define TAB_M800F1067 {0x07070707, 0x06030303, 0x0, 0x0, 0x08010200, \ - 0x0, 0x04000102, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M1067F1067 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M667F1333 {0x05050303, 0xffffffff, 0xffff0000, 0x0, 0x08020000, \ - 0x0, 0x00020001, 0x0, 0x0, 0x0, 0x08010204, \ - 0x0, 0x04010000} -#define TAB_M800F1333 {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x0, 0x10020400, \ - 0x02000000, 0x00040100, 0x0, 0x0, 0x04080000, \ - 0x00100102, 0x0, 0x08100200} -#define TAB_M1067F1333 {0x0f0f0f0f, 0x5b1f1f6d, 0x0, 0x0, 0x08010204, \ - 0x04000000, 0x00080102, 0x0, 0x0, 0x02000408, \ - 0x00100001, 0x0, 0x04080102} -#define TAB_M1333F1333 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x04080102, 0x0, 0x0, 0x0, 0x0, 0x0, 0x02040801} - static const u32 clkxtab[6][3][13] = { - {{}, {}, {}}, // MEMCLK 400 N/A - {{}, {}, {}}, // MEMCLK 533 N/A - {TAB_M667F800, TAB_M667F1067, TAB_M667F1333, }, - {TAB_M800F800, TAB_M800F1067, TAB_M800F1333, }, - {{}, TAB_M1067F1067, TAB_M1067F1333, }, - {{}, {}, TAB_M1333F1333, }, + /* MEMCLK 400 N/A */ + {{}, {}, {} }, + /* MEMCLK 533 N/A */ + {{}, {}, {} }, + /* MEMCLK 667 + * FSB 800 */ + {{0x1f1f1f1f, 0x1a07070b, 0x00000000, 0x10000000, + 0x20010208, 0x04080000, 0x10010002, 0x00000000, + 0x00000000, 0x02000000, 0x04000100, 0x08000000, + 0x10200204}, + /* FSB 1067 */ + {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, + 0x80020410, 0x02040008, 0x10000100, 0x00000000, + 0x00000000, 0x04000000, 0x08000102, 0x20000000, + 0x40010208}, + /* FSB 1333 */ + {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, + 0x08020000, 0x00000000, 0x00020001, 0x00000000, + 0x00000000, 0x00000000, 0x08010204, 0x00000000, + 0x04010000} }, + /* MEMCLK 800 + * FSB 800 */ + {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, + 0x08010204, 0x00000000, 0x08010204, 0x0000000, + 0x00000000, 0x00000000, 0x00020001, 0x0000000, + 0x04080102}, + /* FSB 1067 */ + {0x07070707, 0x06030303, 0x00000000, 0x00000000, + 0x08010200, 0x00000000, 0x04000102, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, + 0x10020400, 0x02000000, 0x00040100, 0x00000000, + 0x00000000, 0x04080000, 0x00100102, 0x00000000, + 0x08100200} }, + /* MEMCLK 1067 */ + {{}, + /* FSB 1067 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x08010204, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, + 0x08010204, 0x04000000, 0x00080102, 0x00000000, + 0x00000000, 0x02000408, 0x00100001, 0x00000000, + 0x04080102} }, + /* MEMCLK 1333 */ + {{}, {}, + /* FSB 1333 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x04080102, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x02040801} } }; i = (u8)s->selected_timings.mem_clk;

1 0

Patch set updated for coreboot: Makefile.inc: Update what-jenkins-does target
by Martin Roth 27 Oct '16

27 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17014 -gerrit commit 6da1c3e69f0528039986ddc5d0714546454ef99f Author: Martin Roth <martinroth(a)google.com> Date: Wed Oct 12 14:40:26 2016 -0600 Makefile.inc: Update what-jenkins-does target - Update the junit.xml target to make it less util specific - Add builds of coreboot internal payloads: nvramcui and coreinfo Change-Id: I97fda909065659ab7fa4c8ee00d936d97b255bf7 Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index c7f1d04..25ef92d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1006,18 +1006,18 @@ PHONY+=check-ramstage-overlaps endif junit.xml: - echo "Building $(UTIL)" + echo "Building $(BLD)" echo '<?xml version="1.0" encoding="utf-8"?><testsuite>' > $@.tmp - echo "<testcase classname='$(UTIL)' name='$(UTIL)'>" >> $@.tmp - -$(MAKE) -j $(CPUS) -C "util/$(UTIL)" clean distclean > $@.tmp.2 2>&1 - $(MAKE) -j $(CPUS) -C "util/$(UTIL)" $(MAKETARGET) >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ + echo "<testcase classname='$(BLD)' name='$(BLD)'>" >> $@.tmp + -$(MAKE) -j $(CPUS) -C "$(BLD_DIR)$(BLD)" clean distclean > $@.tmp.2 2>&1 + $(MAKE) -j $(CPUS) -C "$(BLD_DIR)$(BLD)" $(MAKETARGET) >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ cat $@.tmp.2; \ if [ "$$type" = "failure" ]; then \ echo "<failure type='buildFailed'>" >> $@.tmp; \ - echo "Building $(UTIL) Failed"; \ + echo "Building $(BLD) Failed"; \ else \ echo "<$$type>" >> $@.tmp; \ - echo "Building $(UTIL) Succeeded"; \ + echo "Building $(BLD) Succeeded"; \ fi; \ echo '<![CDATA[' >> $@.tmp; \ cat $@.tmp.2 >> $@.tmp; \ @@ -1025,7 +1025,7 @@ junit.xml: rm -f $@.tmp.2 echo "</testcase>" >> $@.tmp echo "</testsuite>" >> $@.tmp - mv $@.tmp "util/$(UTIL)/$@" + mv $@.tmp "$(BLD_DIR)$(BLD)/$@" echo TOOLLIST= \ @@ -1044,5 +1044,7 @@ what-jenkins-does: util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) - $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) - $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) UTIL="romcc" MFLAGS= MAKEFLAGS= MAKETARGET=test junit.xml + $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=util/ BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) + $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/ BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml + $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/ BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml + $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=util/ BLD=romcc MFLAGS= MAKEFLAGS= MAKETARGET=test junit.xml

1 0

New patch to review for coreboot: nb/x4x/raminit.c: cosmetic improvement of crossclock table
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17170 -gerrit commit 3f889215490e698d4db0b97ea7fd148c1d7bb9c4 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 27 23:56:08 2016 +0200 nb/x4x/raminit.c: cosmetic improvement of crossclock table Change-Id: I3f692c55fdff99aa9eb41eaaea79a41ac93be590 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 87 ++++++++++++++++++++------------ 1 file changed, 55 insertions(+), 32 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index cd5b3b2..fbd6191 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -175,39 +175,62 @@ static void clkcross_ddr2(struct sysinfo *s) u8 i, j; MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); -#define TAB_M667F800 {0x1f1f1f1f, 0x1a07070b, 0x0, 0x10000000, 0x20010208, \ - 0x04080000, 0x10010002, 0x0, 0x0, 0x02000000, \ - 0x04000100, 0x08000000, 0x10200204} -#define TAB_M800F800 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x08010204, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, 0x0, 0x04080102} -#define TAB_M667F1067 {0x6d5b1f1f, 0x0f0f0f0f, 0x0, 0x20000000, 0x80020410, \ - 0x02040008, 0x10000100, 0x0, 0x0, 0x04000000, \ - 0x08000102, 0x20000000, 0x40010208} -#define TAB_M800F1067 {0x07070707, 0x06030303, 0x0, 0x0, 0x08010200, \ - 0x0, 0x04000102, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M1067F1067 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, \ - 0x0, 0x02040801} -#define TAB_M667F1333 {0x05050303, 0xffffffff, 0xffff0000, 0x0, 0x08020000, \ - 0x0, 0x00020001, 0x0, 0x0, 0x0, 0x08010204, \ - 0x0, 0x04010000} -#define TAB_M800F1333 {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x0, 0x10020400, \ - 0x02000000, 0x00040100, 0x0, 0x0, 0x04080000, \ - 0x00100102, 0x0, 0x08100200} -#define TAB_M1067F1333 {0x0f0f0f0f, 0x5b1f1f6d, 0x0, 0x0, 0x08010204, \ - 0x04000000, 0x00080102, 0x0, 0x0, 0x02000408, \ - 0x00100001, 0x0, 0x04080102} -#define TAB_M1333F1333 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ - 0x0, 0x04080102, 0x0, 0x0, 0x0, 0x0, 0x0, 0x02040801} - static const u32 clkxtab[6][3][13] = { - {{}, {}, {}}, // MEMCLK 400 N/A - {{}, {}, {}}, // MEMCLK 533 N/A - {TAB_M667F800, TAB_M667F1067, TAB_M667F1333, }, - {TAB_M800F800, TAB_M800F1067, TAB_M800F1333, }, - {{}, TAB_M1067F1067, TAB_M1067F1333, }, - {{}, {}, TAB_M1333F1333, }, + /* MEMCLK 400 N/A */ + {{}, {}, {} }, + /* MEMCLK 533 N/A */ + {{}, {}, {} }, + /* MEMCLK 667 + * FSB 800 */ + {{0x1f1f1f1f, 0x1a07070b, 0x00000000, 0x10000000, + 0x20010208, 0x04080000, 0x10010002, 0x00000000, + 0x00000000, 0x02000000, 0x04000100, 0x08000000, + 0x10200204}, + /* FSB 1067 */ + {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, + 0x80020410, 0x02040008, 0x10000100, 0x00000000, + 0x00000000, 0x04000000, 0x08000102, 0x20000000, + 0x40010208}, + /* FSB 1333 */ + {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, + 0x08020000, 0x00000000, 0x00020001, 0x00000000, + 0x00000000, 0x00000000, 0x08010204, 0x00000000, + 0x04010000} }, + /* MEMCLK 800 + * FSB 800 */ + {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, + 0x08010204, 0x00000000, 0x08010204, 0x0000000, + 0x00000000, 0x00000000, 0x00020001, 0x0000000, + 0x04080102}, + /* FSB 1067 */ + {0x07070707, 0x06030303, 0x00000000, 0x00000000, + 0x08010200, 0x00000000, 0x04000102, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, + 0x10020400, 0x02000000, 0x00040100, 0x00000000, + 0x00000000, 0x04080000, 0x00100102, 0x00000000, + 0x08100200} }, + /* MEMCLK 1067 */ + {{}, + /* FSB 1067 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x08010204, 0x00000000, + 0x00000000, 0x00000000, 0x00020001, 0x00000000, + 0x02040801}, + /* FSB 1333 */ + {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, + 0x08010204, 0x04000000, 0x00080102, 0x00000000, + 0x00000000, 0x02000408, 0x00100001, 0x00000000, + 0x04080102} }, + /* MEMCLK 1333 */ + {{}, {}, + /* FSB 1333 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, + 0x04080102, 0x00000000, 0x04080102, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x02040801} } }; i = (u8)s->selected_timings.mem_clk;

1 0

Patch set updated for coreboot: pci_ids.h: Correct recent AMD ID names
by Marshall Dawson 27 Oct '16

27 Oct '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17169 -gerrit commit 4d1ab85918f61630adfb7292c01616bf1f1debf1 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 20:46:08 2016 -0600 pci_ids.h: Correct recent AMD ID names Adjust the names to match AMD's convention for family and model. This patch is relevant for: Trinity & Richland: Family 15h Models 00h-0Fh Carrizo: Family 15h Models 60h-6Fh Mullins & Steppe Eagle: Family 16h Models 30h-3Fh Change-Id: I613b84ed438fb70269d789c9901f1928b5500757 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/include/device/pci_ids.h | 6 +++--- src/northbridge/amd/agesa/family15rl/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/pi/00660F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index cd0a66e..94955fc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -285,11 +285,11 @@ #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 -#define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400 +#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT 0x1400 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT 0x141A #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 -#define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT 0x1566 -#define PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT 0x1570 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 +#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT 0x1570 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT 0x15B0 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 5a208d2..a8c2807 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -590,7 +590,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT, }; static const struct pci_driver family10_northbridge __pci_driver = { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 4279ba2..ae1efb4 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -589,7 +589,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT, }; static const struct pci_driver family10_northbridge __pci_driver = { diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index c446419..115d760 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -581,7 +581,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, }; static void fam15_finalize(void *chip_info) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e8bc425..5b83721 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -590,7 +590,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family16_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT, + .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, }; static const struct pci_driver family10_northbridge __pci_driver = {

1 0

New patch to review for coreboot: pci_ids: Correct recent AMD ID names
by Marshall Dawson 27 Oct '16

27 Oct '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17169 -gerrit commit 5415252d04bc330fb7d991ed667ddedb23226144 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 20:46:08 2016 -0600 pci_ids: Correct recent AMD ID names Adjust the names to match AMD's convention for family and model. This patch is relevant for: Trinity & Richland: Family 15h Models 00h-0Fh Carrizo: Family 15h Models 60h-6Fh Mullins & Steppe Eagle: Family 16h Models 30h-3Fh Change-Id: I613b84ed438fb70269d789c9901f1928b5500757 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/include/device/pci_ids.h | 6 +++--- src/northbridge/amd/agesa/family15rl/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/pi/00660F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index cd0a66e..94955fc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -285,11 +285,11 @@ #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 -#define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400 +#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT 0x1400 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT 0x141A #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 -#define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT 0x1566 -#define PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT 0x1570 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 +#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT 0x1570 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT 0x15B0 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 5a208d2..a8c2807 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -590,7 +590,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT, }; static const struct pci_driver family10_northbridge __pci_driver = { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 4279ba2..ae1efb4 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -589,7 +589,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT, }; static const struct pci_driver family10_northbridge __pci_driver = { diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index c446419..115d760 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -581,7 +581,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, }; static void fam15_finalize(void *chip_info) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e8bc425..5b83721 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -590,7 +590,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family16_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT, + .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, }; static const struct pci_driver family10_northbridge __pci_driver = {

1 0

Patch set updated for coreboot: payloads/external/Makefile.inc: Clean up targets
by Martin Roth 27 Oct '16

27 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17047 -gerrit commit c08a6a40787a4a8bfe0d26dd2501f821d9181206 Author: Martin Roth <martinroth(a)google.com> Date: Mon Oct 17 10:21:17 2016 -0600 payloads/external/Makefile.inc: Clean up targets - Combine the short target name with the filename. - All targets depend on top level dotconfig. - Payload targets depend on their payload .config. - Add .PHONY target for the short target names. - Add additional short target names grub, uboot, and memtest. - Remove reversed dependencies of config files on the output. - Set SeaBIOS vgabios target at same level as main SeaBIOS target to prevent rebuilds because of the vbios being included. This fixes an issue with SeaBIOS and Filo rebuilding every time. Change-Id: Ied3b4ea7edfd3b4183ff788f57f484c462b63b5b Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/Makefile.inc | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index e4d3e12..90233ae 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -16,14 +16,20 @@ ## ###################################################################### + +SEABIOS_DIR=payloads/external/SeaBIOS/seabios +SEABIOS_OUT=$(SEABIOS_DIR)/out +FILO_DIR=payloads/external/FILO/filo +FILO_OUT=$(FILO_DIR)/build + # set up payload config and version files for later inclusion ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) -PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config -PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/autoversion.h +PAYLOAD_CONFIG=$(SEABIOS_DIR)/.config +PAYLOAD_VERSION=$(SEABIOS_OUT)/autoversion.h endif ifeq ($(CONFIG_PAYLOAD_FILO),y) -PAYLOAD_CONFIG=payloads/external/FILO/filo/.config -PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h +PAYLOAD_CONFIG=$(FILO_DIR)/.config +PAYLOAD_VERSION=$(FILO_OUT)/version.h endif ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config @@ -60,10 +66,12 @@ cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_revision payload_revision-file := $(PAYLOAD_VERSION) payload_revision-type := raw +.PHONY: seabios depthcharge grub2 grub tint memtest u-boot uboot ipxe + # SeaBIOS SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) -payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) +$(SEABIOS_OUT)/vgabios.bin $(SEABIOS_OUT)/bios.bin.elf seabios: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/SeaBIOS \ HOSTCC="$(HOSTCC)" \ CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \ @@ -83,10 +91,6 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) -payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios -payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf -payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf - # add a SeaBIOS bootorder file ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),) cbfs-files-y += bootorder @@ -96,15 +100,14 @@ endif # Depthcharge -payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) - +payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/depthcharge \ BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) \ MFLAGS= MAKEFLAGS= # FILO -filo: +$(FILO_OUT)/filo.elf filo: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/FILO \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ @@ -112,13 +115,9 @@ filo: CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) -payloads/external/FILO/filo/build/filo.elf: filo -payloads/external/FILO/filo/.config: filo -payloads/external/FILO/filo/build/version.h: filo - # Grub -grub2: +payloads/external/GRUB2/grub2/build/default_payload.elf grub2 grub: $(DOTCONFIG) $(MAKE) -C payloads/external/GRUB2 \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ @@ -126,11 +125,9 @@ grub2: CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER) \ CONFIG_GRUB2_EXTRA_MODULES=$(CONFIG_GRUB2_EXTRA_MODULES) -payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 - # U-Boot -payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) +payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot uboot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) @@ -156,7 +153,7 @@ ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD) endif -payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG) +payloads/external/Memtest86Plus/memtest86plus/memtest memtest: $(DOTCONFIG) $(MAKE) -C payloads/external/Memtest86Plus all \ CC="$(CC_x86_32)" \ LD="$(LD_x86_32)" \

1 0

Patch merged into coreboot/master: util/lint/lint: Show lint script output as it's running
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 78f73353a3c0b7e3e59d0372f02dc1c37b226ac4 Author: Martin Roth <martinroth(a)google.com> Date: Mon Oct 24 13:36:32 2016 -0700 util/lint/lint: Show lint script output as it's running The checkpatch script takes a really long time to run, and when the output is buffered to wait until it's finished, it's hard to tell if the script is actually doing anything. Instead, use tee to log the output and display it at the same time. Change-Id: I3cf36e5e6ca28584103888ee1c6f125320ac068a Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/17125 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17125 for details. -gerrit

1 0

Patch set updated for coreboot: nb/intel/i945: make pci_mmio_size a devicetree parameter
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit 7650f6ec535e8969561be2ba7c1daedcdd20b28a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 23 +++++++++++++++++++++-- 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..c6d80e6 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..f442bf2 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1500,6 +1504,22 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) } } +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE / 128; + else + return cfg->pci_mmio_size / 128; +} + static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; @@ -1542,8 +1562,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + tolud = MIN(((0x20 - get_mmio_size()) << 3), tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

1 0

Patch set updated for coreboot: mb/gigabyte/ga-945gcm-s2l: add mainboard
by Arthur Heymans 27 Oct '16

27 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17033 -gerrit commit b0d59c909677ebce6219ea038ee8d84fe3b94a8b Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 15 18:00:22 2016 +0200 mb/gigabyte/ga-945gcm-s2l: add mainboard Startpoint was Intel d945gclf, which has same chipset and Gigabyte ga-g41m-es2l which has same Superio. What works and is tested: * PCI slot; * PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card; * onboard VGA output (only textmode implemented) with native graphic init; * 533, 800, 1067MHz CPU (1333MHz is unsupported by the chipset); * serial output during and after boot. What does not work: * resume from suspend (does not work for d945gclf either). Quirks: * The Realtek ethernet card requires a reset which currently also hardcodes a MAC adress. This board was only tested with the SeaBIOS payload due to flash size constraints (512KB) and with GNU/Linux. Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 58 ++++++ src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name | 2 + src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc | 1 + src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl | 51 +++++ .../gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl | 75 +++++++ .../gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl | 44 +++++ .../gigabyte/ga-945gcm-s2l/acpi/mainboard.asl | 30 +++ .../gigabyte/ga-945gcm-s2l/acpi/platform.asl | 48 +++++ .../gigabyte/ga-945gcm-s2l/acpi/superio.asl | 1 + .../gigabyte/ga-945gcm-s2l/acpi/thermal.asl | 1 + src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c | 32 +++ .../gigabyte/ga-945gcm-s2l/board_info.txt | 6 + src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default | 7 + src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout | 122 ++++++++++++ src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c | 20 ++ src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 160 +++++++++++++++ src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl | 53 +++++ src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c | 37 ++++ src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 217 +++++++++++++++++++++ 19 files changed, 965 insertions(+) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig new file mode 100644 index 0000000..b41becc --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans <arthur(a)ahemans.xyz +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if BOARD_GIGABYTE_GA_945GCM_S2L + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_ITE_IT8718F + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_EDID + select REALTEK_8168_RESET + +config MAINBOARD_DIR + string + default gigabyte/ga-945gcm-s2l + +config MAINBOARD_PART_NUMBER + string + default "GA-945GCM-S2L" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 2 + +endif # BOARD_GIGABYTE_GA_945GCM_S2L diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name new file mode 100644 index 0000000..95baebe --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_945GCM_S2L + bool "GA-945GCM-S2L" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl new file mode 100644 index 0000000..5362bb2 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + // _REG method requires that an operation region be defined. + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..4aaa33f --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 17 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 19 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 17 }, + Package() { 0x001fffff, 2, 0, 18 }, + Package() { 0x001fffff, 3, 0, 19 }, + + }) + + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..cc229a5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x14 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 }, + + }) +} Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + }) +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl new file mode 100644 index 0000000..0454c3f --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl new file mode 100644 index 0000000..21eb3df --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/thermal.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/thermal.asl new file mode 100644 index 0000000..4107d3b --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/thermal.asl @@ -0,0 +1 @@ +/* dummy */ \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c new file mode 100644 index 0000000..677ebcf --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <arch/ioapic.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/board_info.txt b/src/mainboard/gigabyte/ga-945gcm-s2l/board_info.txt new file mode 100644 index 0000000..70cbe41 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2669#ov +Release year: 2007 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default new file mode 100644 index 0000000..ab7aac1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout new file mode 100644 index 0000000..47f48dd --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout @@ -0,0 +1,122 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# RAM initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c new file mode 100644 index 0000000..f683756 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <arch/x86/include/arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb new file mode 100644 index 0000000..a993848 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -0,0 +1,160 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x + device lapic 0xACAC off end + end + end + + device domain 0 on + device pci 00.0 on # host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 on # i945 PCIe root port + subsystemid 0x1458 0x5000 + ioapic_irq 2 INTA 0x10 + end + device pci 02.0 on # vga controller + subsystemid 0x1458 0xd000 + ioapic_irq 2 INTA 0x10 + end + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8c" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x85" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi0_routing" = "1" + register "gpi1_routing" = "1" + register "gpi2_routing" = "1" + register "gpi3_routing" = "1" + register "gpi4_routing" = "1" + register "gpi5_routing" = "1" + register "gpi6_routing" = "1" + register "gpi7_routing" = "1" + register "gpi8_routing" = "1" + register "gpi9_routing" = "1" + register "gpi10_routing" = "1" + register "gpi11_routing" = "1" + register "gpi12_routing" = "1" + register "gpi13_routing" = "2" + register "gpi14_routing" = "1" + register "gpi15_routing" = "1" + + register "gpe0_en" = "0" + + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + register "c3_latency" = "85" + + register "p_cnt_throttling_supported" = "0" + + device pci 1b.0 on # High Definition Audio + ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + #device pci 1c.2 off end # PCIe port 3 + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on # USB UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # USB UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # USB UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1d.3 on # USB UHCI + ioapic_irq 2 INTD 0x13 + end + device pci 1d.7 on # USB2 EHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on end # PCI bridge + + device pci 1f.0 on # LPC bridge + ioapic_irq 2 INTA 0x10 + chip superio/ite/it8718f # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + io 0x62 = 0 + drq 0x74 = 4 + irq 0xf0 = 0x08 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0x00 + io 0x62 = 0x000 + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x0a + irq 0xf3 = 0x00 + irq 0xf4 = 0x80 + irq 0xf5 = 0x20 + irq 0xf6 = 0x3e + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 0 + irq 0x71 = 2 + irq 0xf0 = 0 + end + end + end + device pci 1f.1 on # IDE + ioapic_irq 2 INTB 0x11 + end + device pci 1f.2 on # SATA + ioapic_irq 2 INTC 0x12 + end + device pci 1f.3 on # SMBus + ioapic_irq 2 INTD 0x13 + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl new file mode 100644 index 0000000..187481a --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + //#include "acpi/thermal.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c new file mode 100644 index 0000000..1b57dfa --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0662, /* Vendor ID */ + 0x1458a002, /* Subsystem ID */ + 0x00000009, /* Number of entries */ + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19830), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c31), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), + AZALIA_PIN_CFG(0, 0x1e, 0x014b6120), +}; + +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c new file mode 100644 index 0000000..2965ff4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -0,0 +1,217 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/ite/it8718f/it8718f.h> +#include <superio/ite/common/ite.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +void setup_ich7_gpios(void) +{ + /* TODO: This is highly board specific and should be moved */ + printk(BIOS_DEBUG, " GPIOS..."); + /* General Registers */ + outl(0x1f15f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe2fefc03, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00400000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000c7, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000000f2, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void setup_sio(void) +{ + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x40); + ite_reg_write(GPIO_DEV, 0x26, 0x3f); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x88); + ite_reg_write(GPIO_DEV, 0x2c, 0x1c); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x38); + ite_reg_write(GPIO_DEV, 0xb1, 0x01); + ite_reg_write(GPIO_DEV, 0xb8, 0x80); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc3, 0x00); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x4a); + + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + ite_reg_write(EC_DEV, 0x30, 0xff); // Enable +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + // Enable COM1 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d); + // Enable SuperIO Power Management Events + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801); +} + +static void rcba_config(void) +{ + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Disable unused devices */ + RCBA32(0x3418) = 0x003c0061; + + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030509; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void mainboard_romstage_entry(unsigned long bist) +{ + int s3resume = 0, boot_mode = 0; + + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + /* Enable SuperIO PM */ + setup_sio(); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected.\n"); + boot_mode = 1; + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(s3resume ? 2 : boot_mode, NULL); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +}

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Allow use of MRC cache data in recovery
by Andrey Petrov 27 Oct '16

27 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17165 -gerrit commit 244f85bfb7aea053092a722a2b2818cf03719408 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 27 10:12:22 2016 -0700 drivers/intel/fsp2_0: Allow use of MRC cache data in recovery Add a configuration option to allow using MRC cache in recovery boot, off by default. This can be overridden by Chrome EC if it requests retrain. BUG=chrome-os-partner:56643 BRANCH=none TEST=invoke power-alt-refresh key combination, notice memory is retrained in recovery Change-Id: I31a87afc8a70c17e488c06e42da4acbb2dde3f5d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +++++++ src/drivers/intel/fsp2_0/memory_init.c | 9 +++++++-- src/soc/intel/apollolake/Kconfig | 1 + 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index c653148..75e3901 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -94,4 +94,11 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n +config FSP_RECOVERY_USE_MRCCACHE + bool "Use MRC cache in recovery boot" + depends on CACHE_MRC_SETTINGS + default n + help + Select yes if you want recovery boot to use MRC cache. + endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0a22ce..70379c3 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -113,12 +113,17 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - /* Don't use saved training data when recovery mode is enabled. */ - if (vboot_recovery_mode_enabled()) { + if (!IS_ENABLED(CONFIG_FSP_RECOVERY_USE_MRCCACHE)) { printk(BIOS_SPEW, "Recovery mode. Not using MRC cache.\n"); return; } + /* If recovery with full retrain is requested do not load cache */ + if (vboot_recovery_mode_memory_retrain()) { + printk(BIOS_SPEW, "Recovery with forced memory retrain.\n"); + return; + } + if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { printk(BIOS_SPEW, "MRC cache was not found\n"); return; diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 187214a..39cab36 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -74,6 +74,7 @@ config CHROMEOS select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VIRTUAL_DEV_SWITCH + select FSP_RECOVERY_USE_MRCCACHE config TPM_ON_FAST_SPI bool

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2016