coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: util/lint/lint: Show lint script output as it's running
by Martin Roth 27 Oct '16

27 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17125 -gerrit commit 6e6bb310e6a585a0826ffc1b8a6df405691abf35 Author: Martin Roth <martinroth(a)google.com> Date: Mon Oct 24 13:36:32 2016 -0700 util/lint/lint: Show lint script output as it's running The checkpatch script takes a really long time to run, and when the output is buffered to wait until it's finished, it's hard to tell if the script is actually doing anything. Instead, use tee to log the output and display it at the same time. Change-Id: I3cf36e5e6ca28584103888ee1c6f125320ac068a Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/util/lint/lint b/util/lint/lint index 826685d..772d8bd 100755 --- a/util/lint/lint +++ b/util/lint/lint @@ -50,15 +50,14 @@ for script in "$(dirname "$0")/${1}-"*; do grep "^# DESCR:" "$script" | sed "s,.*DESCR: *,," echo "========" junit_write " <testcase classname='lint' name='$(basename "$script")'>" - $script > "$LINTLOG" + $script | tee "$LINTLOG" #if the lint script gives any output, that's a failure if [ "$(wc -l < "$LINTLOG")" -eq 0 ]; then echo "success" junit_write " <system-out><![CDATA[success]]></system-out>" else - echo "test failed:" - cat "$LINTLOG" + echo "test failed" junit_write " <failure type='testFailed'><![CDATA[" junit_write "$(cat "$LINTLOG")" junit_write "]]></failure>"

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Patch merged into coreboot/master: soc/intel/skylake: make inline function static
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 38f5a577ca48bb0608544d8922f7894197293b82 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Fri Oct 21 15:44:23 2016 +0530 soc/intel/skylake: make inline function static Make bootblock_fsp_temp_ram_init as static inline. Change-Id: Iacf24728a45fc6554d7a425feecc25e55ac5da6c Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17084 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17084 for details. -gerrit

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Patch merged into coreboot/master: driver/intel/fsp2_0: Reset on invalid stage cache.
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit d5353e36483daef462fd37e47aa4c0524f868ace Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Mon Oct 24 13:01:28 2016 +0530 driver/intel/fsp2_0: Reset on invalid stage cache. Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is invalid during S3 resume. Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17112 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17112 for details. -gerrit

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New patch to review for coreboot: soc/intel/skylake: don't hardcode GPE0 standard reg
by Aaron Durbin 27 Oct '16

27 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17160 -gerrit commit e0741fce00818e4ded95c030a09ad2bb5943ba23 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 27 09:53:17 2016 -0500 soc/intel/skylake: don't hardcode GPE0 standard reg While using '3' is fine for the standard gpe0 for skylake, I want to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX without the hard coded index. If that does happen now things will still work, but it may just not match the hardware proper. BUG=chrome-os-partner:58666 Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index fc4f58c..54468d2 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -598,6 +598,7 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) uint32_t pm1_en; uint32_t gpe0_std; int i; + const int last_index = GPE0_REG_MAX - 1; ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps == NULL) @@ -622,9 +623,9 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) /* Mask off GPE0 status bits that are not enabled */ *gpe0 = &gpe0_sts[0]; - for (i = 0; i < (GPE0_REG_MAX-1); i++) + for (i = 0; i < last_index; i++) gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; - gpe0_sts[3] = ps->gpe0_sts[3] & gpe0_std; + gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std; return GPE0_REG_MAX; }

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Patch merged into coreboot/master: mainboard/google/reef: drop disabling periodic training for micron
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 6ea1500e48aa86ca0ae5da2227a65a3e5b5420db Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 25 15:19:54 2016 -0500 mainboard/google/reef: drop disabling periodic training for micron In anticipation of getting fixed material remove the disabling of periodic training for MT53B512M32D2NP and MT53B256M32D1NP. BUG=chrome-os-partner:59003 Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17130 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17130 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: clarify memory part number details
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit ed5b8bf3edcb85df3613ac8b47d1ef61eeb101ce Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 25 15:16:26 2016 -0500 mainboard/google/reef: clarify memory part number details Explain the reasoning for the part_num strings used in the memory SKU table explaining the necessity of keeping mosys in sync with the strings used. It's possible that actual part numbers could change as the higher speed material gets cheaper, for example. BUG=chrome-os-partner:58966 Change-Id: If895e52791dc56e283261b3438106116b8b2ea05 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17129 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17129 for details. -gerrit

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Patch merged into coreboot/master: skylake: Add support for eSPI SMI events
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 8d01902bb78e25c750f796ea2645d17672f4b9a3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 19:58:27 2016 -0700 skylake: Add support for eSPI SMI events Add the necessary infrastructure to support eSPI SMI events, and a mainboard handler to pass control to the EC. BUG=chrome-os-partner:58666 TEST=tested on eve board with eSPI enabled, verified that lid close event from the EC during firmware will result in an SMI and shut down the system. Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17134 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17134 for details. -gerrit

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Patch merged into coreboot/master: skylake: Prepare GPE for use in bootblock
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit f0ba2259b84c1f5083dab14925351ddf8b245e11 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:03:56 2016 -0700 skylake: Prepare GPE for use in bootblock Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17135 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17135 for details. -gerrit

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Patch merged into coreboot/master: skylake: Support for early I2C TPM driver
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:05:31 2016 -0700 skylake: Support for early I2C TPM driver Add the SOC definition for acpi_get_gpe() so it can be used by the I2C TPM driver. Also add the I2C support code to verstage so it can get used by vboot. BUG=chrome-os-partner:58666 TEST=boot with I2C TPM on skylake board Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17136 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17136 for details. -gerrit

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Patch merged into coreboot/master: skylake: Fix wake source reporting with Deep S3
by gerrit＠coreboot.org 27 Oct '16

27 Oct '16

the following patch was just integrated into master: commit 95f9020de162f29b8b30af361339c94c298acf52 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:07:22 2016 -0700 skylake: Fix wake source reporting with Deep S3 The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17137 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17137 for details. -gerrit

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coreboot-gerrit October 2016