coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

Patch set updated for coreboot: Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU
by Arthur Heymans 26 Oct '16

26 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17122 -gerrit commit 1cf989c66c9aac1631a1381771b3872413bbcf15 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Oct 25 17:11:16 2016 +0200 Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU On QEMU using SeaVGABIOS breaks some bootloaders, e.g. ISOLINUX does not work and GRUB works but is forced in txtmode, instead of graphical mode. Change-Id: If31d4e5ed19cbeed3f8f9dbc23cc738dd55986e5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- payloads/external/SeaBIOS/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index a9d701d..0780820 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -53,7 +53,7 @@ config SEABIOS_THREAD_OPTIONROMS config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" - default y + default y if !VENDOR_EMULATION depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT bool help

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Patch set updated for coreboot: pcengines/apu1: Add RS485 configuration
by Kyösti Mälkki 26 Oct '16

26 Oct '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14998 -gerrit commit 4da018dc2aa63bf68a96c49cc97ef2c81ff9403f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 13 15:01:15 2015 +0300 pcengines/apu1: Add RS485 configuration In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 6 ++++++ src/mainboard/pcengines/apu1/mainboard.c | 23 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index e9aab8c..3099d14 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -95,6 +95,9 @@ config APU1_PINMUX_UART_C endchoice +config UART_C_RS485 + bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C + choice prompt "J19 pins 11-20" default APU1_PINMUX_OFF_D @@ -110,4 +113,7 @@ config APU1_PINMUX_UART_D endchoice +config UART_D_RS485 + bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 96b2020..055cd58 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -158,6 +158,28 @@ static void config_gpio_mux(void) gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; } +static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) +{ + struct resource *res; + res = new_resource(dev, reg); + res->base = val; + res->size = 0; + res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; +} + +static void config_addon_uart(void) +{ + struct device *uart; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + if (uart && uart->enabled && CONFIG_UART_C_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + if (uart && uart->enabled && CONFIG_UART_D_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); +} + /** * TODO * SB CIMx callback @@ -182,6 +204,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); + config_addon_uart(); /* Power off unused clock pins of GPP PCIe devices */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);

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Patch set updated for coreboot: pcengines/apu1: Add RS485 configuration
by Kyösti Mälkki 26 Oct '16

26 Oct '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14998 -gerrit commit cc79628748e0fcee6aa8bf39bde62668d0c33466 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 13 15:01:15 2015 +0300 pcengines/apu1: Add RS485 configuration In RS485 mode #RTS line acts as a transceiver direction control. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 6 ++++++ src/mainboard/pcengines/apu1/mainboard.c | 23 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index e9aab8c..3099d14 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -95,6 +95,9 @@ config APU1_PINMUX_UART_C endchoice +config UART_C_RS485 + bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C + choice prompt "J19 pins 11-20" default APU1_PINMUX_OFF_D @@ -110,4 +113,7 @@ config APU1_PINMUX_UART_D endchoice +config UART_D_RS485 + bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 96b2020..055cd58 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -158,6 +158,28 @@ static void config_gpio_mux(void) gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; } +static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) +{ + struct resource *res; + res = new_resource(dev, reg); + res->base = val; + res->size = 0; + res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; +} + +static void config_addon_uart(void) +{ + struct device *uart; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + if (uart && uart->enabled && CONFIG_UART_C_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + if (uart && uart->enabled && CONFIG_UART_D_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); +} + /** * TODO * SB CIMx callback @@ -182,6 +204,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); + config_addon_uart(); /* Power off unused clock pins of GPP PCIe devices */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);

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Patch merged into coreboot/master: intel/skylake: Add support to enable wake-on-usb attach/detach
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit 3bfe3404df32ca226c624be0435c640bf1ebeae7 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 18 14:25:25 2016 -0700 intel/skylake: Add support to enable wake-on-usb attach/detach Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17056 for details. -gerrit

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New patch to review for coreboot: amd/hudson: Add PSP2 build for combo BIOS
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17149 -gerrit commit 89104a7a70c7d86baf434453bcf7b98bb8880d18 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:50:25 2016 -0600 amd/hudson: Add PSP2 build for combo BIOS The Stoney processor can use multiple directory structures. Turn this feature on in the makefile. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e) Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 66 ++++++++++++++++++++++++------ 1 file changed, 53 insertions(+), 13 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 59e4240..53a1a4f0 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -161,19 +161,18 @@ OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_TRUSTLETKEY_FILE), --trustl OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_SMUFIRMWARE2_FILE), --smufirmware2) OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs) -#TODO: Set PSP2 Firmware. The setting below is just for testing. -#CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE) -#CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE) -#CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE) -#CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE) -#CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE) -#CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE) -#CONFIG_2PSPNVRAM_FILE =$(CONFIG_PSPNVRAM_FILE) -#CONFIG_2PSPSECUREDEBUG_FILE =$(CONFIG_PSPSECUREDEBUG_FILE) -#CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE) -#CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE) -#CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE) -#CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE) +CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE) +CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE) +CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE) +CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE) +CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE) +CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE) +CONFIG_2PSPNVRAM_FILE =$(CONFIG_PSPNVRAM_FILE) +CONFIG_2PSPSECUREDEBUG_FILE =$(CONFIG_PSPSECUREDEBUG_FILE) +CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE) +CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE) +CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE) +CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE) OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2) OPT_2PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPBTLDR_FILE), --bootloader2) @@ -203,9 +202,50 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_PSPTRUSTLETS_FILE)) \ $(call strip_quotes, $(CONFIG_TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(CONFIG_SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(CONFIG_2AMD_PUBKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_2PUBSIGNEDKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPBTLDR_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUFWM_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPRCVR_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPNVRAM_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUSCS_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(CONFIG_2PSPTRUSTLETS_FILE)) \ + $(call strip_quotes, $(CONFIG_2TRUSTLETKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUFIRMWARE2_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + echo "$(AMDFWTOOL) \ + $(OPT_HUDSON_XHCI_FWM_FILE) \ + $(OPT_HUDSON_IMC_FWM_FILE) \ + $(OPT_HUDSON_GEC_FWM_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUSCS_FILE) \ + $(OPT_2AMD_PUBKEY_FILE) \ + $(OPT_2PSPBTLDR_FILE) \ + $(OPT_2SMUFWM_FILE) \ + $(OPT_2PSPRCVR_FILE) \ + $(OPT_2PUBSIGNEDKEY_FILE) \ + $(OPT_2PSPSCUREOS_FILE) \ + $(OPT_2PSPNVRAM_FILE) \ + $(OPT_2PSPSECUREDEBUG_FILE) \ + $(OPT_2PSPTRUSTLETS_FILE) \ + $(OPT_2TRUSTLETKEY_FILE) \ + $(OPT_2SMUFIRMWARE2_FILE) \ + $(OPT_2SMUSCS_FILE) \ + --output $@" $(AMDFWTOOL) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \

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New patch to review for coreboot: util/amdfwtool: Increase space used for structures
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17148 -gerrit commit 0c29979e0394af7ed1c9428e0e5f49dfd4145edf Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 22:55:54 2016 -0600 util/amdfwtool: Increase space used for structures Double the space for psp2dir to 0x200. Based on advice from AMD, increase the region containing the signature to 4K. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639) Change-Id: If60132f913928bab0c2fe4aacedf342080929599 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index ccddfec..92b8a1b 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -538,7 +538,7 @@ int main(int argc, char **argv) } } - current = ALIGN(current, 0x100); + current = ALIGN(current, 0x1000); current = integrate_firmwares(rom, current, amd_romsig, amd_fw_table); if (pspflag == 1) { @@ -555,7 +555,7 @@ int main(int argc, char **argv) current = ALIGN(current, 0x10000); /* PSP2 dir */ psp2dir = rom + current; amd_romsig[5] = current + ROM_BASE_ADDRESS; - current += 0x100; /* Add conservative size of psp2dir. */ + current += 0x200; /* Add conservative size of psp2dir. */ #if PSP_COMBO /* TODO: remove the hardcode. */

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New patch to review for coreboot: util/amdfwtool: Add PSP2 options to optstring
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17147 -gerrit commit 02937a84d3ed8f8cafda2aa4b4c59c07e6a0dd01 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 21:05:45 2016 -0600 util/amdfwtool: Add PSP2 options to optstring Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de) Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1106304..ccddfec 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -300,7 +300,12 @@ uint32_t integrate_psp_firmwares(void *base, uint32_t pos, uint32_t *pspdir, amd return pos; } -static const char *optstring = "x:i:g:p:b:s:r:k:o:n:d:t:u:w:m:h"; +#if PSP2 +static const char *optstring = "x:i:g:p:b:s:r:k:c:n:d:t:u:w:m:P:B:S:R:K:C:N:D:T:U:W:M:o:h"; +#else +static const char *optstring = "x:i:g:p:b:s:r:k:c:n:d:t:u:w:m:o:h"; +#endif + static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, {"imc", required_argument, 0, 'i' },

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New patch to review for coreboot: util/amdfwtool: Fix duplicate long option name
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17146 -gerrit commit 7b55f93ced7b7e5a65bae6851a9d9dc5b24e1eac Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 14:49:41 2016 -0600 util/amdfwtool: Fix duplicate long option name Make the PSP2 smufirmware2 name unique so the command-line option gets picked up. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: <marcj303(a)gmail.com> (cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624) Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 2 +- util/amdfwtool/amdfwtool.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 291e25f..59e4240 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -177,7 +177,7 @@ OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs) OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2) OPT_2PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPBTLDR_FILE), --bootloader2) -OPT_2SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FILE), --smufirmware2) +OPT_2SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FILE), --smufirmware_2) OPT_2PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_2PSPRCVR_FILE), --recovery2) OPT_2PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_2PUBSIGNEDKEY_FILE), --rtmpubkey2) OPT_2PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_2PSPSCUREOS_FILE), --secureos2) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 3dff2ac..1106304 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -323,7 +323,7 @@ static struct option long_options[] = { #if PSP2 {"pubkey2", required_argument, 0, 'P' }, {"bootloader2", required_argument, 0, 'B' }, - {"smufirmware2", required_argument, 0, 'S' }, + {"smufirmware_2", required_argument, 0, 'S' }, {"recovery2", required_argument, 0, 'R' }, {"rtmpubkey2", required_argument, 0, 'K' }, {"secureos2", required_argument, 0, 'C' },

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New patch to review for coreboot: northbridge/amd: Modify 00670F00 chip.h to match DCT
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17145 -gerrit commit e57c8829a4b2b0d60164ba33e493b00e6651b7f0 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 09:12:27 2016 -0600 northbridge/amd: Modify 00670F00 chip.h to match DCT The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: <marcj303(a)gmail.com> (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8) Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h index 917bc65..a6cc893 100644 --- a/src/northbridge/amd/pi/00670F00/chip.h +++ b/src/northbridge/amd/pi/00670F00/chip.h @@ -18,7 +18,7 @@ struct northbridge_amd_pi_00670F00_config { - u8 spdAddrLookup[2][2][4]; + u8 spdAddrLookup[1][1][2]; }; #endif

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New patch to review for coreboot: northbridge/amd: Update 00670F00 asl for reduced hardware
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17144 -gerrit commit dfd5ff4c4eb8f943c92fda9fe3402a6ff3456525 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 17:57:08 2016 -0400 northbridge/amd: Update 00670F00 asl for reduced hardware Remove the language associated with the Carrizo Gfx PCIe bridges. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748) Change-Id: I8b67a646f98667d500fcee5da8389c10483488da Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- .../amd/pi/00670F00/acpi/northbridge.asl | 35 ---------------------- 1 file changed, 35 deletions(-) diff --git a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl index cde5182..4e6d13e 100644 --- a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl @@ -94,38 +94,3 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -/* GFX 1 */ -Device(PBR9) { - Name(_ADR, 0x00030002) -} /* end PBR8 */ - -/* GFX 2 */ -Device(PBRA) { - Name(_ADR, 0x00030003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSA) } /* APIC mode */ - Return (PSA) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 3 */ -Device(PBRB) { - Name(_ADR, 0x00030004) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSB) } /* APIC mode */ - Return (PSB) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 4 */ -Device(PBRC) { - Name(_ADR, 0x00030005) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSC) } /* APIC mode */ - Return (PSC) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */

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coreboot-gerrit October 2016