coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

1 participants
1281 discussions

New patch to review for coreboot: cbfs: Fix parens typo
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17133 -gerrit commit 923611f520bab982f218e002106604a1ce047d4e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:00:18 2016 -0700 cbfs: Fix parens typo Make the parens used in this string consistent [] instead of [). Change-Id: I02f9909ff8237e3b98536f86bc07adfa4f7f230e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/lib/cbfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 5a2f63f..4d268fc 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -313,7 +313,7 @@ int cbfs_boot_region_properties(struct cbfs_props *props) if (ops->locate(props)) continue; - LOG("'%s' located CBFS at [%zx:%zx)\n", + LOG("'%s' located CBFS at [%zx:%zx]\n", ops->name, props->offset, props->offset + props->size); return 0;

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New patch to review for coreboot: riscv: add the lowrisc/nexys4ddr mainboard
by Ronald G. Minnich 26 Oct '16

26 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17132 -gerrit commit 862acb9e1e45b8828326ec4ba64d2704047559d2 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Oct 25 19:11:07 2016 -0700 riscv: add the lowrisc/nexys4ddr mainboard This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/lowrisc/Kconfig | 16 ++++ src/mainboard/lowrisc/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Kconfig | 38 +++++++++ src/mainboard/lowrisc/nexys4ddr/Kconfig.name | 2 + src/mainboard/lowrisc/nexys4ddr/Makefile.inc | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/board_info.txt | 3 + src/mainboard/lowrisc/nexys4ddr/devicetree.cb | 20 +++++ src/mainboard/lowrisc/nexys4ddr/mainboard.c | 37 +++++++++ src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 31 ++++++++ src/mainboard/lowrisc/nexys4ddr/rom_media.c | 29 +++++++ src/mainboard/lowrisc/nexys4ddr/romstage.c | 28 +++++++ src/mainboard/lowrisc/nexys4ddr/uart.c | 40 ++++++++++ src/mainboard/lowrisc/nexys4ddr/util.c | 103 +++++++++++++++++++++++++ 13 files changed, 377 insertions(+) diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig new file mode 100644 index 0000000..ba0fbe7 --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_LOWRISC + +choice + prompt "Mainboard model" + +source "src/mainboard/lowrisc/*/Kconfig.name" + +endchoice + +source "src/mainboard/lowrisc/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "lowrisc" + +endif # VENDOR_LOWRISC diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name new file mode 100644 index 0000000..4c992fc --- /dev/null +++ b/src/mainboard/lowrisc/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_LOWRISC + bool "lowrisc" diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig new file mode 100644 index 0000000..f0a3637 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_LOWRISC_NEXYS4DDR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_LOWRISC_LOWRISC + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_UART_8250MEM + select BOOT_DEVICE_NOT_SPI_FLASH + select UART_OVERRIDE_REFCLK + select UART_OVERRIDE_INPUT_CLOCK_DIVIDER + +config MAINBOARD_DIR + string + default lowrisc/nexys4ddr + +config MAINBOARD_PART_NUMBER + string + default "LOWRISC NEXYS4DDR" + +config MAX_CPUS + int + default 1 + +endif # BOARD_LOWRISC_NEXYS4DDR diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name new file mode 100644 index 0000000..f99b3cc --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LOWRISC_NEXYS4DDR + bool "nexys4ddr" diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc new file mode 100644 index 0000000..7af6ede --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +bootblock-y += uart.c +bootblock-y += util.c +bootblock-y += rom_media.c +romstage-y += romstage.c +romstage-y += uart.c +romstage-y += util.c +romstage-y += rom_media.c +ramstage-y += uart.c +ramstage-y += util.c +ramstage-y += rom_media.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt new file mode 100644 index 0000000..391509e --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/board_info.txt @@ -0,0 +1,3 @@ +Board name: lowrisc nexys4ddr +Category: eval +Board URL: http://lowrisc.org/docs/debug-v0.3/ diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb new file mode 100644 index 0000000..e3ce088 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c new file mode 100644 index 0000000..3b883ce --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> + +static void mainboard_enable(device_t dev) +{ + /* + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; + + if (!dev) + die("No dev0; die\n"); + + ram_resource(dev, 0, 0x80000000/KiB, ram_size/KiB); + + cbmem_recovery(0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld new file mode 100644 index 0000000..c0ef78f --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +#define START 0x80000000 + +SECTIONS +{ + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + PAGETABLES(START + 8M + 200K, 56K) + RAMSTAGE(START + 8M + 256K, 256K) +} diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c new file mode 100644 index 0000000..26a3b02 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <boot_device.h> + +/* + * 0x80000000 is this start of RAM. We currently need to load coreboot.rom into + * RAM. The actual "rom" code on the FPGAs is in a block ram. + */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c new file mode 100644 index 0000000..ff4a082 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/romstage.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <program_loading.h> + +void main(void) +{ + // You currently can not call console_init from romstage. It brings + // in COREBOOT_EXTRA_VERSION, which is in .data, and we get a linker + // warning. I suspect the best fix is to have all the declarations + // in src/lib/version.c set up to be in the .text or .rodata + // section but that's a problem for another day. At some point + // we'd like to call console_init here. + // console_init(); + run_ramstage(); +} diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c new file mode 100644 index 0000000..128c736 --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/uart.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <spike_util.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t) 0x42000000; +} + +/* these are currently not quite right but they are here for reference + * and will be fixed soon. */ +// divisor = clk_freq / (16 * Baud) +unsigned int uart_input_clock_divider(void) +{ + return (25*1000*1000u / (16u * 115200u)) % 0x100; +} + +// System clock 25 MHz, 115200 baud rate +unsigned int uart_platform_refclk(void) +{ + return (25*1000*1000u / (16u * 115200u)) >> 8; +} + diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c new file mode 100644 index 0000000..32cdb6d --- /dev/null +++ b/src/mainboard/lowrisc/nexys4ddr/util.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, + * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING + * LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS + * DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING + * DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS + * IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, + * UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + /* Ensure the other hart sees it. */ + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +}

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New patch to review for coreboot: [RFC] Add ich9deblob from libreboot project
by Iru Cai 26 Oct '16

26 Oct '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17131 -gerrit commit 888825fc7b4167ba1ba454a63e5d5ef704d5e025 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Wed Oct 26 10:09:55 2016 +0800 [RFC] Add ich9deblob from libreboot project Change-Id: I637305d3436b0508e1e0ddb2e44430a271c1109b Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- util/ich9deblob/Makefile | 92 ++++ util/ich9deblob/obj/.empty | 0 util/ich9deblob/obj/common/.empty | 0 util/ich9deblob/obj/descriptor/.empty | 0 util/ich9deblob/obj/gbe/.empty | 0 util/ich9deblob/obj/ich9gen/.empty | 0 util/ich9deblob/src/common/descriptor_gbe.c | 90 ++++ util/ich9deblob/src/common/descriptor_gbe.h | 37 ++ util/ich9deblob/src/common/x86compatibility.c | 161 +++++++ util/ich9deblob/src/common/x86compatibility.h | 42 ++ util/ich9deblob/src/demefactory.c | 141 ++++++ util/ich9deblob/src/demefactory.h | 34 ++ util/ich9deblob/src/descriptor/descriptor.c | 665 ++++++++++++++++++++++++++ util/ich9deblob/src/descriptor/descriptor.h | 333 +++++++++++++ util/ich9deblob/src/gbe/gbe.c | 454 ++++++++++++++++++ util/ich9deblob/src/gbe/gbe.h | 435 +++++++++++++++++ util/ich9deblob/src/ich9deblob.c | 221 +++++++++ util/ich9deblob/src/ich9deblob.h | 38 ++ util/ich9deblob/src/ich9gen.c | 150 ++++++ util/ich9deblob/src/ich9gen.h | 39 ++ util/ich9deblob/src/ich9gen/mkdescriptor.c | 229 +++++++++ util/ich9deblob/src/ich9gen/mkdescriptor.h | 27 ++ util/ich9deblob/src/ich9gen/mkgbe.c | 257 ++++++++++ util/ich9deblob/src/ich9gen/mkgbe.h | 29 ++ 24 files changed, 3474 insertions(+) diff --git a/util/ich9deblob/Makefile b/util/ich9deblob/Makefile new file mode 100644 index 0000000..dad57e7 --- /dev/null +++ b/util/ich9deblob/Makefile @@ -0,0 +1,92 @@ +# +# Makefile for ich9deblob utility from libreboot project +# +# Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +CC=gcc +FORCEC99=-std=c99 +CFLAGS=-I. -Wall -Wextra -g $(FORCEC99) +NOLINKER=-c + +all: ich9deblob ich9gen demefactory + +ich9deblob: obj/ich9deblob.o obj/common/descriptor_gbe.o \ + obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o + + $(CC) $(CFLAGS) obj/ich9deblob.o obj/common/descriptor_gbe.o \ + obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ + -o ich9deblob + +ich9gen: obj/ich9gen.o obj/ich9gen/mkdescriptor.o obj/ich9gen/mkgbe.o \ + obj/common/descriptor_gbe.o \ + obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o + + $(CC) $(CFLAGS) obj/ich9gen.o obj/ich9gen/mkdescriptor.o obj/ich9gen/mkgbe.o \ + obj/common/descriptor_gbe.o \ + obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ + -o ich9gen + +demefactory: obj/demefactory.o obj/common/descriptor_gbe.o \ + obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o + + $(CC) $(CFLAGS) obj/demefactory.o obj/common/descriptor_gbe.o \ + obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ + -o demefactory + +# for demefactory +# ---------------------------------------------------------------------- + +obj/demefactory.o: + $(CC) $(CFLAGS) $(NOLINKER) src/demefactory.c -o obj/demefactory.o + +# for ich9deblob +# ---------------------------------------------------------------------- + +obj/ich9deblob.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9deblob.c -o obj/ich9deblob.o + +# for ich9gen +# ---------------------------------------------------------------------- + +obj/ich9gen.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen.c -o obj/ich9gen.o + +obj/ich9gen/mkdescriptor.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen/mkdescriptor.c -o obj/ich9gen/mkdescriptor.o + +obj/ich9gen/mkgbe.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen/mkgbe.c -o obj/ich9gen/mkgbe.o + +# for demefactory, ich9deblob and ich9gen: +# ---------------------------------------------------------------------- + +obj/common/descriptor_gbe.o: + $(CC) $(CFLAGS) $(NOLINKER) src/common/descriptor_gbe.c -o obj/common/descriptor_gbe.o + +obj/common/x86compatibility.o: + $(CC) $(CFLAGS) $(NOLINKER) src/common/x86compatibility.c -o obj/common/x86compatibility.o + +obj/descriptor/descriptor.o: + $(CC) $(CFLAGS) $(NOLINKER) src/descriptor/descriptor.c -o obj/descriptor/descriptor.o + +obj/gbe/gbe.o: + $(CC) $(CFLAGS) $(NOLINKER) src/gbe/gbe.c -o obj/gbe/gbe.o + +# make clean +# ---------------------------------------------------------------------- +clean: + rm -Rf ich9deblob ich9gen demefactory obj/*.o obj/*/*.o diff --git a/util/ich9deblob/obj/.empty b/util/ich9deblob/obj/.empty new file mode 100644 index 0000000..e69de29 diff --git a/util/ich9deblob/obj/common/.empty b/util/ich9deblob/obj/common/.empty new file mode 100644 index 0000000..e69de29 diff --git a/util/ich9deblob/obj/descriptor/.empty b/util/ich9deblob/obj/descriptor/.empty new file mode 100644 index 0000000..e69de29 diff --git a/util/ich9deblob/obj/gbe/.empty b/util/ich9deblob/obj/gbe/.empty new file mode 100644 index 0000000..e69de29 diff --git a/util/ich9deblob/obj/ich9gen/.empty b/util/ich9deblob/obj/ich9gen/.empty new file mode 100644 index 0000000..e69de29 diff --git a/util/ich9deblob/src/common/descriptor_gbe.c b/util/ich9deblob/src/common/descriptor_gbe.c new file mode 100644 index 0000000..1c1ad32 --- /dev/null +++ b/util/ich9deblob/src/common/descriptor_gbe.c @@ -0,0 +1,90 @@ +/* + * descriptor_gbe.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: common descriptor/gbe functions used by ich9deblob + * + * Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "descriptor_gbe.h" + +/* + * create 12KiB file with descriptor, and then gbe immediately after. + */ +int notCreatedDescriptorGbeFile(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k, char* fileName) +{ + FILE* fileStream = NULL; + + /* delete old file before continuing */ + remove(fileName); + + /* open new file for writing the descriptor+gbe */ + fileStream = fopen(fileName, "ab"); + + /* write the descriptor region into the first part */ + if (DESCRIPTORREGIONSIZE != fwrite((uint8_t*)&descriptorStruct, 1, sizeof(descriptorStruct), fileStream)) + { + printf("\nerror: writing descriptor region failed\n"); + return 1; + } + + /* add gbe to the end of the file */ + if (GBEREGIONSIZE_8K != fwrite((uint8_t*)&gbeStruct8k, 1, sizeof(gbeStruct8k), fileStream)) + { + printf("\nerror: writing GBe region failed\n"); + return 1; + } + + fclose(fileStream); + + printf("descriptor and gbe successfully written to the file: %s\n", fileName); + printf("Now do: dd if=%s of=libreboot.rom bs=1 count=12k conv=notrunc\n", fileName); + printf("(in other words, add the modified descriptor+gbe to your ROM image)\n\n"); + + return 0; +} + +/* + * create 4KiB file with descriptor + */ +int notCreated4kDescriptorFile(struct DESCRIPTORREGIONRECORD descriptorStruct, char* fileName) +{ + FILE* fileStream = NULL; + + /* delete old file before continuing */ + remove(fileName); + + /* open new file for writing the descriptor+gbe */ + fileStream = fopen(fileName, "ab"); + + /* write the descriptor region into the first part */ + if (DESCRIPTORREGIONSIZE != fwrite((uint8_t*)&descriptorStruct, 1, sizeof(descriptorStruct), fileStream)) + { + printf("\nerror: writing descriptor region failed\n"); + return 1; + } + + + fclose(fileStream); + + printf("descriptor successfully written to the file: %s\n", fileName); + printf("Now do: dd if=%s of=yourrom.rom bs=1 count=4k conv=notrunc\n", fileName); + printf("(in other words, add the modified descriptor to your ROM image)\n\n"); + + return 0; +} diff --git a/util/ich9deblob/src/common/descriptor_gbe.h b/util/ich9deblob/src/common/descriptor_gbe.h new file mode 100644 index 0000000..b3713c8 --- /dev/null +++ b/util/ich9deblob/src/common/descriptor_gbe.h @@ -0,0 +1,37 @@ +/* + * gbe_descriptor.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: header file for descriptor_gbe.c + * + * Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef COMMON_DESCRIPTOR_GBE_H +#define COMMON_DESCRIPTOR_GBE_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> + +#include "../descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "../gbe/gbe.h" /* structs describing what's in the gbe region */ + +int notCreatedDescriptorGbeFile(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k, char* fileName); +int notCreated4kDescriptorFile(struct DESCRIPTORREGIONRECORD descriptorStruct, char* fileName); + +#endif diff --git a/util/ich9deblob/src/common/x86compatibility.c b/util/ich9deblob/src/common/x86compatibility.c new file mode 100644 index 0000000..362c634 --- /dev/null +++ b/util/ich9deblob/src/common/x86compatibility.c @@ -0,0 +1,161 @@ +/* + * x86compatibility.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: compiler/cpu compatibility checks. ich9deblob is not portable, yet. + * + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "x86compatibility.h" + +/* + * --------------------------------------------------------------------- + * x86 compatibility checking: + * --------------------------------------------------------------------- + */ + +/* fail if struct size is incorrect */ +int structSizesIncorrect(struct DESCRIPTORREGIONRECORD descriptorDummy, struct GBEREGIONRECORD_8K gbe8kDummy) +{ + unsigned int descriptorRegionStructSize = sizeof(descriptorDummy); + unsigned int gbeRegion8kStructSize = sizeof(gbe8kDummy); + + /* check compiler bit-packs in a compatible way. basically, it is expected that this code will be used on x86 */ + if (DESCRIPTORREGIONSIZE != descriptorRegionStructSize){ + printf("\nerror: compiler incompatibility: descriptor struct length is %i bytes (should be %i)\n", descriptorRegionStructSize, DESCRIPTORREGIONSIZE); + return 1; + } + if (GBEREGIONSIZE_8K != gbeRegion8kStructSize){ + printf("\nerror: compiler incompatibility: gbe struct length is %i bytes (should be %i)\n", gbeRegion8kStructSize, GBEREGIONSIZE_8K); + return 1; + } + + return 0; +} + +/* fail if members are presented in the wrong order */ +int structMembersWrongOrder() +{ + int i; + struct DESCRIPTORREGIONRECORD descriptorDummy; + uint8_t *meVsccTablePtr = (uint8_t*)&descriptorDummy.meVsccTable; + + /* These do not use bitfields. */ + descriptorDummy.meVsccTable.jid0 = 0x01020304; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.vscc0 = 0x10203040; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.jid1 = 0x11223344; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.vscc1 = 0x05060708; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.jid2 = 0x50607080; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.vscc2 = 0x55667788; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.padding[0] = 0xAA; /* unsigned char 8-bit */ + descriptorDummy.meVsccTable.padding[1] = 0xBB; /* unsigned char 8-bit */ + descriptorDummy.meVsccTable.padding[2] = 0xCC; /* unsigned char 8-bit */ + descriptorDummy.meVsccTable.padding[3] = 0xDD; /* unsigned char 8-bit */ + + /* + * Look from the top down, and concatenate the unsigned ints but + * with each unsigned in little endian order. + * Then, concatenate the unsigned chars in big endian order. (in the padding array) + * + * combined, these should become: + * 01020304 10203040 11223344 05060708 50607080 55667788 AA BB CC DD (ignore this. big endian. just working it out manually:) + * 04030201 40302010 44332211 08070605 80706050 88776655 AA BB CC DD (ignore this. not byte-separated, just working it out:) + * 04 03 02 01 40 30 20 10 44 33 22 11 08 07 06 05 80 70 60 50 88 77 66 55 AA BB CC DD <-- it should match this + */ + + if ( + ! + ( + *meVsccTablePtr == 0x04 && *(meVsccTablePtr+1) == 0x03 && *(meVsccTablePtr+2) == 0x02 && *(meVsccTablePtr+3) == 0x01 + && *(meVsccTablePtr+4) == 0x40 && *(meVsccTablePtr+5) == 0x30 && *(meVsccTablePtr+6) == 0x20 && *(meVsccTablePtr+7) == 0x10 + && *(meVsccTablePtr+8) == 0x44 && *(meVsccTablePtr+9) == 0x33 && *(meVsccTablePtr+10) == 0x22 && *(meVsccTablePtr+11) == 0x11 + && *(meVsccTablePtr+12) == 0x08 && *(meVsccTablePtr+13) == 0x07 && *(meVsccTablePtr+14) == 0x06 && *(meVsccTablePtr+15) == 0x05 + && *(meVsccTablePtr+16) == 0x80 && *(meVsccTablePtr+17) == 0x70 && *(meVsccTablePtr+18) == 0x60 && *(meVsccTablePtr+19) == 0x50 + && *(meVsccTablePtr+20) == 0x88 && *(meVsccTablePtr+21) == 0x77 && *(meVsccTablePtr+22) == 0x66 && *(meVsccTablePtr+23) == 0x55 + && *(meVsccTablePtr+24) == 0xAA && *(meVsccTablePtr+25) == 0xBB && *(meVsccTablePtr+26) == 0xCC && *(meVsccTablePtr+27) == 0xDD + ) + ) { + + printf("\nStruct member order check (descriptorDummy.meVsccTable) with junk/dummy data:"); + printf("\nShould be: 04 03 02 01 40 30 20 10 44 33 22 11 08 07 06 05 80 70 60 50 88 77 66 55 aa bb cc dd "); + printf("\nAnd it is: "); + + for (i = 0; i < 28; i++) { + printf("%02x ", *(meVsccTablePtr + i)); + } + printf("\nIncorrect order.\n"); + + return 1; + } + + return 0; +} + +/* fail if bit fields are presented in the wrong order */ +int structBitfieldWrongOrder() +{ + int i; + struct DESCRIPTORREGIONRECORD descriptorDummy; + uint8_t *flMap0Ptr = (uint8_t*)&descriptorDummy.flMaps.flMap0; + + descriptorDummy.flMaps.flMap0.FCBA = 0xA2; /* :8 --> 10100010 */ + descriptorDummy.flMaps.flMap0.NC = 0x02; /* :2 --> 10 */ + descriptorDummy.flMaps.flMap0.reserved1 = 0x38; /* :6 --> 111000 */ + descriptorDummy.flMaps.flMap0.FRBA = 0xD2; /* :8 --> 11010010 */ + descriptorDummy.flMaps.flMap0.NR = 0x05; /* :3 --> 101 */ + descriptorDummy.flMaps.flMap0.reserved2 = 0x1C; /* :5 --> 11100 */ + + /* + * Look from the top bottom up, and concatenate the binary strings. + * Then, convert the 8-bit groups to hex and reverse the (8-bit)byte order + * + * combined, these should become (in memory), in binary: + * 10100010 11100010 11010010 11100101 + * or in hex: + * A2 E2 D2 E5 + */ + + if (!(*flMap0Ptr == 0xA2 && *(flMap0Ptr+1) == 0xE2 && *(flMap0Ptr+2) == 0xD2 && *(flMap0Ptr+3) == 0xE5)) + { + printf("\nBitfield order check (descriptorDummy.flMaps.flMaps0) with junk/dummy data:"); + printf("\nShould be: a2 e2 d2 e5 "); + printf("\nAnd it is: "); + + for (i = 0; i < 4; i++) { + printf("%02x ", *(flMap0Ptr + i)); + } + printf("\nIncorrect order.\n"); + + return 1; + } + + return 0; +} + +/* Compatibility checks. This version of ich9deblob is not yet porable. */ +int systemOrCompilerIncompatible(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k) +{ + if (structSizesIncorrect(descriptorStruct, gbeStruct8k)) return 1; + if (IS_BIG_ENDIAN) { + printf("big endian not supported\n"); + return 1; + } + if (structBitfieldWrongOrder()) return 1; + if (structMembersWrongOrder()) return 1; + return 0; +} diff --git a/util/ich9deblob/src/common/x86compatibility.h b/util/ich9deblob/src/common/x86compatibility.h new file mode 100644 index 0000000..5a598ad --- /dev/null +++ b/util/ich9deblob/src/common/x86compatibility.h @@ -0,0 +1,42 @@ +/* + * x86compatibility.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: keep gcc/make happy. no actual code here, just function definitions. + * + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef X86COMPATIBILITY_H +#define X86COMPATIBILITY_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> + +/* http://esr.ibiblio.org/?p=5095 */ +#define IS_BIG_ENDIAN (*(uint16_t *)"\0\xff" < 0x100) + +#include "../descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "../gbe/gbe.h" /* structs describing what's in the gbe region */ + +int structSizesIncorrect(struct DESCRIPTORREGIONRECORD descriptorDummy, struct GBEREGIONRECORD_8K gbe8kDummy); +int structMembersWrongOrder(); +int structBitfieldWrongOrder(); +int systemOrCompilerIncompatible(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k); + +#endif diff --git a/util/ich9deblob/src/demefactory.c b/util/ich9deblob/src/demefactory.c new file mode 100644 index 0000000..596118c --- /dev/null +++ b/util/ich9deblob/src/demefactory.c @@ -0,0 +1,141 @@ +/* + * demefactory.c + * This file is part of the demefactory utility from the libreboot project + * + * Purpose: disable ME on GM45 factory firmware, but leave region intact + * enable read-write on all regions + * + * Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * demfactory utility - main + */ + +#include "demefactory.h" + +int main() +{ + struct DESCRIPTORREGIONRECORD descriptorStruct; + uint8_t* descriptorBuffer = (uint8_t*)&descriptorStruct; + + struct GBEREGIONRECORD_8K gbeStruct8k; /* not needed, except for compatibility checking */ + + char* romFilename = "factory.rom"; + char* descriptorFilename = "demefactory_4kdescriptor.bin"; + + unsigned int bufferLength; + unsigned int romSize; + + /* + * ------------------------------------------------------------------ + * Compatibility checks. This version of ich9deblob is not yet portable. + * ------------------------------------------------------------------ + */ + + if (systemOrCompilerIncompatible(descriptorStruct, gbeStruct8k)) return 1; + /* If true, fail with error message */ + + /* + * ------------------------------------------------------------------ + * Extract the descriptor region from the factory.rom dump + * ------------------------------------------------------------------ + */ + FILE* fp = NULL; + fp = fopen(romFilename, "rb"); /* open factory.rom */ + if (NULL == fp) + { + printf("\nerror: could not open %s\n", romFilename); + fclose(fp); + return 1; + } + printf("\n%s opened successfully\n", romFilename); + + /* + * Get the descriptor region dump from the factory.rom + * (goes in factoryDescriptorBuffer variable) + */ + bufferLength = fread(descriptorBuffer, 1, DESCRIPTORREGIONSIZE, fp); + if (DESCRIPTORREGIONSIZE != bufferLength) // + { + printf("\nerror: could not read descriptor from %s (%i) bytes read\n", romFilename, bufferLength); + fclose(fp); + return 1; + } + printf("\ndescriptor region read successfully\n"); + + /* ------------------------------------------------- */ + + fseek(fp, 0L, SEEK_END); + romSize = ftell(fp); + printf("\n%s size: [%i] bytes\n", romFilename, romSize); + + /* -------------------------------------------------- */ + + fclose(fp); + + /* Debugging (before modification) */ + printDescriptorRegionLocations(descriptorStruct, "Original"); + + /* + * ------------------------------------------------------------------ + * Modify the descriptor region, ready to go in the modified factory.rom + * ------------------------------------------------------------------ + */ + + // Disable the ME/TPM: + descriptorStruct = descriptorDisableMe(descriptorStruct); + descriptorStruct = descriptorDisableTpm(descriptorStruct); + + /* Host/CPU is allowed to read/write all regions. */ + descriptorStruct = descriptorHostRegionsUnlocked(descriptorStruct); + /* The ME is disallowed read-write access to all regions + * (this is probably redundant, since the ME is already removed from libreboot) */ + descriptorStruct = descriptorMeRegionsForbidden(descriptorStruct); + + /* Debugging (after modifying the descriptor region) */ + printDescriptorRegionLocations(descriptorStruct, "Modified"); + + /* + * ------------------------------------------------------------------ + * Create the file with the modified descriptor inside + * ------------------------------------------------------------------ + */ + + printf("\n"); + if (notCreated4kDescriptorFile(descriptorStruct, descriptorFilename)) { + return 1; + } + + /* + * ------------------------------------------------------------------ + * Generate ich9gen data (C code that will recreate the deactivatedME descriptor from scratch) + * ------------------------------------------------------------------ + */ + /* Code for generating the Descriptor struct */ + /* mkdescriptor.h */ + if (notCreatedHFileForDescriptorCFile("mkdescriptor.h", "mkdescriptor.c")) { + return 1; + } /* and now mkdescriptor.c */ + if (notCreatedCFileFromDescriptorStruct(descriptorStruct, "mkdescriptor.c", "mkdescriptor.h")) { + return 1; + } + + printf("The modified descriptor region has also been dumped as src files: mkdescriptor.c, mkdescriptor.h\n\n"); + + return 0; +} diff --git a/util/ich9deblob/src/demefactory.h b/util/ich9deblob/src/demefactory.h new file mode 100644 index 0000000..7226886 --- /dev/null +++ b/util/ich9deblob/src/demefactory.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Header file for demefactory.c */ + +#ifndef DEMEFACTORY_H +#define DEMEFACTORY_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> + +#include "common/descriptor_gbe.h" /* common descriptor/gbe functions used by ich9deblob */ +#include "common/x86compatibility.h" /* system/compiler compatibility checks. This code is not portable. */ +#include "descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "gbe/gbe.h" /* structs describing what's in the gbe region */ + +int main(); + +#endif diff --git a/util/ich9deblob/src/descriptor/descriptor.c b/util/ich9deblob/src/descriptor/descriptor.c new file mode 100644 index 0000000..18e4e17 --- /dev/null +++ b/util/ich9deblob/src/descriptor/descriptor.c @@ -0,0 +1,665 @@ +/* + * descriptor/descriptor.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Provide descriptor related functions. + */ + +/* structs describing the data in descriptor region */ +#include "descriptor.h" + +/* + * --------------------------------------------------------------------- + * Descriptor related functions + * --------------------------------------------------------------------- + */ + +/* Set the Host CPU / BIOS region to have read-write access on all regions */ +struct DESCRIPTORREGIONRECORD descriptorHostRegionsUnlocked(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; + + return descriptorStruct; +} + +/* Set the ME to have *no* read-write access on any region */ +struct DESCRIPTORREGIONRECORD descriptorMeRegionsForbidden(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess = 0x0; + + return descriptorStruct; +} + +/* Disable (delete) the ME region */ +struct DESCRIPTORREGIONRECORD descriptorMeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg2.BASE = 0x1FFF; + descriptorStruct.regionSection.flReg2.LIMIT = 0; + + return descriptorStruct; +} + +/* Disable (delete) the Platform region */ +struct DESCRIPTORREGIONRECORD descriptorPlatformRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg4.BASE = 0x1FFF; + descriptorStruct.regionSection.flReg4.LIMIT = 0; + + return descriptorStruct; +} + +/* Disable the ME in ICHSTRAP0 and MCHSTRAP0 */ +struct DESCRIPTORREGIONRECORD descriptorDisableMe(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.ichStraps.ichStrap0.meDisable = 1; + descriptorStruct.mchStraps.mchStrap0.meDisable = 1; + + return descriptorStruct; +} + +/* Disable the TPM in MCHSTRAP0 */ +struct DESCRIPTORREGIONRECORD descriptorDisableTpm(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.mchStraps.mchStrap0.tpmDisable = 1; + + return descriptorStruct; +} + +/* Relocate the Gbe region to begin at 4KiB (immediately after the flash descriptor) */ +struct DESCRIPTORREGIONRECORD descriptorMoveGbeToStart(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg3.BASE = DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT; + descriptorStruct.regionSection.flReg3.LIMIT = GBEREGIONSIZE_8K >> FLREGIONBITSHIFT; + + return descriptorStruct; +} + +/* Disable (delete) the GbE region */ +struct DESCRIPTORREGIONRECORD descriptorGbeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg3.BASE = 0x1FFF; + descriptorStruct.regionSection.flReg3.LIMIT = 0; + + return descriptorStruct; +} + +/* BIOS Region begin after descriptor+gbe at first 12KiB, fills the rest of the image */ +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterGbe(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + GBEREGIONSIZE_8K) >> FLREGIONBITSHIFT; + descriptorStruct.regionSection.flReg1.LIMIT = (romSize >> FLREGIONBITSHIFT) - 1; + + return descriptorStruct; +} + +/* BIOS Region begin after descriptor at first 4KiB, fills the rest of the image */ +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterDescriptor(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + descriptorStruct.regionSection.flReg1.BASE = DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT; + descriptorStruct.regionSection.flReg1.LIMIT = (romSize >> FLREGIONBITSHIFT) - 1; + + return descriptorStruct; +} + +/* Set OEM string to "LIBERATE" */ +struct DESCRIPTORREGIONRECORD descriptorOemString(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.oemSection.magicString[0] = 0x4C; + descriptorStruct.oemSection.magicString[1] = 0x49; + descriptorStruct.oemSection.magicString[2] = 0x42; + descriptorStruct.oemSection.magicString[3] = 0x45; + descriptorStruct.oemSection.magicString[4] = 0x52; + descriptorStruct.oemSection.magicString[5] = 0x41; + descriptorStruct.oemSection.magicString[6] = 0x54; + descriptorStruct.oemSection.magicString[7] = 0x45; + + return descriptorStruct; +} + +/* Check whether a GbE region is defined by this descriptor. + * Not thorough, but should work in most cases */ +int descriptorDefinesGbeRegion(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + if ( + (descriptorStruct.regionSection.flReg3.BASE == 0x1FFF || descriptorStruct.regionSection.flReg3.BASE == 0xFFF) + && + (descriptorStruct.regionSection.flReg3.LIMIT == 0) + ) + return 0; /* has no GbE region */ + else if ( + descriptorStruct.ichStraps.ichStrap0.integratedGbe == 0 + || + descriptorStruct.ichStraps.ichStrap0.lanPhy == 0 + ) + return 0; /* has no GbE region */ + else + return 1; /* has a GbE region */ +} + +/* Configure the BIOS and GbE regions, as required by libreboot. + * Enable or disable the GbE region, based on what's in the descriptor */ +struct DESCRIPTORREGIONRECORD librebootSetGbeBiosDescriptorRegions(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + /* + * set number of regions from 4 -> 2 (0 based, so 4 means 5 and 2 + * means 3. We want 3 regions: descriptor, gbe and bios, in that order) + */ + descriptorStruct.flMaps.flMap0.NR = 2; + /* Move GbE region to the start of the image (after the descriptor) */ + descriptorStruct = descriptorMoveGbeToStart(descriptorStruct); + /* BIOS region fills the remaining space */ + descriptorStruct = descriptorBiosRegionFillImageAfterGbe(descriptorStruct, romSize); + + /* GbE region means that an Intel NIC is to be present */ + descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x1; + descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x1; + } + else { + /* + * set number of regions from 4 -> 2 (0 based, so 4 means 5 and 1 + * means 2. We want 2 regions: descriptor and bios, in that order) + */ + descriptorStruct.flMaps.flMap0.NR = 1; + /* Disable the GbE region */ + descriptorStruct = descriptorGbeRegionRemoved(descriptorStruct); + /* BIOS region fills the remaining space, after the descriptor */ + descriptorStruct = descriptorBiosRegionFillImageAfterDescriptor(descriptorStruct, romSize); + + /* No GbE region means that an onboard NIC is still used, but it's discrete (eg Broadcom) */ + descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x0; + descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x0; + } + + return descriptorStruct; +} + +uint8_t componentDensity(unsigned int romSizeInBytes) +{ + /* component density, see Component Section Record. page 848 in the datasheet */ + switch (romSizeInBytes) + { + case ROMSIZE_512KB: return 0; + case ROMSIZE_1MB: return 1; + case ROMSIZE_2MB: return 2; + case ROMSIZE_4MB: return 3; + case ROMSIZE_8MB: return 4; + case ROMSIZE_16MB: return 5; + default: return 0x7; /* reserved value */ + } +} + +/* From a factory.rom image, create a modified descriptor region, suitable + * for use by the libreboot project */ +struct DESCRIPTORREGIONRECORD librebootDescriptorStructFromFactory(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + /* Enable or disable the GbE region, from what's in the descriptor */ + descriptorStruct = librebootSetGbeBiosDescriptorRegions(descriptorStruct, romSize); + + /* Disable the ME/TPM and remove the ME/Platform regions: */ + descriptorStruct = descriptorMeRegionRemoved(descriptorStruct); + /* Disable the ME/TPM and remove the ME/Platform regions: */ + descriptorStruct = descriptorPlatformRegionRemoved(descriptorStruct); + + /* Disable the ME itself, so that it doesn't try to start when this descriptor is in use */ + descriptorStruct = descriptorDisableMe(descriptorStruct); + /* Also disable the TPM, by default */ + descriptorStruct = descriptorDisableTpm(descriptorStruct); + + return descriptorStruct; +} + +/* + * --------------------------------------------------------------------- + * C code generator (self-writing code) + * --------------------------------------------------------------------- + */ + +/* + * Generate a C (.h) header file for the C source file made by notCreatedCFileFromDescriptorStruct() + * + * Output it to a file. + */ +int notCreatedHFileForDescriptorCFile(char* outFileName, char* cFileName) +{ + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .h header file for the descriptor-generating C code (%s) */\n\n", cFileName); + + fprintf(fp, "#ifndef ICH9GEN_MKDESCRIPTOR_H\n"); + fprintf(fp, "#define ICH9GEN_MKDESCRIPTOR_H\n\n"); + + fprintf(fp, "#include <stdio.h>\n"); + fprintf(fp, "#include <string.h>\n"); + fprintf(fp, "#include \"../descriptor/descriptor.h\"\n\n"); + + fprintf(fp, "struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe);\n"); + + fprintf(fp, "#endif\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} + +/* + * Generate a C source file that initializes the same data from a given + * 4KiB Descriptor data structure. + * + * Output it to a file. + */ +int notCreatedCFileFromDescriptorStruct(struct DESCRIPTORREGIONRECORD descriptorStruct, char* outFileName, char* headerFileName) +{ + int i, j; + + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .c source file for the descriptor-generating C code */\n\n"); + + fprintf(fp, "#include \"%s\"\n\n", headerFileName); + + fprintf(fp, "/* Generate a 4KiB Descriptor struct, with default values. */\n"); + fprintf(fp, "/* Read ../descriptor/descriptor.h for an explanation of the default values used here */\n\n"); + + fprintf(fp, "struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe)\n"); + fprintf(fp, "{\n"); + fprintf(fp, " int i;\n"); + fprintf(fp, " struct DESCRIPTORREGIONRECORD descriptorStruct;\n"); + fprintf(fp, "\n"); + /* Flash Valid Signature Register */ + fprintf(fp, " /* Flash Valid Signature Register */\n"); + fprintf(fp, " descriptorStruct.flValSig.signature = 0x%08x;\n", descriptorStruct.flValSig.signature); + fprintf(fp, "\n"); + /* Flash Map Registers */ + fprintf(fp, " /* Flash Map Registers */\n"); + fprintf(fp, " /* FLMAP0 */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap0.FCBA = 0x%02x;\n", descriptorStruct.flMaps.flMap0.FCBA); + fprintf(fp, " descriptorStruct.flMaps.flMap0.NC = 0x%01x;\n", descriptorStruct.flMaps.flMap0.NC); + fprintf(fp, " descriptorStruct.flMaps.flMap0.reserved1 = 0x%02x;\n", descriptorStruct.flMaps.flMap0.reserved1); + fprintf(fp, " descriptorStruct.flMaps.flMap0.FRBA = 0x%02x;\n", descriptorStruct.flMaps.flMap0.FRBA); + fprintf(fp, " /* descriptorStruct.flMaps.flMap0.NR = 0x%01x; */ /* see ../descriptor/descriptor.c */\n", descriptorStruct.flMaps.flMap0.NR); + fprintf(fp, " descriptorStruct.flMaps.flMap0.NR = hasGbe ? 0x2 : 0x1; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap0.reserved2 = 0x%02x;\n", descriptorStruct.flMaps.flMap0.reserved2); + fprintf(fp, " /* FLMAP1 */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap1.FMBA = 0x%02x;\n", descriptorStruct.flMaps.flMap1.FMBA); + fprintf(fp, " descriptorStruct.flMaps.flMap1.NM = 0x%01x;\n", descriptorStruct.flMaps.flMap1.NM); + fprintf(fp, " descriptorStruct.flMaps.flMap1.reserved = 0x%02x;\n", descriptorStruct.flMaps.flMap1.reserved); + fprintf(fp, " descriptorStruct.flMaps.flMap1.FISBA = 0x%02x;\n", descriptorStruct.flMaps.flMap1.FISBA); + fprintf(fp, " descriptorStruct.flMaps.flMap1.ISL = 0x%02x;\n", descriptorStruct.flMaps.flMap1.ISL); + fprintf(fp, " /* FLMAP2 */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap2.FMSBA = 0x%02x;\n", descriptorStruct.flMaps.flMap2.FMSBA); + fprintf(fp, " descriptorStruct.flMaps.flMap2.MSL = 0x%02x;\n", descriptorStruct.flMaps.flMap2.MSL); + fprintf(fp, " descriptorStruct.flMaps.flMap2.reserved = 0x%04x;\n", descriptorStruct.flMaps.flMap2.reserved); + fprintf(fp, "\n"); + /* Component Section Record */ + fprintf(fp, " /* Component Section Record */\n"); + fprintf(fp, " /* FLCOMP */\n"); + fprintf(fp, " /* descriptorStruct.componentSection.flcomp.component1Density = 0x%01x; */\n", descriptorStruct.componentSection.flcomp.component1Density); + fprintf(fp, " /* descriptorStruct.componentSection.flcomp.component2Density = 0x%01x; */\n", descriptorStruct.componentSection.flcomp.component2Density); + fprintf(fp, " descriptorStruct.componentSection.flcomp.component1Density = componentDensity(romSize);\n"); + fprintf(fp, " descriptorStruct.componentSection.flcomp.component2Density = componentDensity(romSize);\n"); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved1 = 0x%01x;\n", descriptorStruct.componentSection.flcomp.reserved1); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved2 = 0x%02x;\n", descriptorStruct.componentSection.flcomp.reserved2); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved3 = 0x%01x;\n", descriptorStruct.componentSection.flcomp.reserved3); + fprintf(fp, " descriptorStruct.componentSection.flcomp.readClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.readClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.fastReadSupport = 0x%01x;\n", descriptorStruct.componentSection.flcomp.fastReadSupport); + fprintf(fp, " descriptorStruct.componentSection.flcomp.fastreadClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.fastreadClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.writeEraseClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.writeEraseClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.readStatusClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.readStatusClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved4 = 0x%01x;\n", descriptorStruct.componentSection.flcomp.reserved4); + fprintf(fp, " /* FLILL */\n"); + fprintf(fp, " descriptorStruct.componentSection.flill = 0x%08x;\n", descriptorStruct.componentSection.flill); + fprintf(fp, " /* FLPB */\n"); + fprintf(fp, " descriptorStruct.componentSection.flpb = 0x%08x;\n", descriptorStruct.componentSection.flpb); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 36; i++) { + if (descriptorStruct.componentSection.padding[i] != 0xFF) { + for (j = 0; j < 36; j++) { + fprintf(fp, " descriptorStruct.componentSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.componentSection.padding[j]); + } + break; + } else if (i == 35) { + fprintf(fp, " for (i = 0; i < 36; i++) {\n"); + fprintf(fp, " descriptorStruct.componentSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* Flash Descriptor Region Section */ + fprintf(fp, " /* Flash Descriptor Region Section */\n"); + fprintf(fp, " /* FLREG0 (Descriptor) */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg0.BASE = 0x%04x;\n", descriptorStruct.regionSection.flReg0.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg0.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg0.reserved1); + fprintf(fp, " descriptorStruct.regionSection.flReg0.LIMIT = 0x%04x;\n", descriptorStruct.regionSection.flReg0.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg0.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg0.reserved2); + fprintf(fp, " /* FLREG1 (BIOS) */\n"); + fprintf(fp, " /* descriptorStruct.regionSection.flReg1.BASE = 0x%04x; */\n", descriptorStruct.regionSection.flReg1.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + (hasGbe ? GBEREGIONSIZE_8K : 0)) >> FLREGIONBITSHIFT; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg1.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg1.reserved1); + fprintf(fp, " /* descriptorStruct.regionSection.flReg1.LIMIT = 0x%04x; */\n", descriptorStruct.regionSection.flReg1.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg1.LIMIT = ((romSize >> FLREGIONBITSHIFT) - 1); /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg1.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg1.reserved2); + fprintf(fp, " /* FLREG2 (ME) */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg2.BASE = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg2.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg2.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg2.reserved1); + fprintf(fp, " descriptorStruct.regionSection.flReg2.LIMIT = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg2.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg2.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg2.reserved2); + fprintf(fp, " /* FLREG3 (Gbe) */\n"); + fprintf(fp, " /* descriptorStruct.regionSection.flReg3.BASE = 0x%04x; */\n", descriptorStruct.regionSection.flReg3.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg3.BASE = hasGbe ? (DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT) : 0x1fff; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg3.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg3.reserved1); + fprintf(fp, " /* descriptorStruct.regionSection.flReg3.LIMIT = 0x%04x; */\n", descriptorStruct.regionSection.flReg3.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg3.LIMIT = hasGbe ? (GBEREGIONSIZE_8K >> FLREGIONBITSHIFT) : 0x0000; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg3.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg3.reserved2); + fprintf(fp, " /* FLREG4 (Platform) */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg4.BASE = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg4.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg4.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg4.reserved1); + fprintf(fp, " descriptorStruct.regionSection.flReg4.LIMIT = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg4.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg4.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg4.reserved2); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 12; i++) { + if (descriptorStruct.regionSection.padding[i] != 0xFF) { + for (j = 0; j < 12; j++) { + fprintf(fp, " descriptorStruct.regionSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.regionSection.padding[j]); + } + break; + } else if (i == 11) { + fprintf(fp, " for (i = 0; i < 12; i++) {\n"); + fprintf(fp, " descriptorStruct.regionSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* Master Access Section */ + fprintf(fp, " /* Master Access Section */\n"); + fprintf(fp, " /* FLMSTR1 (Host CPU / BIOS) */\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.requesterId = 0x%04x;\n", descriptorStruct.masterAccessSection.flMstr1.requesterId); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.reserved1 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr1.reserved1); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.reserved2 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr1.reserved2); + fprintf(fp, " /* FLMSTR2 (ME) */\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.requesterId = 0x%04x;\n", descriptorStruct.masterAccessSection.flMstr2.requesterId); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.reserved1 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr2.reserved1); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.reserved2 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr2.reserved2); + fprintf(fp, " /* FLMSTR3 (Gbe) */\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.requesterId = 0x%04x;\n", descriptorStruct.masterAccessSection.flMstr3.requesterId); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.fdRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.fdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.biosRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.biosRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.meRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.meRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.gbeRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.gbeRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.pdRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.pdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.reserved1 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.reserved1); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.fdRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.fdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.biosRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.biosRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.meRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.meRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.gbeRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.gbeRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.pdRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.pdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.reserved2 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.reserved2); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 148; i++) { + if (descriptorStruct.masterAccessSection.padding[i] != 0xFF) { + for (j = 0; j < 148; j++) { + fprintf(fp, " descriptorStruct.masterAccessSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.masterAccessSection.padding[j]); + } + break; + } else if (i == 147) { + fprintf(fp, " for (i = 0; i < 148; i++) {\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* ICH straps */ + fprintf(fp, " /* ICH straps */\n"); + fprintf(fp, " /* ICHSTRAP0 */\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.meDisable = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.ichStraps.ichStrap0.meDisable); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.reserved1 = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap0.reserved1); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.tcoMode = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.tcoMode); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.smBusAddress = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap0.smBusAddress); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.bmcMode = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.bmcMode); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.tripPointSelect = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.tripPointSelect); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.reserved2 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.reserved2); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.integratedGbe = hasGbe ? 0x1 : 0x0;\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.lanPhy = hasGbe ? 0x1 : 0x0;\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.reserved3 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.reserved3); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.dmiRequesterId = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.dmiRequesterId); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.smBus2Address = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap0.smBus2Address); + fprintf(fp, " /* ICHSTRAP1 */\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.northMlink = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.northMlink); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.southMlink = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.southMlink); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.meSmbus = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.meSmbus); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.sstDynamic = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.sstDynamic); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.reserved1 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.reserved1); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.northMlink2 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.northMlink2); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.reserved2 = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap1.reserved2); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.reserved3 = 0x%04x;\n", descriptorStruct.ichStraps.ichStrap1.reserved3); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 248; i++) { + if (descriptorStruct.ichStraps.padding[i] != 0xFF) { + for (j = 0; j < 248; j++) { + fprintf(fp, " descriptorStruct.ichStraps.padding[%d] = 0x%02x;\n", j, descriptorStruct.ichStraps.padding[j]); + } + break; + } else if (i == 247) { + fprintf(fp, " for (i = 0; i < 248; i++) {\n"); + fprintf(fp, " descriptorStruct.ichStraps.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* MCH straps */ + fprintf(fp, " /* MCH straps */\n"); + fprintf(fp, " /* MCHSTRAP0 */\n"); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.meDisable = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.mchStraps.mchStrap0.meDisable); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.meBootFromFlash = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.meBootFromFlash); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.tpmDisable = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.mchStraps.mchStrap0.tpmDisable); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.reserved1 = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.reserved1); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.spiFingerprint = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.spiFingerprint); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.meAlternateDisable = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.meAlternateDisable); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.reserved2 = 0x%02x;\n", descriptorStruct.mchStraps.mchStrap0.reserved2); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.reserved3 = 0x%04x;\n", descriptorStruct.mchStraps.mchStrap0.reserved3); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 3292; i++) { + if (descriptorStruct.mchStraps.padding[i] != 0xFF) { + for (j = 0; j < 3292; j++) { + fprintf(fp, " descriptorStruct.mchStraps.padding[%d] = 0x%02x;\n", j, descriptorStruct.mchStraps.padding[j]); + } + break; + } else if (i == 3291) { + fprintf(fp, " for (i = 0; i < 3292; i++) {\n"); + fprintf(fp, " descriptorStruct.mchStraps.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* ME VSCC Table */ + fprintf(fp, " /* ME VSCC Table */\n"); + fprintf(fp, " descriptorStruct.meVsccTable.jid0 = 0x%08x;\n", descriptorStruct.meVsccTable.jid0); + fprintf(fp, " descriptorStruct.meVsccTable.vscc0 = 0x%08x;\n", descriptorStruct.meVsccTable.vscc0); + fprintf(fp, " descriptorStruct.meVsccTable.jid1 = 0x%08x;\n", descriptorStruct.meVsccTable.jid1); + fprintf(fp, " descriptorStruct.meVsccTable.vscc1 = 0x%08x;\n", descriptorStruct.meVsccTable.vscc1); + fprintf(fp, " descriptorStruct.meVsccTable.jid2 = 0x%08x;\n", descriptorStruct.meVsccTable.jid2); + fprintf(fp, " descriptorStruct.meVsccTable.vscc2 = 0x%08x;\n", descriptorStruct.meVsccTable.vscc2); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 4; i++) { + if (descriptorStruct.meVsccTable.padding[i] != 0xFF) { + for (j = 0; j < 4; j++) { + fprintf(fp, " descriptorStruct.meVsccTable.padding[%d] = 0x%02x;\n", j, descriptorStruct.meVsccTable.padding[j]); + } + break; + } else if (i == 3) { + fprintf(fp, " for (i = 0; i < 4; i++) {\n"); + fprintf(fp, " descriptorStruct.meVsccTable.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* Descriptor Map 2 Record */ + fprintf(fp, " /* Descriptor Map 2 Record */\n"); + fprintf(fp, " descriptorStruct.descriptor2Map.meVsccTableBaseAddress = 0x%02x;\n", descriptorStruct.descriptor2Map.meVsccTableBaseAddress); + fprintf(fp, " descriptorStruct.descriptor2Map.meVsccTableLength = 0x%02x;\n", descriptorStruct.descriptor2Map.meVsccTableLength); + fprintf(fp, " descriptorStruct.descriptor2Map.reserved = 0x%04x;\n", descriptorStruct.descriptor2Map.reserved); + fprintf(fp, "\n"); + /* OEM section */ + fprintf(fp, " /* OEM section */\n"); + fprintf(fp, " /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " /* Magic String (ascii characters) */\n"); + for(i = 0; i < 8; i++) { + fprintf(fp, " descriptorStruct.oemSection.magicString[%d] = 0x%02x;\n", i, descriptorStruct.oemSection.magicString[i]); + } + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 248; i++) { + if (descriptorStruct.oemSection.padding[i] != 0xFF) { + for (j = 0; j < 248; j++) { + fprintf(fp, " descriptorStruct.oemSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.oemSection.padding[j]); + } + break; + } else if (i == 247) { + fprintf(fp, " for (i = 0; i < 248; i++) {\n"); + fprintf(fp, " descriptorStruct.oemSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + fprintf(fp, " return descriptorStruct;\n"); + fprintf(fp, "}\n\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} + +/* + * --------------------------------------------------------------------- + * Debugging functions: + * --------------------------------------------------------------------- + */ + +/* + * show debugging info: descriptor region boundaries, in a 4KB struct. + */ +void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStruct, char* romName) +{ + printf("\n"); + + /* Descriptor region */ + printf( + "%s: Descriptor start block: %08x ; Descriptor end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg0.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg0.LIMIT << FLREGIONBITSHIFT + ); + + /* BIOS region */ + printf( + "%s: BIOS start block: %08x ; BIOS end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg1.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg1.LIMIT << FLREGIONBITSHIFT + ); + + /* ME region */ + printf( + "%s: ME start block: %08x ; ME end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg2.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg2.LIMIT << FLREGIONBITSHIFT + ); + + /* GBe region */ + printf( + "%s: GBe start block: %08x ; GBe end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg3.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg3.LIMIT << FLREGIONBITSHIFT + ); + + /* Platform region */ + printf( + "%s: Platform start block: %08x ; Platform end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg4.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg4.LIMIT << FLREGIONBITSHIFT + ); + + return; +} diff --git a/util/ich9deblob/src/descriptor/descriptor.h b/util/ich9deblob/src/descriptor/descriptor.h new file mode 100644 index 0000000..38a55df --- /dev/null +++ b/util/ich9deblob/src/descriptor/descriptor.h @@ -0,0 +1,333 @@ +/* + * descriptor/descriptor.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Purpose: provide struct representing descriptor region. + * Map actual buffers of this regions, directly to instances of these + * structs. This makes working with descriptor really easy. + * + * bit fields used, corresponding to datasheet. See links to datasheets + * and documentation in ich9deblob.c + */ + +/* + * See docs/hcl/x200_remove_me.html for info plus links to datasheet (also linked below) + * + * Info about flash descriptor (read page 845 onwards): + * http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datash… + */ + +#ifndef DESCRIPTORSTRUCT_H +#define DESCRIPTORSTRUCT_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> +#include "../gbe/gbe.h" /* Needed for GBEREGIONSIZE_4K/8K define */ + +/* size of the descriptor in bytes */ +#define DESCRIPTORREGIONSIZE 0x1000 + +/* ROM image sizes in bytes */ +#define ROMSIZE_512KB 0x80000 +#define ROMSIZE_1MB 0x100000 +#define ROMSIZE_2MB 0x200000 +#define ROMSIZE_4MB 0x400000 +#define ROMSIZE_8MB 0x800000 +#define ROMSIZE_16MB 0x1000000 + +/* + * Related to the flash descriptor + * bits 12(0xC)-24(0x18) are represented for words found in the flash descriptor + * To manipulate these easily in C, we shift them by FLREGIONBITSHIFT and then shift them back when done + * (because this is how data is stored in the flash descriptor) + */ +#define FLREGIONBITSHIFT 0xC + +/* + * --------------------------------------------------------------------- + * Descriptor struct representing the data + * --------------------------------------------------------------------- + */ + +/* Flash Valid Signature Register */ +struct FLVALSIG +{ + /* + * 4 bytes. + * descriptor mode = 0FF0A55A (hex, big endian). Note: stored in ROM in little endian order. + * Anything else is considered invalid and will put the system in non-descriptor mode. + */ + uint32_t signature; /* Put 0x0FF0A55A here. confirmed in deblobbed_descriptor.bin */ +}; + +/* */ +struct FLMAP0 +{ + /* least signicant bits */ + uint8_t FCBA : 8; + uint8_t NC : 2; + uint8_t reserved1 : 6; + uint8_t FRBA : 8; + uint8_t NR : 3; + uint8_t reserved2 : 5; + /* most significant bits. */ +}; + +struct FLMAP1 +{ + /* least significant bits */ + uint8_t FMBA : 8; + uint8_t NM : 3; + uint8_t reserved : 5; + uint8_t FISBA : 8; + uint8_t ISL : 8; + /* most significant bits */ +}; + +struct FLMAP2 +{ + /* least significant bits */ + uint8_t FMSBA : 8; + uint8_t MSL : 8; + uint16_t reserved : 16; + /* most significant bits */ +}; + +/* Flash Map Registers */ +struct FLMAPS +{ + struct FLMAP0 flMap0; + struct FLMAP1 flMap1; + struct FLMAP2 flMap2; +}; + +/* Flash Components Register */ +struct FLCOMP +{ + /* least significant bits */ + uint8_t component1Density : 3; + uint8_t component2Density : 3; + uint8_t reserved1 : 2; + uint8_t reserved2 : 8; + uint8_t reserved3 : 1; + uint8_t readClockFrequency : 3; + uint8_t fastReadSupport : 1; + uint8_t fastreadClockFrequency : 3; + uint8_t writeEraseClockFrequency : 3; + uint8_t readStatusClockFrequency : 3; + uint8_t reserved4 : 2; + /* most significant bits */ +}; + +struct COMPONENTSECTIONRECORD +{ + struct FLCOMP flcomp; + uint32_t flill; + uint32_t flpb; + uint8_t padding[36]; +}; + +struct FLREG +{ + /* least significant bits */ + uint16_t BASE : 13; + uint16_t reserved1 : 3; + uint16_t LIMIT : 13; + uint16_t reserved2 : 3; + /* most significant bits */ +}; + +/* Flash Descriptor Region Section */ +/* + * Defines where all the regions begin/end. + * This is very important for disabling ME/AMT + */ +struct REGIONSECTIONRECORD +{ + struct FLREG flReg0; /* Descriptor */ + struct FLREG flReg1; /* BIOS */ + struct FLREG flReg2; /* ME */ + struct FLREG flReg3; /* Gbe */ + struct FLREG flReg4; /* Platform */ + uint8_t padding[12]; +}; + +struct FLMSTR +{ + /* least significant bits */ + uint16_t requesterId : 16; + uint8_t fdRegionReadAccess : 1; + uint8_t biosRegionReadAccess : 1; + uint8_t meRegionReadAccess : 1; + uint8_t gbeRegionReadAccess : 1; + uint8_t pdRegionReadAccess : 1; + uint8_t reserved1 : 3; /* Must be zero, according to datasheet */ + uint8_t fdRegionWriteAccess : 1; + uint8_t biosRegionWriteAccess : 1; + uint8_t meRegionWriteAccess : 1; + uint8_t gbeRegionWriteAccess : 1; + uint8_t pdRegionWriteAccess : 1; + uint8_t reserved2 : 3; /* Must be zero, according to datasheet */ + /* most significant bits */ +}; + +/* Master Access Section */ +struct MASTERACCESSSECTIONRECORD +{ + struct FLMSTR flMstr1; /* Flash Master 1 (Host CPU / BIOS) */ + struct FLMSTR flMstr2; /* Flash Master 2 (ME) */ + struct FLMSTR flMstr3; /* Flash Master 3 (Gbe) */ + uint8_t padding[148]; +}; + +struct ICHSTRAP0 +{ + /* least significant bits */ + /* todo: add MeSmBus2Sel (boring setting) */ + uint8_t meDisable : 1; /* If true, ME is disabled. */ + uint8_t reserved1 : 6; + uint8_t tcoMode : 1; /* TCO Mode: (Legacy,TCO Mode) The TCO Mode, along with the BMCMODE strap, determines the behavior of the IAMT SmBus controller. */ + uint8_t smBusAddress : 7; /* The ME SmBus 7-bit address. */ + uint8_t bmcMode : 1; /* BMC mode: If true, device is in BMC mode. If Intel(R) AMT or ASF using Intel integrated LAN then this should be false. */ + uint8_t tripPointSelect : 1; /* Trip Point Select: false the NJCLK input buffer is matched to 3.3v signal from the external PHY device, true is matched to 1.8v. */ + uint8_t reserved2 : 2; + uint8_t integratedGbe : 1; /* Integrated GbE or PCI Express select: (PCI Express,,Integrated GbE) Defines what PCIe Port 6 is used for. */ + uint8_t lanPhy : 1; /* LANPHYPC_GP12_SEL: Set to 0 for GP12 to be used as GPIO (General Purpose Input/Output), or 1 for GP12 to be used for native mode as LAN_PHYPC for 82566 LCD device */ + uint8_t reserved3 : 3; + uint8_t dmiRequesterId : 1; /* DMI requestor ID security check disable: The primary purpose of this strap is to support server environments with multiple CPUs that each have a different RequesterID that can access the Flash. */ + uint8_t smBus2Address : 7; /* The ME SmBus 2 7-bit address. */ + /* most significant bits */ +}; + +struct ICHSTRAP1 +{ + /* least significant bits */ + uint8_t northMlink : 1; /* North MLink Dynamic Clock Gate Disable : Sets the default value for the South MLink Dynamic Clock Gate Enable registers. */ + uint8_t southMlink : 1; /* South MLink Dynamic Clock Gate Enable : Sets the default value for the South MLink Dynamic Clock Gate Enable registers. */ + uint8_t meSmbus : 1; /* ME SmBus Dynamic Clock Gate Enable : Sets the default value for the ME SMBus Dynamic Clock Gate Enable for both the ME SmBus controllers. */ + uint8_t sstDynamic : 1; /* SST Dynamic Clock Gate Enable : Sets the default value for the SST Clock Gate Enable registers. */ + uint8_t reserved1 : 4; + uint8_t northMlink2 : 1; /* North MLink 2 Non-Posted Enable : 'true':North MLink supports two downstream non-posted requests. 'false':North MLink supports one downstream non-posted requests. */ + uint8_t reserved2 : 7; + uint16_t reserved3 : 16; + /* most significant bits */ +}; + +/* ICH straps */ +struct ICHSTRAPSRECORD +{ + struct ICHSTRAP0 ichStrap0; + struct ICHSTRAP1 ichStrap1; + uint8_t padding[248]; +}; + +struct MCHSTRAP0 +{ + /* least significant bits */ + uint8_t meDisable : 1; /* If true, ME is disabled. */ + uint8_t meBootFromFlash : 1; /* ME boot from Flash - guessed location */ + uint8_t tpmDisable : 1; /* iTPM Disable : When set true, iTPM Host Interface is disabled. When set false (default), iTPM is enabled. */ + uint8_t reserved1 : 3; + uint8_t spiFingerprint : 1; /* SPI Fingerprint Sensor Present: Indicates if an SPI Fingerprint sensor is present at CS#1. */ + uint8_t meAlternateDisable : 1; /* ME Alternate Disable: Setting this bit allows ME to perform critical chipset functions but prevents loading of any ME FW applications. */ + uint8_t reserved2 : 8; + uint16_t reserved3 : 16; + /* most significant bits */ +}; + +/* MCH straps */ +struct MCHSTRAPSRECORD +{ + struct MCHSTRAP0 mchStrap0; + uint8_t padding[3292]; +}; + +/* ME VSCC Table */ +struct MEVSCCTABLERECORD +{ + uint32_t jid0; + uint32_t vscc0; + uint32_t jid1; + uint32_t vscc1; + uint32_t jid2; + uint32_t vscc2; + uint8_t padding[4]; +}; + +/* Descriptor Map 2 Record */ +struct DESCRIPTORMAP2RECORD +{ + /* least significant bits */ + uint8_t meVsccTableBaseAddress : 8; + uint8_t meVsccTableLength : 8; + uint16_t reserved : 16; + /* most significant bits */ +}; + +/* OEM section */ +struct OEMSECTIONRECORD +{ + uint8_t magicString[8]; + uint8_t padding[248]; +}; + +/* 4KiB descriptor region, goes at the beginning of the ROM image */ +struct DESCRIPTORREGIONRECORD +{ + struct FLVALSIG flValSig; /* Flash Valid Signature Register */ + struct FLMAPS flMaps; /* Flash Map Registers */ + struct COMPONENTSECTIONRECORD componentSection; /* Component Section Record */ + struct REGIONSECTIONRECORD regionSection; /* Flash Descriptor Region Section */ + struct MASTERACCESSSECTIONRECORD masterAccessSection; /* Master Access Section */ + struct ICHSTRAPSRECORD ichStraps; /* ICH straps */ + struct MCHSTRAPSRECORD mchStraps; /* MCH straps */ + struct MEVSCCTABLERECORD meVsccTable; /* ME VSCC Table */ + struct DESCRIPTORMAP2RECORD descriptor2Map; /* Descriptor Map 2 Record */ + struct OEMSECTIONRECORD oemSection; /* OEM section */ +}; + +/* + * --------------------------------------------------------------------- + * Function declarations (keep gcc/make happy. check them in descriptor.c) + * --------------------------------------------------------------------- + */ + +struct DESCRIPTORREGIONRECORD descriptorHostRegionsUnlocked(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorMeRegionsForbidden(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorMeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorPlatformRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorDisableMe(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorDisableTpm(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorMoveGbeToStart(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorGbeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterGbe(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterDescriptor(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +struct DESCRIPTORREGIONRECORD descriptorOemString(struct DESCRIPTORREGIONRECORD descriptorStruct); +int descriptorDefinesGbeRegion(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD librebootSetGbeBiosDescriptorRegions(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +uint8_t componentDensity(unsigned int romSizeInBytes); +struct DESCRIPTORREGIONRECORD librebootDescriptorStructFromFactory(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +int notCreatedHFileForDescriptorCFile(char* outFileName, char* cFileName); +int notCreatedCFileFromDescriptorStruct(struct DESCRIPTORREGIONRECORD descriptorStruct, char* outFileName, char* headerFileName); +void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStruct, char* romName); + +#endif diff --git a/util/ich9deblob/src/gbe/gbe.c b/util/ich9deblob/src/gbe/gbe.c new file mode 100644 index 0000000..d04b8f2 --- /dev/null +++ b/util/ich9deblob/src/gbe/gbe.c @@ -0,0 +1,454 @@ +/* + * gbe/gbe.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Provide gbe related functions. + */ + +/* structs describing the data from gbe region */ +#include "gbe.h" + +/* + * --------------------------------------------------------------------- + * Gbe functions: + * --------------------------------------------------------------------- + */ + +/* gbe checksum calculation (algorithm based on datasheet) */ +uint16_t gbeGetChecksumFrom4kBuffer(uint16_t* gbeWord, uint16_t desiredValue, int gbeRegionBase) +{ + int wordOffset; + uint16_t total = 0; + + for (wordOffset = 0; wordOffset < 0x3F; wordOffset++) + total += gbeWord[wordOffset + (gbeRegionBase>>1)]; + + return desiredValue - total; +} + +/* checksum calculation for 4k gbe struct (algorithm based on datasheet) */ +uint16_t gbeGetChecksumFrom4kStruct(struct GBEREGIONRECORD_4K gbeStruct4k, uint16_t desiredValue) +{ + return gbeGetChecksumFrom4kBuffer((uint16_t*)&gbeStruct4k, desiredValue, 0); +} + +/* modify the gbe region extracted from a factory.rom dump */ +struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8K gbeStruct8k) +{ + unsigned int i; + + /* + * http://www.intel.co.uk/content/dam/doc/application-note/82573-nvm-map-appl-… + * That is a datasheet for a later chipset. Word 40H-53H seems (as per this datasheet) to be for AMT. + * Writing over it doesn't seem to cause any harm, since the ME/AMT is already removed in libreboot. + */ + for(i = 0; i < sizeof(gbeStruct8k.backup.padding); i++) { + gbeStruct8k.backup.padding[i] = 0xFF; /* FF is correct. In the struct, this is a char buffer. */ + } /* We really only need to do this for words 40h-53h, but let's just nuke the whole lot. It's all 0xFF anyway. */ + + /* Fix the checksum */ + gbeStruct8k.backup.checkSum = gbeGetChecksumFrom4kStruct(gbeStruct8k.backup, GBECHECKSUMTOTAL); + + /* Main Gbe region on X200 (as shipped by Lenovo) is broken. Fix it by over-writing it with the contents of the backup */ + memcpy(&gbeStruct8k.main, &gbeStruct8k.backup, GBEREGIONSIZE_4K); + + return gbeStruct8k; +} + +/* + * --------------------------------------------------------------------- + * C code generator (self-writing code) + * --------------------------------------------------------------------- + */ + +/* + * Generate a C (.h) header file for the C source file made by notCreatedCFileFromGbeStruct4k() + * + * Output it to a file. + */ +int notCreatedHFileForGbeCFile(char* outFileName, char* cFileName) +{ + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .h header file for the gbe-generating C code (%s) */\n\n", cFileName); + + fprintf(fp, "#ifndef ICH9GEN_MKGBE_H\n"); + fprintf(fp, "#define ICH9GEN_MKGBE_H\n\n"); + + fprintf(fp, "#include <stdio.h>\n"); + fprintf(fp, "#include <string.h>\n"); + fprintf(fp, "#include \"../gbe/gbe.h\"\n\n"); + + fprintf(fp, "struct GBEREGIONRECORD_4K generatedGbeStruct4k();\n"); + fprintf(fp, "struct GBEREGIONRECORD_8K generatedGbeStruct8k();\n\n"); + + fprintf(fp, "#endif\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} +/* + * Generate a C source file that initializes the same data from a given + * 4KiB Gbe data structure. + * + * It will simply copy the 4KiB struct at the end to make a full 8KiB struct. + * So just pass a working 4KiB Gbe struct here and you're good to go. + * + * Output it to a file. + */ +int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* outFileName, char* headerFileName) +{ + int i; + int paddingSize; + int paddingIdentical; + + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .c source file for the gbe-generating C code */\n\n"); + + fprintf(fp, "#include \"%s\"\n\n", headerFileName); + + fprintf(fp, "/* Generate a 4KiB Gbe struct, with default values. */\n"); + fprintf(fp, "/* Read ../gbe/gbe.h for an explanation of the default values used here */\n\n"); + + fprintf(fp, "struct GBEREGIONRECORD_4K generatedGbeStruct4k()\n"); + fprintf(fp, "{\n"); + fprintf(fp, " int i;\n"); + fprintf(fp, " struct GBEREGIONRECORD_4K gbeStruct4k;\n"); + fprintf(fp, "\n"); + /* Words 00h to 02h: MAC Address */ + fprintf(fp, " /* MAC address (words 00h to 02h) */\n"); + fprintf(fp, " /* see ../gbe/gbe.c */\n"); + for (i = 0; i < 6; i++) { + fprintf(fp, " gbeStruct4k.macAddress[%d] = 0x%02x;\n", i, gbeStruct4k.macAddress[i]); + } + fprintf(fp, "\n"); + /* Word 03h (Reserved) */ + fprintf(fp, " /* Word 03h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord03h.reserved1_0 = 0x%02x;\n", gbeStruct4k.reservedWord03h.reserved1_0); + fprintf(fp, " gbeStruct4k.reservedWord03h.reserved1_1 = 0x%01x;\n", gbeStruct4k.reservedWord03h.reserved1_1); + fprintf(fp, " gbeStruct4k.reservedWord03h.ibaLom = 0x%01x;\n", gbeStruct4k.reservedWord03h.ibaLom); + fprintf(fp, " gbeStruct4k.reservedWord03h.reserved2 = 0x%01x;\n", gbeStruct4k.reservedWord03h.reserved2); + fprintf(fp, "\n"); + /* Word 04h (Reserved) */ + fprintf(fp, " /* Word 04h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord04h = 0x%04x;\n", gbeStruct4k.reservedWord04h); + fprintf(fp, "\n"); + /* Word 05h (Image Version Information) */ + fprintf(fp, " /* Word 05h (Image Version Information) */\n"); + fprintf(fp, " gbeStruct4k.imageVersionInformation = 0x%04x;\n", gbeStruct4k.imageVersionInformation); + fprintf(fp, "\n"); + /* Words 06h and 07h (Reserved) */ + fprintf(fp, " /* Words 06h and 07h (Reserved) */\n"); + for (i = 0; i < 2; i++) { + fprintf(fp, " gbeStruct4k.reservedWords06h07h[%d] = 0x%04x;\n", i, gbeStruct4k.reservedWords06h07h[i]); + } + fprintf(fp, "\n"); + /* Words 08h and 09h (PBA Low and PBA High) */ + fprintf(fp, " /* Word 08h and 09h (PBA Low and PBA High) */\n"); + fprintf(fp, " gbeStruct4k.pbaLow = 0x%04x;\n", gbeStruct4k.pbaLow); + fprintf(fp, " gbeStruct4k.pbaHigh = 0x%04x;\n", gbeStruct4k.pbaHigh); + fprintf(fp, "\n"); + /* Word 0Ah (PCI Initialization Control Word) */ + fprintf(fp, " /* Word 0Ah (PCI Initialization Control Word) */\n"); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.loadVendorDeviceId = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.loadVendorDeviceId); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.loadSubsystemId = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.loadSubsystemId); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved1 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved1); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved2 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved2); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.pmEnable = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.pmEnable); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.auxPwr = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.auxPwr); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved3 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved3); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved4 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved4); + fprintf(fp, "\n"); + /* Word 0Bh (Subsystem ID) */ + fprintf(fp, " /* Word 0Bh (Subsystem ID) */\n"); + fprintf(fp, " gbeStruct4k.subsystemId = 0x%04x;\n", gbeStruct4k.subsystemId); + fprintf(fp, "\n"); + /* Word 0Ch (Subsystem Vendor ID) */ + fprintf(fp, " /* Word 0Ch (Subsystem Vendor ID) */\n"); + fprintf(fp, " gbeStruct4k.subsystemVendorId = 0x%04x;\n", gbeStruct4k.subsystemVendorId); + fprintf(fp, "\n"); + /* Word 0Dh (Device ID) */ + fprintf(fp, " /* Word 0Dh (Device ID) */\n"); + fprintf(fp, " gbeStruct4k.deviceId = 0x%04x;\n", gbeStruct4k.deviceId); + fprintf(fp, "\n"); + /* Word 0Eh (Vendor ID) */ + fprintf(fp, " /* Word 0Eh (Vendor ID) */\n"); + fprintf(fp, " gbeStruct4k.vendorId = 0x%04x;\n", gbeStruct4k.vendorId); + fprintf(fp, "\n"); + /* Word 0Fh (Device Revision ID) */ + fprintf(fp, " /* Word 0Fh (Device Revision ID) */\n"); + fprintf(fp, " gbeStruct4k.deviceRevId = 0x%04x;\n", gbeStruct4k.deviceRevId); + fprintf(fp, "\n"); + /* Word 10h (LAN Power Consumption) */ + fprintf(fp, " /* Word 10h (LAN Power Consumption) */\n"); + fprintf(fp, " gbeStruct4k.lanPowerConsumption.lanD3Power = 0x%02x;\n", gbeStruct4k.lanPowerConsumption.lanD3Power); + fprintf(fp, " gbeStruct4k.lanPowerConsumption.reserved = 0x%01x;\n", gbeStruct4k.lanPowerConsumption.reserved); + fprintf(fp, " gbeStruct4k.lanPowerConsumption.lanD0Power = 0x%02x;\n", gbeStruct4k.lanPowerConsumption.lanD0Power); + fprintf(fp, "\n"); + /* Words 11h and 12h (Reserved) */ + fprintf(fp, " /* Words 11h and 12h (Reserved) */\n"); + for (i = 0; i < 2; i++) { + fprintf(fp, " gbeStruct4k.reservedWords11h12h[%d] = 0x%04x;\n", i, gbeStruct4k.reservedWords11h12h[i]); + } + fprintf(fp, "\n"); + /* Word 13h (Shared Initialization Control Word) */ + fprintf(fp, " /* Word 13h (Shared Initialization Control Word) */\n"); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved1 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved1); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.forceDuplex = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.forceDuplex); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.forceSpeedEnable = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.forceSpeedEnable); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved2_0 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved2_0); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved2_1 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved2_1); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.phyPowerDownEnable = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.phyPowerDownEnable); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved3 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved3); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved4 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved4); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.sign = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.sign); + fprintf(fp, "\n"); + /* Word 14h (Extended Configuration Control Word 1) */ + fprintf(fp, " /* Word 14h (Extended Configuration Control Word 1) */\n"); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.extendedConfigurationPointer = 0x%03x;\n", gbeStruct4k.extendedConfigurationControlWord1.extendedConfigurationPointer); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.oemWriteEnable = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.oemWriteEnable); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.reserved1 = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.reserved1); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.reserved2 = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.reserved2); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.reserved3 = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.reserved3); + fprintf(fp, "\n"); + /* Word 15h (Extended Configuration Control Word 2) */ + fprintf(fp, " /* Word 15h (Extended Configuration Control Word 2) */\n"); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord2.reserved = 0x%02x;\n", gbeStruct4k.extendedConfigurationControlWord2.reserved); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord2.extendedPhyLength = 0x%02x;\n", gbeStruct4k.extendedConfigurationControlWord2.extendedPhyLength); + fprintf(fp, "\n"); + /* Word 16h (Extended Configuration Control Word 3) */ + fprintf(fp, " /* Word 16h (Extended Configuration Control Word 3) */\n"); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord3 = 0x%04x;\n", gbeStruct4k.extendedConfigurationControlWord3); + fprintf(fp, "\n"); + /* Word 17h (LED 1 Configuration and Power Management) */ + fprintf(fp, " /* Word 17h (LED 1 Configuration and Power Management) */\n"); + fprintf(fp, " gbeStruct4k.ledCtl1.led1Mode = 0x%01x;\n", gbeStruct4k.ledCtl1.led1Mode); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved1 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved1); + fprintf(fp, " gbeStruct4k.ledCtl1.led1BlinkMode = 0x%01x;\n", gbeStruct4k.ledCtl1.led1BlinkMode); + fprintf(fp, " gbeStruct4k.ledCtl1.led1Invert = 0x%01x;\n", gbeStruct4k.ledCtl1.led1Invert); + fprintf(fp, " gbeStruct4k.ledCtl1.led1Blink = 0x%01x;\n", gbeStruct4k.ledCtl1.led1Blink); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved2 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved2); + fprintf(fp, " gbeStruct4k.ledCtl1.lpluEnable = 0x%01x;\n", gbeStruct4k.ledCtl1.lpluEnable); + fprintf(fp, " gbeStruct4k.ledCtl1.lpluEnableNonD0a = 0x%01x;\n", gbeStruct4k.ledCtl1.lpluEnableNonD0a); + fprintf(fp, " gbeStruct4k.ledCtl1.gbeDisableNonD0a = 0x%01x;\n", gbeStruct4k.ledCtl1.gbeDisableNonD0a); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved3 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved3); + fprintf(fp, " gbeStruct4k.ledCtl1.gbeDisable = 0x%01x;\n", gbeStruct4k.ledCtl1.gbeDisable); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved4 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved4); + fprintf(fp, "\n"); + /* Word 18h (LED 0 and 2 Configuration Defaults) */ + fprintf(fp, " /* Word 18h (LED 0 and 2 Configuration Defaults) */\n"); + fprintf(fp, " gbeStruct4k.ledCtl02.led0Mode = 0x%01x;\n", gbeStruct4k.ledCtl02.led0Mode); + fprintf(fp, " gbeStruct4k.ledCtl02.reserved1 = 0x%01x;\n", gbeStruct4k.ledCtl02.reserved1); + fprintf(fp, " gbeStruct4k.ledCtl02.led0BlinkMode = 0x%01x;\n", gbeStruct4k.ledCtl02.led0BlinkMode); + fprintf(fp, " gbeStruct4k.ledCtl02.led0Invert = 0x%01x;\n", gbeStruct4k.ledCtl02.led0Invert); + fprintf(fp, " gbeStruct4k.ledCtl02.led0Blink = 0x%01x;\n", gbeStruct4k.ledCtl02.led0Blink); + fprintf(fp, " gbeStruct4k.ledCtl02.led2Mode = 0x%01x;\n", gbeStruct4k.ledCtl02.led2Mode); + fprintf(fp, " gbeStruct4k.ledCtl02.reserved2 = 0x%01x;\n", gbeStruct4k.ledCtl02.reserved2); + fprintf(fp, " gbeStruct4k.ledCtl02.led2BlinkMode = 0x%01x;\n", gbeStruct4k.ledCtl02.led2BlinkMode); + fprintf(fp, " gbeStruct4k.ledCtl02.led2Invert = 0x%01x;\n", gbeStruct4k.ledCtl02.led2Invert); + fprintf(fp, " gbeStruct4k.ledCtl02.led2Blink = 0x%01x;\n", gbeStruct4k.ledCtl02.led2Blink); + fprintf(fp, "\n"); + /* Word 19h (Reserved) */ + fprintf(fp, " /* Word 19h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord19h = 0x%04x;\n", gbeStruct4k.reservedWord19h); + fprintf(fp, "\n"); + /* Word 1Ah (Reserved) */ + fprintf(fp, " /* Word 1Ah (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Ah = 0x%04x;\n", gbeStruct4k.reservedWord1Ah); + fprintf(fp, "\n"); + /* Word 1Bh (Reserved) */ + fprintf(fp, " /* Word 1Bh (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Bh = 0x%04x;\n", gbeStruct4k.reservedWord1Bh); + fprintf(fp, "\n"); + /* Word 1Ch (Reserved) */ + fprintf(fp, " /* Word 1Ch (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Ch = 0x%04x;\n", gbeStruct4k.reservedWord1Ch); + fprintf(fp, "\n"); + /* Word 1Dh (Reserved) */ + fprintf(fp, " /* Word 1Dh (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Dh = 0x%04x;\n", gbeStruct4k.reservedWord1Dh); + fprintf(fp, "\n"); + /* Word 1Eh (Device ID for Intel 82567LM gigabit ethernet controller) */ + fprintf(fp, " /* Word 1Eh (Device ID for Intel 82567LM gigabit ethernet controller) */\n"); + fprintf(fp, " gbeStruct4k._82567lmDeviceId = 0x%04x;\n", gbeStruct4k._82567lmDeviceId); + fprintf(fp, "\n"); + /* Word 1Fh (Device ID for Intel 82567LF gigabit ethernet controller) */ + fprintf(fp, " /* Word 1Fh (Device ID for Intel 82567LF gigabit ethernet controller) */\n"); + fprintf(fp, " gbeStruct4k._82567lfDeviceId = 0x%04x;\n", gbeStruct4k._82567lfDeviceId); + fprintf(fp, "\n"); + /* Word 20h (Reserved) */ + fprintf(fp, " /* Word 20h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord20h = 0x%04x;\n", gbeStruct4k.reservedWord20h); + fprintf(fp, "\n"); + /* Word 21h (Device ID for Intel 82567V gigabit ethernet controller) */ + fprintf(fp, " /* Word 21h (Device ID for Intel 82567V gigabit ethernet controller) */\n"); + fprintf(fp, " gbeStruct4k._82567vDeviceId = 0x%04x;\n", gbeStruct4k._82567vDeviceId); + fprintf(fp, "\n"); + /* Word 22h (Reserved) */ + fprintf(fp, " /* Word 22h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord22h = 0x%04x;\n", gbeStruct4k.reservedWord22h); + fprintf(fp, "\n"); + /* Word 23h (Reserved) */ + fprintf(fp, " /* Word 23h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord23h = 0x%04x;\n", gbeStruct4k.reservedWord23h); + fprintf(fp, "\n"); + /* Words 24h to 2Fh (Reserved) */ + fprintf(fp, " /* Words 24h to 2Fh (Reserved) */\n"); + for (i = 0; i < 12; i++) { + fprintf(fp, " gbeStruct4k.reservedWords24to2Fh[%d] = 0x%04x;\n", i, gbeStruct4k.reservedWords24to2Fh[i]); + } + fprintf(fp, "\n"); + /* Words 30h to 3Eh (PXE Software Region) */ + fprintf(fp, " /* Words 30h to 3Eh (PXE Software Region) */\n"); + fprintf(fp, " /* Boot Agent Main Setup Options (Word 30h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.protocolSelect = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.protocolSelect); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved1 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.defaultBootSelection = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.defaultBootSelection); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved2 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved2); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.promptTime = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.promptTime); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.displaySetupMessage = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.displaySetupMessage); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved3 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved3); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceSpeed = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceSpeed); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceFullDuplex = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceFullDuplex); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved4 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved4); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.efiPresence = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.efiPresence); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.pxePresence = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.pxePresence); + fprintf(fp, " /* Boot Agent Configuration Customization Options (Word 31h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableSetupMenu = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableSetupMenu); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableTitleMessage = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableTitleMessage); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableProtocolSelect = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableProtocolSelect); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableBootSelection = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableBootSelection); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableLegacyWakeupSupport = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableLegacyWakeupSupport); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableFlashUpdate = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableFlashUpdate); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved1 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.ibaBootOrderSetupMode = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.ibaBootOrderSetupMode); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved2 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved2); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.signature = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.signature); + fprintf(fp, " /* Boot Agent Configuration Customization Options (Word 32h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber = 0x%02x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.minorVersionNumber = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.minorVersionNumber); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.majorVersionNumber = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.majorVersionNumber); + fprintf(fp, " /* IBA Capabilities (Word 33h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.baseCodePresent = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.baseCodePresent); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.undiCapabilityPresent = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.undiCapabilityPresent); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved1 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.efiUndiCapabilityPresent = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.efiUndiCapabilityPresent); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_0 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_0); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_1 = 0x%02x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.signature = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.signature); + fprintf(fp, " /* Padding (Words 34h to 3Eh) */\n"); + for (i = 0; i < 11; i++) { + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[%d] = 0x%04x;\n", i, gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[i]); + } + fprintf(fp, "\n"); + /* Word 3Fh (Checksum) */ + fprintf(fp, " /* Word 3Fh (Checksum) */\n"); + fprintf(fp, " gbeStruct4k.checkSum = 0x%04x;\n", gbeStruct4k.checkSum); + fprintf(fp, "\n"); + /* The rest of Gbe is just padding */ + paddingSize = sizeof(gbeStruct4k.padding); + paddingIdentical = 1; /* Assume that it's all 0xFF, then try to disprove it */ + for (i = 0; i < paddingSize; i++) { /* check whether contents differ */ + if (gbeStruct4k.padding[i] != 0xFF) { + paddingIdentical = 0; + break; + } + } + if (!paddingIdentical) { + fprintf(fp, " /* The rest of Gbe (word 40h or byte 80h onwards) is just padding */\n"); + for (i = 0; i < paddingSize; i++) { /* contents are not all 0xFF, just spit them all out one by one */ + fprintf(fp, " gbeStruct4k.padding[%d] = 0x%02x;\n", i, gbeStruct4k.padding[i]); + } + } else { /* contents are all 0xFF. Generate a small for loop that sets them all to 0xFF */ + fprintf(fp, " /* The rest of Gbe (word 40h or byte 80h onwards) is just padding (0xFF) */\n"); + fprintf(fp, " for (i = 0; i < %d; i++) {\n", paddingSize); + fprintf(fp, " gbeStruct4k.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + } + fprintf(fp, "\n"); + fprintf(fp, " return gbeStruct4k;\n"); + fprintf(fp, "}\n\n"); + + fprintf(fp, "struct GBEREGIONRECORD_8K generatedGbeStruct8k()\n"); + fprintf(fp, "{\n"); + fprintf(fp, " struct GBEREGIONRECORD_8K gbeStruct8k;\n"); + fprintf(fp, " gbeStruct8k.main = generatedGbeStruct4k();\n"); + fprintf(fp, " memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K);\n"); + fprintf(fp, " return gbeStruct8k;\n"); + fprintf(fp, "}\n\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} + +/* + * --------------------------------------------------------------------- + * Debugging functions: + * --------------------------------------------------------------------- + */ + +/* + * show debugging info: show calculated (correct) gbe checksum and what + * is actually stored, in a 4K gbe struct. Only for a single region. + */ +void printGbeChecksumDataFromStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* romName, char* regionName) +{ + printf( + "%s Gbe (%s): calculated Gbe checksum: 0x%hx and actual GBe checksum: 0x%hx\n", + romName, + regionName, + gbeGetChecksumFrom4kStruct(gbeStruct4k, GBECHECKSUMTOTAL), + gbeStruct4k.checkSum + ); + + return; +} + +/* + * show debugging info: show calculated (correct) gbe checksum and what + * is actually stored, in a 8K gbe struct. Do so for main and backup regions. + */ +void printGbeChecksumDataFromStruct8k(struct GBEREGIONRECORD_8K gbeStruct8k, char* romName) +{ + printGbeChecksumDataFromStruct4k(gbeStruct8k.main, romName, "main"); + printGbeChecksumDataFromStruct4k(gbeStruct8k.backup, romName, "backup"); + + return; +} diff --git a/util/ich9deblob/src/gbe/gbe.h b/util/ich9deblob/src/gbe/gbe.h new file mode 100644 index 0000000..4947494 --- /dev/null +++ b/util/ich9deblob/src/gbe/gbe.h @@ -0,0 +1,435 @@ +/* + * gbe/gbe.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Purpose: provide struct representing gbe region. + * Map actual buffers of this regions, directly to instances of these + * structs. This makes working with gbe really easy. + */ + +/* + * bit fields used, corresponding to datasheet. See links to datasheets + * and documentation in ich9deblob.c + */ + + /* + * See docs/hcl/x200_remove_me.html for info plus links to datasheet (also linked below) + * + * Info about Gbe region (read whole datasheet): + * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-… + * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-… + */ + +#ifndef GBESTRUCT_H +#define GBESTRUCT_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> +#include "../descriptor/descriptor.h" + +/* Size of the full gbe region in bytes */ +#define GBEREGIONSIZE_8K 0x2000 +/* + * Size of each sub-region in gbe. + * gbe contains two regions which + * can be identical: main and backup. + * These are each half the size of the full region + */ +#define GBEREGIONSIZE_4K 0x1000 + +/* + * When adding up the first 0x3F 16-bit words + * in a 4KiB GBE region, it should be equal + * to 0xBABA + */ +#define GBECHECKSUMTOTAL 0xBABA + +/* + * These will have a modified descriptor+gbe based on what's in the factory.rom + * These will be joined into a single 12KiB buffer (descriptor, then gbe) and saved to a file + * NOTE: The GBE region of 8K is actually 2x 4K regions in a single region; both 4K blocks can be identical (and by default, are) + * The 2nd one is a "backup", but we don't know when it's used. perhaps it's used when the checksum on the first one does not match? + */ + +/* + * --------------------------------------------------------------------- + * Gbe struct representing the data: + * --------------------------------------------------------------------- + */ + +struct GBE_RESERVED_WORD_03H { + /* least significant bits */ + uint8_t reserved1_0 : 8; /* bits should all be set to zero */ + uint8_t reserved1_1 : 3; /* ^ part of above. Separated so that the bitfields align */ + uint8_t ibaLom : 1; /* set to 1 for intel boot agent to work (i.e. set it to 0) */ + uint8_t reserved2 : 4; /* bits should all be set to zero */ + /* most significant bits */ +}; + +/* Word 0A */ +struct GBE_PCI_INITIALIZATION_CONTROL_WORD { + /* least significant bits */ + uint8_t loadVendorDeviceId : 1; /* 1 = load from NVM. 0 = load from MAC fuses. It's 1 in my deblobbed_descriptor.bin */ + uint8_t loadSubsystemId : 1; /* 1 = load from NVM. 0 = load from MAC fuses. It's 1 in my deblobbed_descriptor.bin */ + uint8_t reserved1 : 1; /* Reserved. Set to 0 (according to datasheet). 0 in my deblobbed_descriptor.bin */ + uint8_t reserved2 : 3; /* Reserved. Set them to 0 (according to datasheet). 0 in my deblobbed_descriptor.bin */ + uint8_t pmEnable : 1; /* Power Management Enable. 1=Enable. It's 1 in my deblobbed_descriptor.bin */ + uint8_t auxPwr : 1; /* Auxiliary Power Indication. See datasheet. it's 1 in my deblobbed_descriptor.bin */ + uint8_t reserved3 : 4; /* Reserved. Set to 0000 (according to datasheet). */ + uint8_t reserved4 : 4; /* Reserved. Set to 0001 (according to datasheet). */ + /* most significant bits */ +}; + +/* Word 10h. */ +struct GBE_LAN_POWER_CONSUMPTION { + /* least significant bits */ + uint8_t lanD3Power : 5; /* It's 00001b (0x1) in deblobbed_descriptor.bin */ + uint8_t reserved : 3; /* Reserved. These bits should all be 0. confirmed from deblobbed_descriptor.bin */ + uint8_t lanD0Power : 8; /* default value: 0x0D (according to datasheet). confirmed from deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* Word 13h */ +struct GBE_SHARED_INITIALIZATION_CONTROL_WORD { + /* least significant bits */ + uint8_t reserved1 : 3; /* Reserved. These bits should be set to 101 (0x5) in binary (according to datasheet and deblobbed_descriptor.bin) */ + uint8_t forceDuplex : 1; /* Hardware default is 0 according to datasheet and deblobbed_descriptor.bin. Presumably to set whether the chipset is to operate at full- or half-duplex */ + uint8_t forceSpeedEnable : 1; /* Hardware default is 0. Presumably to limited speed eg 10, 10/100, 10/100/1000 */ + uint8_t reserved2_0 : 3; /* Reserved. All bits should be set to 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved2_1 : 1; /* ^ part of above. separated so that bitfields align */ + uint8_t phyPowerDownEnable : 1; /* PHY Power Down in D3/Dr (if WoL is disabled), 1 means Enable power down. deblobbed_descriptor.bin says 1 */ + uint8_t reserved3 : 1; /* Reserved. Should be set to 1 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved4 : 3; /* Reserved. These bits should all be 0 according to datasheet and deblobbed_descriptor.bin */ + /* ^ reserved4: indicates whether a valid NVM is present. If invalid, MAC does not read NVM and uses default values. */ + /* 00 = invalid NVM, 01 = invalid NVM, 10 = valid NVM present, 11 = invalid NVM */ + /* Default should be 10 (binary) according to datasheet and deblobbed_descriptor.bin */ + uint8_t sign : 2; /* Make sure to set this to 0x2 (10 in binary) */ + /* most significant bits */ +}; + +/* Word 14h */ +struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_1 { + /* least significant bits */ + uint16_t extendedConfigurationPointer: 12; /* dword: base address of extended configuration area in NVM. should not be zero. Default is 020h according to datasheet and deblobbed_descriptor.bin */ + uint8_t oemWriteEnable : 1; /* 1=enable. if set, loads oem bits from phy_ctrl register to the 82567. loaded to EXTCNF_CTRL register. default is 1 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved1 : 1; /* Reserved. default value 1 according to datasheet and deblobed_descriptor.bin */ + uint8_t reserved2 : 1; /* Reserved. default value 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved3 : 1; /* Reserved. default value 0 according to datasheet and deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* Word 15h */ +struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_2 { + /* least significant bits */ + uint8_t reserved : 8; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t extendedPhyLength : 8; /* dword: size of extended phy configuration area. most be 0 if phy config area is disabled. default is 0000101 (binary) or 05 (hex) according to datasheet, but 00001010 (0A) according to deblobbed_descriptor.bin. Is 0000101 (in the datasheet) a typo that actually means 00001010? */ + /* most significant bits */ +}; + +/* + * Word 17h: LED 1 Configuration and Power Management + * + * Default values for LEDCTL register fields controlling LED1 (LINK_1000) + * output behaviours and OEM fields that define PHY power management + * parameters loaded to the PHY_CTRL register. + */ +struct LED_CTL_1 { + /* least significant bits */ + + /* See page 16 in the datasheet to show the different modes. deblobbed_descriptor.bin has "ACTIVITY" mode set */ + uint8_t led1Mode : 4; /* Default value 0111 (bin) 7 (hex) says datasheet. 1011 (bin) B (hex) according to deblobbed_descriptor.bin */ + + uint8_t reserved1 : 1; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led1BlinkMode : 1; /* 0 = slow blink, 1 = fast blink. should be identical to led0 blink mode. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + /* By setting this and led0 blink mode (see word 18h) to 1, you could enable a faster blinking on the LED's where the ethernet cable goes + * on the gigabit ethernet port. Not really useful. Slow blink is fine, and probably better (the LED will probably last longer) */ + + uint8_t led1Invert : 1; /* initial value of LED1_IVRT field. 0 = led1 has active low output, 1 is high active output. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led1Blink : 1; /* 1 = led1 blinks, 0 = it does not. default 0 according to datasheet, but it's 1 in deblobbed_descriptor.bin */ + uint8_t reserved2 : 1; /* Reserved. should be 1 according to datasheet and deblobbed_descriptor.bin */ + uint8_t lpluEnable : 1; /* Low Power Link Up. Enable links at lowest supported speed by both link partners in all power states. 1=enabled(all power states), 0=disabled. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t lpluEnableNonD0a : 1; /* Low Power Link up (non-D0a states). Same as above but only for non-D0a states. default is 1 according to and deblobbed_descriptor.bin */ + uint8_t gbeDisableNonD0a : 1; /* If set to 1, disable gigabit speeds in non-D0a power states. Must be 1 (according to datasheet) because GbE is not supported in Sx mode. It's also set to 1 in deblobbed_descriptor.bin */ + uint8_t reserved3 : 2; /* Reserved. Datasheet says both bits should be 0 (confirmed in deblobbed_descriptor.bin) */ + uint8_t gbeDisable : 1; /* When 1, gigabit speeds are disabled in all power states including D0a. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved4 : 1; /* Reserved. Should be 1, according to datasheet and deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* + * Word 18: LED 0 and 2 Configuration Defaults + * + * Hardware defaults for LEDCTL register fields controlling LED0 (LINK/ACTIVITY) + * and LED2 (LINK_100) output behaviours. + */ +struct LED_CTL_02 { + /* least significant bits */ + + /* see page 16 in datasheet to show the different modes. deblobbed_descriptor has "LINK-UP" mode set */ + uint8_t led0Mode : 4; /* default value 0100 (bin) or 4 (hex) according to datasheet. It's 0010 (bin) or 2 (hex) according to deblobbed_descriptor.bin */ + + uint8_t reserved1 : 1; /* Reserved. Should be set to 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led0BlinkMode : 1; /* This should be the same as led1BlinkMode (see word 17h). Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led0Invert : 1; /* initial value of LED0_IVRT field. 0 = led0 has active low output, 1 is high active output. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led0Blink : 1; /* LED0_BLINK field. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + + /* see page 16 in datasheet to shew the different modes. deblobbed_descriptor has "LINK_100" mode set */ + uint8_t led2Mode : 4; /* default value 0110 (bin) or 6 (hex) according to datasheet and deblobbed_descriptor.bin */ + + uint8_t reserved2 : 1; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led2BlinkMode : 1; /* 0 = slow blink. 1 = fast. default 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led2Invert : 1; /* LED2_IVRT field. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led2Blink : 1; /* LED2_BLINK field. should be 0 according to datasheet and deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* Word 30h */ +struct GBE_PXE_BOOT_AGENT_MAIN_SETUP_OPTIONS { + /* least significant bits */ + uint8_t protocolSelect : 2; /* Default 00 binary (PXE) according to datasheet. 01 is reserved. 10/11 are undefined. deblobbed_descriptor.bin says 00 */ + uint8_t reserved1 : 1; /* Reserved. deblobbed_descriptor.bin says 0 */ + uint8_t defaultBootSelection : 2; /* deblobbed_descriptor.bin says 00 (binary). 00 is network boot, then local. 01 is local boot, then network. 10 is network boot only. 11 is local boot only */ + uint8_t reserved2 : 1; /* Reserved. deblobbed_descriptor.bin says 0. */ + uint8_t promptTime : 2; /* deblobbed_descriptor.bin says 00. delay for how long "press ctrl-s" setup prompt message appears. 00 = 2 secs, 01 is 3 secs, 10 is 5 secs, 11 is 0 secs. */ + uint8_t displaySetupMessage : 1; /* default 1 says datasheet. deblobbed_descriptor.bin says 1. if 1, "ctrl-s" setup prompt message appears after the title message. */ + uint8_t reserved3 : 1; /* Datasheet says to set 0. deblobbed_descriptor.bin says 0. */ + uint8_t forceSpeed : 2; /* deblobbed_descriptor.bin says 00. 00 = auto-negotiate, 01 = 10Mbps, 10 = 100Mbps, 11 = "not allowed" */ + uint8_t forceFullDuplex : 1; /* deblobbed_descriptor.bin says 0. Only relevant when bits 10/11 are set; if so, then: 0 = half duplex, 1 = full duplex */ + uint8_t reserved4 : 1; /* Reserved. deblobbed_descriptor.bin says 0. datasheet recommends 0. */ + uint8_t efiPresence : 1; /* 1 means that an EFI image is present (0 means not present). deblobbed_descriptor.bin says 0. if 1, eeprom word 33h (efi version) becomes valid. if pxePresent is 1, that means EFI and PXE are both present.*/ + uint8_t pxePresence : 1; /* 0 means that a PXE image is present. 1 means to pxe present. deblobbed_descriptor.bin says 0. if 0, then word 32h (PXE version) in eeprom becomes valid */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Word 31h */ +struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_31H { + /* least significant bits */ + uint8_t disableSetupMenu : 1; /* 1 means invoking setup menu with ctrl-s won't work. deblobbed_descriptor.bin says 0 (as is default, per datasheet) */ + uint8_t disableTitleMessage : 1; /* 1 means that title in boot agent screen is suppressed, as is ctrl-s message. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableProtocolSelect : 1; /* 1 means no changes to boot protocol are allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableBootSelection : 1; /* 1 means no changes in boot order option menu are allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableLegacyWakeupSupport : 1; /* 1 means no changes in legacy wakeup support menu is allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableFlashUpdate : 1; /* 1 means no changes to flash image using PROset is allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t reserved1 : 2; /* Reserved. Datasheet says these must be 0, and deblobbed_descriptor.bin sets them to 0. */ + + /* + * deblobbed_descriptor says 000 + * 000 = normal behaviour + * see datasheet (page 21) for other modes. + */ + uint8_t ibaBootOrderSetupMode : 3; + + uint8_t reserved2 : 3; /* Reserved. Datasheet says these must be set to 0, and deblobbed_descriptor.bin sets them to 0. */ + uint8_t signature : 2; /* Must be set to 01 to indicate that this whole word has been configured by the agent or other software. deblobbed_descriptor.bin says 01. */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Word 32h */ +struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_32H { + /* least significant bits */ + uint8_t buildNumber : 8; /* PXE boot agent build number. default is 28 (hex). deblobbed_descriptor.bin says 18 (hex) */ + uint8_t minorVersionNumber : 4; /* PXE boot agent minor number. default is 2 (hex). deblobbed_descriptor.bin says 3 (hex) */ + uint8_t majorVersionNumber : 4; /* PXE boot agent major number. default is F (hex). deblobbed_descriptor.bin says 1 (hex) */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Word 33h */ +struct GBE_PXE_IBA_CAPABILITIES { + /* least significant bits */ + uint8_t baseCodePresent : 1; /* 0 means PXE base code is indicated as being present. 1 (default) means not. deblobbed_descriptor.bin says 1 */ + uint8_t undiCapabilityPresent : 1; /* 1 (default) means pxe/undi capability is indicated present. 0 means not present. deblobbed_descriptor.bin says 1 */ + uint8_t reserved1 : 1; /* Reserved. Must be 1. deblobbed_descriptor.bin says 1 */ + uint8_t efiUndiCapabilityPresent : 1; /* EFI UNDI capability present: 0 (default) means not present. 1 means present. deblobbed_descriptor.bin says 0 */ + uint8_t reserved2_0 : 4; /* reserved. all bits must be 0. deblobbed_descriptor.bin sets them to 0. */ + uint8_t reserved2_1 : 6; /* ^ part of reserved2_0. split this way so that the bitfields align */ + uint8_t signature : 2; /* must be 01 to indicate that the word is configured by the agent or other software. deblobbed_descriptor.bin says 01 */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Words 30h to 3Eh */ +struct GBE_PXE_SOFTWARE_REGION { + struct GBE_PXE_BOOT_AGENT_MAIN_SETUP_OPTIONS bootAgentMainSetupOptions; /* Word 30h */ + struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_31H bootAgentConfigurationCustomizationOptions31h; /* Word 31h */ + struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_32H bootAgentConfigurationCustomizationOptions32h; /* Word 32h */ + struct GBE_PXE_IBA_CAPABILITIES ibaCapabilities; /* Word 33h */ + + /* Words 34h to 3Eh (padding). Set these to 0xFFFF (according to deblobbed_descriptor.bin) */ + uint16_t paddingWords34hTo3Eh[11]; + + /* + * the pxe software region is practically useless in libreboot, since + * libreboot does not include the intel boot agent (it's proprietary software). + * + * Having this struct in place is simply for documentations sake. It is completely + * irrelevant what you put here. filling it with 0xFFFF would probably be fine. + */ +}; + +struct GBEREGIONRECORD_4K { + uint8_t macAddress[6]; /* Word 00 to 02 */ + struct GBE_RESERVED_WORD_03H reservedWord03h; /* Reserved word 03. */ + uint16_t reservedWord04h; /* Reserved word 04: set it to 0xFFFF (according to datasheet and deblobbed_descriptor.bin) */ + uint16_t imageVersionInformation; /* Reserved word 05: 83 10 (little endian) in my deblobbed_descriptor.bin. Set this to 0x1083 (in C, assuming little endian byte order). "cannot be changed" according to datasheet */ + uint16_t reservedWords06h07h[2]; /* Reserved words 06-07: set both to 0xFFFF (according to datasheet and deblobbed_descriptor.bin) */ + + /* + * Word 08 and 09 (pba low and pba high): + * + * Both of these should be set to 0xFFFF by default, according to the datasheet. + * "nine digit printed board assembly (PBA) number" for intel cards to be stored + * in a 4 byte (read: 2 word) field. + * + * Example: if pba number is 123456-003, then word 08 should be 1234h and word 09 becomes 5603. + * Note: 1234 and 5603 above are big endian. In the image it would actually be 34 12 and 0356 + * + * Example: in mine it was (in the image): 08 10 FF FF. That becomes 1008h and FFFFh, or + * basically: 1008FF-0FF. The same was observed in another. + * + * Setting it to FF FF FF FF should be fine, according to the datasheet. + */ + uint16_t pbaLow; /* Word 08. Set it to 0x1008 (according to deblobbed_descriptor.bin). */ + uint16_t pbaHigh; /* Word 09. Set it to 0xFFFF (according to deblobbed_descriptor.bin). */ + + /* Word 0A */ + struct GBE_PCI_INITIALIZATION_CONTROL_WORD pciInitializationControlWord; + + /* + * Word 0B; subsystem ID + * + * If load subsystem ID bit of word 0A (pci init control word) is + * set to 1 (read: it is. in my deblobbed_descriptor.bin), store + * the subsystem id here. Datasheet says that the default value is + * 0000h, but you should set this to 20EEh (little endian: EE 20) + */ + uint16_t subsystemId; /* Set this to 0x20EE */ + + /* + * Word 0C; subsystem vendor ID + * + * If load subsystem vendor ID bit of word 0A (pci init control word) + * is set to 1 (read: it is. in my deblobbed_descriptor.bin), store + * the subsystem vendor id here. Datasheet says that the default + * value is 8086h, but you should set this to 17AAh (lendian: AA 17). + */ + uint16_t subsystemVendorId; /* Set this to 0x17AA */ + + /* + * Word 0D: device ID + * + * If load vendor/device ID in word 0A (pci init control word) is 1 + * (it is) then this word is used to init device id using word 21h, + * 1Eh or 1Fh. In my case, deviceId is 0x10F5. Word 21h is set to + * 0x10CB, word 1Eh is 0x10F5 and 1Fh is 0x10BF + * + * The datasheet says that 10F5 is for Intel 82567LM gigabit ethernet + * controller; 10BF is for Intel 82567LF and 10CB is for Intel 82567V. + * + * Based on this, the X200 is shown to have the Intel 82567LM ethernet + * controller. + */ + uint16_t deviceId; /* Set this to 0x10F5. */ + /* It is important that this is correct, for the linux kernel driver */ + + /* + * Word 0E: vendor ID + * + * If load vendor/device ID in word 0A (pci init control) is 1 (it is), + * then this word used read to initialize the PCI vendor ID. Default + * value is 8086 according to datasheets, and deblobbed_descriptor.bin. + * + * Intel is often 8086 as a PCI vendor ID. Because 8086. As in the CPU architecture. + */ + uint16_t vendorId; + + uint16_t deviceRevId; /* Word 0F: reserved bits. Set all bits to 0. */ + struct GBE_LAN_POWER_CONSUMPTION lanPowerConsumption; /* Word 10: LAN Power Consumption (see struct definition) */ + uint16_t reservedWords11h12h[2]; /* Words 11-12: Reserved. Set both of them to 0x0000 (according to datasheet). */ + + /* Word 13: Shared Initialization Control Word */ + struct GBE_SHARED_INITIALIZATION_CONTROL_WORD sharedInitializationControlWord; + + /* Word 14: Extended Configuration Control Word 1 */ + struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_1 extendedConfigurationControlWord1; + + /* Word 15: Extended Configuration Control Word 2 */ + struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_2 extendedConfigurationControlWord2; + + /* Word 16: Extended Configuration Control Word 3 */ + /* All bits reserved. Datasheet and deblobbed_descriptor.bin say to set it to zero */ + uint16_t extendedConfigurationControlWord3; + + struct LED_CTL_1 ledCtl1; /* Word 17: LED 1 Configuration and Power Management */ + struct LED_CTL_02 ledCtl02; /* Word 18: LED 0 and 2 Configuration Defaults */ + uint16_t reservedWord19h; /* Word 19: Reserved. Default is 0x2B00 according to datasheet, but in deblobbed_descriptor.bin it is 0x2B40 */ + uint16_t reservedWord1Ah; /* Word 1A: Reserved. Default is 0x0043 according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord1Bh; /* Word 1B: Reserved. Should be 0x0000 according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord1Ch; /* Word 1C: Reserved. Should be 0x10F5 according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord1Dh; /* Word 1D: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t _82567lmDeviceId; /* Word 1E: Device ID for Intel 82567LM gigabit ethernet controller (note: X200 uses this). Should be 0x10F5 according to datasheet and deblobbed_descriptor.bin*/ + uint16_t _82567lfDeviceId; /* Word 1F: Device ID for Intel 82567LF gigabit ethernet controller. Should be 0x10BF according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord20h; /* Word 20: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t _82567vDeviceId; /* Word 21: Device ID for Intel 82567V gigabit ethernet controller. Should be 0x10CB according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord22h; /* Word 22: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord23h; /* Word 23: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWords24to2Fh[12]; /* Words 24-2F: Reserved. These should all be 0x0000 according to datasheet and deblobbed_descriptor.bin */ + struct GBE_PXE_SOFTWARE_REGION pxeSoftwareRegion; /* Words 30-3E: PXE Software Region */ + uint16_t checkSum; /* when added to the sum of all words above, this should match GBECHECKSUMTOTAL */ + + /* set all bytes in here to 0xFF */ + uint8_t padding[3968]; +}; + +/* main and backup region in gbe */ +struct GBEREGIONRECORD_8K { + struct GBEREGIONRECORD_4K main; + struct GBEREGIONRECORD_4K backup; + /* + * Backup region: + * This is actually "main" on X200, since the real main has a bad checksum + * and other errors. You should do what you need on this one (if modifying + * lenovobios's gbe region) and then copy to main + */ +}; + +/* + * --------------------------------------------------------------------- + * Function declarations (keep gcc/make happy. check them in gbe.c) + * --------------------------------------------------------------------- + */ + +uint16_t gbeGetChecksumFrom4kBuffer(uint16_t* gbeWord, uint16_t desiredValue, int gbeRegionBase); +uint16_t gbeGetChecksumFrom4kStruct(struct GBEREGIONRECORD_4K gbeStruct4k, uint16_t desiredValue); +struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8K factoryGbeStruct8k); +int notCreatedHFileForGbeCFile(char* outFileName, char* cFileName); +int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* outFileName, char* headerFileName); +void printGbeChecksumDataFromStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* romName, char* regionName); +void printGbeChecksumDataFromStruct8k(struct GBEREGIONRECORD_8K gbeStruct8k, char* romName); + +#endif diff --git a/util/ich9deblob/src/ich9deblob.c b/util/ich9deblob/src/ich9deblob.c new file mode 100644 index 0000000..cc904d9 --- /dev/null +++ b/util/ich9deblob/src/ich9deblob.c @@ -0,0 +1,221 @@ +/* + * ich9deblob.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: disable and remove the ME from ich9m/gm45 systems in coreboot. + * + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * Copyright (C) 2014,2015 Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Initially based on proof of concept by Steve Shenton. */ +/* Original utility can be found at https://gitorious.org/ich9descriptortool */ + +/* + * Read a factory.rom dump (ich9m/gm45 systems) and + * modify the flash descriptor to remove all regions except descriptor, + * Gbe and BIOS. Set BIOS region to full size of the ROM image (after + * the flash descriptor and gbe). Basically, deblob the descriptor. + * + * This will will generate a concatenated descriptor+gbe dump suitable + * for use in libreboot. Currently tested: ThinkPad X200 (coreboot/libreboot) + */ + +/* + * See docs/hcl/x200_remove_me.html for info plus links to datasheet (also linked below) + * + * Info about flash descriptor (read page 845 onwards): + * http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datash… + * + * Info about Gbe region (read whole datasheet): + * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-… + * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-… + */ + +#include "ich9deblob.h" + +int main() +{ + struct DESCRIPTORREGIONRECORD descriptorStruct; + uint8_t* descriptorBuffer = (uint8_t*)&descriptorStruct; + + struct GBEREGIONRECORD_8K gbeStruct8k; + uint8_t* gbeBuffer8k = (uint8_t*)&gbeStruct8k; + uint32_t gbeRegionStart; + + char* romFilename = "factory.rom"; + char* descriptorGbeFilename = "deblobbed_descriptor.bin"; + char* descriptorNoGbeFilename = "deblobbed_4kdescriptor.bin"; + + unsigned int bufferLength; + unsigned int romSize; + + /* + * ------------------------------------------------------------------ + * Compatibility checks. This version of ich9deblob is not yet portable. + * ------------------------------------------------------------------ + */ + + if (systemOrCompilerIncompatible(descriptorStruct, gbeStruct8k)) return 1; + /* If true, fail with error message */ + + /* + * ------------------------------------------------------------------ + * Extract the descriptor and gbe regions from the factory.rom dump + * ------------------------------------------------------------------ + */ + FILE* fp = NULL; + fp = fopen(romFilename, "rb"); /* open factory.rom */ + if (NULL == fp) + { + printf("\nerror: could not open %s\n", romFilename); + fclose(fp); + return 1; + } + printf("\n%s opened successfully\n", romFilename); + + /* + * Get the descriptor region dump from the factory.rom + * (goes in factoryDescriptorBuffer variable) + */ + bufferLength = fread(descriptorBuffer, 1, DESCRIPTORREGIONSIZE, fp); + if (DESCRIPTORREGIONSIZE != bufferLength) // + { + printf("\nerror: could not read descriptor from %s (%i) bytes read\n", romFilename, bufferLength); + fclose(fp); + return 1; + } + printf("\ndescriptor region read successfully\n"); + + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + gbeRegionStart = descriptorStruct.regionSection.flReg3.BASE << FLREGIONBITSHIFT; + + /* + * Set offset so that we can read the data from + * the gbe region + */ + fseek(fp, gbeRegionStart, SEEK_SET); + /* Read the gbe data from the factory.rom and put it in factoryGbeBuffer8k */ + bufferLength = fread(gbeBuffer8k, 1, GBEREGIONSIZE_8K, fp); + if (GBEREGIONSIZE_8K != bufferLength) + { + printf("\nerror: could not read GBe region from %s (%i) bytes read\n", romFilename, bufferLength); + fclose(fp); + return 1; + } + printf("\ngbe (8KiB) region read successfully\n"); + } + + fseek(fp, 0L, SEEK_END); + romSize = ftell(fp); + printf("\n%s size: [%i] bytes\n", romFilename, romSize); + + fclose(fp); + + /* Debugging (before modification) */ + printDescriptorRegionLocations(descriptorStruct, "Original"); + if (descriptorDefinesGbeRegion(descriptorStruct)) + printGbeChecksumDataFromStruct8k(gbeStruct8k, "Original"); + else printf("NO GBE REGION\n"); + + /* + * ------------------------------------------------------------------ + * Modify the descriptor and gbe regions, ready to go in libreboot.rom + * ------------------------------------------------------------------ + */ + + /* Delete the ME/Platform regions, place Gbe after the descriptor, resize BIOS region to fill the gap */ + descriptorStruct = librebootDescriptorStructFromFactory(descriptorStruct, romSize); + + /* The ME is disallowed read-write access to all regions + * (this is probably redundant, since the ME firmware is already removed from libreboot) */ + descriptorStruct = descriptorMeRegionsForbidden(descriptorStruct); + /* Host/CPU is allowed to read/write all regions. + * This makes flashrom -p internal work */ + descriptorStruct = descriptorHostRegionsUnlocked(descriptorStruct); + + /* Set OEM string */ + descriptorStruct = descriptorOemString(descriptorStruct); + + /* Modify the Gbe region (see function for details) */ + if (descriptorDefinesGbeRegion(descriptorStruct)) + gbeStruct8k = deblobbedGbeStructFromFactory(gbeStruct8k); + + /* Debugging (after modifying the descriptor and gbe regions) */ + printDescriptorRegionLocations(descriptorStruct, "Modified"); + if (descriptorDefinesGbeRegion(descriptorStruct)) + printGbeChecksumDataFromStruct8k(gbeStruct8k, "Modified"); + else printf("NO GBE REGION\n"); + + /* + * ------------------------------------------------------------------ + * Create the file with the modified descriptor and gbe inside + * ------------------------------------------------------------------ + */ + printf("\n"); + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + if (notCreatedDescriptorGbeFile(descriptorStruct, gbeStruct8k, descriptorGbeFilename)) { + return 1; + } + } + else + { + if (notCreated4kDescriptorFile(descriptorStruct, descriptorNoGbeFilename)) { + return 1; + } + } + + /* + * ------------------------------------------------------------------ + * Generate ich9gen data (C code that will recreate the deblobbed descriptor+gbe from scratch) + * ------------------------------------------------------------------ + */ + /* Code for generating the Descriptor struct */ + /* mkdescriptor.h */ + if (notCreatedHFileForDescriptorCFile("mkdescriptor.h", "mkdescriptor.c")) { + return 1; + } /* and now mkdescriptor.c */ + if (notCreatedCFileFromDescriptorStruct(descriptorStruct, "mkdescriptor.c", "mkdescriptor.h")) { + return 1; + } + + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + /* Code for generating the Gbe struct */ + /* mkgbe.h */ + if (notCreatedHFileForGbeCFile("mkgbe.h", "mkgbe.c")) { + return 1; + } /* and now mkgbe.c */ + if (notCreatedCFileFromGbeStruct4k(gbeStruct8k.backup, "mkgbe.c", "mkgbe.h")) { + return 1; + } + } + + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + printf("The modified descriptor and gbe regions have also been dumped as src files: mkdescriptor.c, mkdescriptor.h, mkgbe.c, mkgbe.h\n"); + printf("To use these in ich9gen, place them in src/ich9gen/ and re-build ich9gen.\n\n"); + } + else + { + printf("The modified descriptor region have also been dumped as src files: mkdescriptor.c, mkdescriptor.h\n"); + printf("To use these in ich9gen, place them in src/ich9gen/ and re-build ich9gen.\n\n"); + } + + return 0; +} diff --git a/util/ich9deblob/src/ich9deblob.h b/util/ich9deblob/src/ich9deblob.h new file mode 100644 index 0000000..c11ea29 --- /dev/null +++ b/util/ich9deblob/src/ich9deblob.h @@ -0,0 +1,38 @@ +/* + * ich9deblob.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: header file for ich9deblob.c + * + * Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> + * Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef ICH9DEBLOB_H +#define ICH9DEBLOB_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> + +#include "common/descriptor_gbe.h" /* common descriptor/gbe functions used by ich9deblob */ +#include "common/x86compatibility.h" /* system/compiler compatibility checks. This code is not portable. */ +#include "descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "gbe/gbe.h" /* structs describing what's in the gbe region */ + +int main(); + +#endif diff --git a/util/ich9deblob/src/ich9gen.c b/util/ich9deblob/src/ich9gen.c new file mode 100644 index 0000000..b3a2c9f --- /dev/null +++ b/util/ich9deblob/src/ich9gen.c @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> + * Copyright (C) 2016 Swift Geek <swiftgeek(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Generate deblobbed descriptor and gbe 12KiB file from scratch + * without relying on a factory.rom dump */ + +#include "ich9gen.h" + +int main(int argc, char *argv[]) +{ + int i, j; + + struct GBEREGIONRECORD_8K gbeStruct8k = generatedGbeStruct8k(); + struct DESCRIPTORREGIONRECORD descriptorStruct4M = generatedDescriptorStruct(ROMSIZE_4MB, WITHGBE); + struct DESCRIPTORREGIONRECORD descriptorStruct8M = generatedDescriptorStruct(ROMSIZE_8MB, WITHGBE); + struct DESCRIPTORREGIONRECORD descriptorStruct16M = generatedDescriptorStruct(ROMSIZE_16MB, WITHGBE); + struct DESCRIPTORREGIONRECORD descriptorStructNoGbe4M = generatedDescriptorStruct(ROMSIZE_4MB, WITHOUTGBE); + struct DESCRIPTORREGIONRECORD descriptorStructNoGbe8M = generatedDescriptorStruct(ROMSIZE_8MB, WITHOUTGBE); + struct DESCRIPTORREGIONRECORD descriptorStructNoGbe16M = generatedDescriptorStruct(ROMSIZE_16MB, WITHOUTGBE); + + /* Only for the compatibility checks */ + struct DESCRIPTORREGIONRECORD dummyDescriptorStruct; + struct GBEREGIONRECORD_8K dummyGbeStruct8k; + + /* + * ------------------------------------------------------------------ + * Compatibility checks. This version of ich9deblob is not yet portable. + * ------------------------------------------------------------------ + */ + + if (systemOrCompilerIncompatible(dummyDescriptorStruct, dummyGbeStruct8k)) return 1; + /* If true, fail with error message */ + + /* + * ------------------------------------------------------------------ + * Arguments given on the terminal + * ------------------------------------------------------------------ + */ + + + if(argc==3) { + + /* If user provides their own MAC address, it will be used. + * Otherwise, ich9gen will simply use the default one. + * + * However, if the user provides an invalid MAC address, then ich9gen + * will exit. */ + if(0==strcmp(argv[1],"--macaddress")) { + /* 6 hex chars format (example): AA:BB:CC:DD:EE:FF */ + if (strlen(argv[2]) != 17) { + printf("ich9gen: invalid mac address format (wrong length)\n"); + return 1; + } + for(i=2; i<14; i+=3) { + if(argv[2][i]!=':') { + printf("ich9gen: invalid mac address format (non-colon characters used as spacing)\n"); + return 1; + } + } + for(i=0; i<6; i++) { + gbeStruct8k.main.macAddress[i] = 0; + + /* Go through each nibble of the byte */ + for(j=0; j<2; j++) { + if(argv[2][(i*3)+j]>='a' && argv[2][(i*3)+j]<='f') + gbeStruct8k.main.macAddress[i] |= (uint8_t)((argv[2][(i*3)+j] - 87) << ((j^1) << 2)); + else if(argv[2][(i*3)+j]>='A' && argv[2][(i*3)+j]<='F') + gbeStruct8k.main.macAddress[i] |= (uint8_t)((argv[2][(i*3)+j] - 55) << ((j^1) << 2)); + else if(argv[2][(i*3)+j]>='0' && argv[2][(i*3)+j]<='9') + gbeStruct8k.main.macAddress[i] |= (uint8_t)((argv[2][(i*3)+j] - 48) << ((j^1) << 2)); + else { + printf("ich9gen: invalid mac address format (non-hex characters)\n"); + return 1; + } + } + } + + gbeStruct8k.main.checkSum = gbeGetChecksumFrom4kStruct(gbeStruct8k.main, GBECHECKSUMTOTAL); /* Fix the checksum */ + memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K); /* Copy to the backup */ + + /* Generate ich9gen data (C code for Gbe region): */ + + /* mkgbe.h */ + if (notCreatedHFileForGbeCFile("mkgbe.h", "mkgbe.c")) { + return 1; + } /* and now mkgbe.c */ + if (notCreatedCFileFromGbeStruct4k(gbeStruct8k.backup, "mkgbe.c", "mkgbe.h")) { + return 1; + } + + printf("You selected to change the MAC address in the Gbe section. This has been done.\n\n"); + + printf("The modified gbe region has also been dumped as src files: mkgbe.c, mkgbe.h\n"); + printf("To use these in ich9gen, place them in src/ich9gen/ and re-build ich9gen.\n\n"); + } + + } + + /* + * ------------------------------------------------------------------ + * Generate the 12KiB files, ready to be used in a libreboot image + * ------------------------------------------------------------------ + */ + + if (notCreatedDescriptorGbeFile(descriptorStruct4M, gbeStruct8k, "ich9fdgbe_4m.bin")) { + return 1; + } + + if (notCreatedDescriptorGbeFile(descriptorStruct8M, gbeStruct8k, "ich9fdgbe_8m.bin")) { + return 1; + } + + if (notCreatedDescriptorGbeFile(descriptorStruct16M, gbeStruct8k, "ich9fdgbe_16m.bin")) { + return 1; + } + /* + * ------------------------------------------------------------------ + * Generate the 4KiB files (descriptors without GbE), ready to be used in a libreboot image + * In these descriptors, the onboard Intel GbE NIC is disabled; a discrete one is used instead + * ------------------------------------------------------------------ + */ + + if (notCreated4kDescriptorFile(descriptorStructNoGbe4M, "ich9fdnogbe_4m.bin")) { + return 1; + } + + if (notCreated4kDescriptorFile(descriptorStructNoGbe8M, "ich9fdnogbe_8m.bin")) { + return 1; + } + + if (notCreated4kDescriptorFile(descriptorStructNoGbe16M, "ich9fdnogbe_16m.bin")) { + return 1; + } + return 0; +} diff --git a/util/ich9deblob/src/ich9gen.h b/util/ich9deblob/src/ich9gen.h new file mode 100644 index 0000000..6b346b0 --- /dev/null +++ b/util/ich9deblob/src/ich9gen.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Header file for ich9gen.c */ + +#ifndef ICH9GEN_H +#define ICH9GEN_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> + +#include "ich9gen/mkdescriptor.h" +#include "ich9gen/mkgbe.h" +#include "common/descriptor_gbe.h" /* common descriptor/gbe functions used by ich9deblob */ +#include "common/x86compatibility.h" /* system/compiler compatibility checks. This code is not portable. */ +#include "descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "gbe/gbe.h" /* structs describing what's in the gbe region */ + +#define WITHGBE 1 +#define WITHOUTGBE 0 + +int main(int argc, char *argv[]); + +#endif diff --git a/util/ich9deblob/src/ich9gen/mkdescriptor.c b/util/ich9deblob/src/ich9gen/mkdescriptor.c new file mode 100644 index 0000000..3b97a97 --- /dev/null +++ b/util/ich9deblob/src/ich9gen/mkdescriptor.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "mkdescriptor.h" + +/* Generate a 4KiB Descriptor struct, with default values. */ +/* Read ../descriptor/descriptor.h for an explanation of the default values used here */ + +struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe) +{ + int i; + struct DESCRIPTORREGIONRECORD descriptorStruct; + + /* Flash Valid Signature Register */ + descriptorStruct.flValSig.signature = 0x0ff0a55a; + + /* Flash Map Registers */ + /* FLMAP0 */ + descriptorStruct.flMaps.flMap0.FCBA = 0x01; + descriptorStruct.flMaps.flMap0.NC = 0x0; + descriptorStruct.flMaps.flMap0.reserved1 = 0x00; + descriptorStruct.flMaps.flMap0.FRBA = 0x04; + descriptorStruct.flMaps.flMap0.NR = hasGbe ? 0x2 : 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.flMaps.flMap0.reserved2 = 0x00; + /* FLMAP1 */ + descriptorStruct.flMaps.flMap1.FMBA = 0x06; + descriptorStruct.flMaps.flMap1.NM = 0x2; + descriptorStruct.flMaps.flMap1.reserved = 0x00; + descriptorStruct.flMaps.flMap1.FISBA = 0x10; + descriptorStruct.flMaps.flMap1.ISL = 0x02; + /* FLMAP2 */ + descriptorStruct.flMaps.flMap2.FMSBA = 0x20; + descriptorStruct.flMaps.flMap2.MSL = 0x01; + descriptorStruct.flMaps.flMap2.reserved = 0x0000; + + /* Component Section Record */ + /* FLCOMP */ + descriptorStruct.componentSection.flcomp.component1Density = componentDensity(romSize); + descriptorStruct.componentSection.flcomp.component2Density = componentDensity(romSize); + descriptorStruct.componentSection.flcomp.reserved1 = 0x0; + descriptorStruct.componentSection.flcomp.reserved2 = 0x00; + descriptorStruct.componentSection.flcomp.reserved3 = 0x0; + descriptorStruct.componentSection.flcomp.readClockFrequency = 0x0; + descriptorStruct.componentSection.flcomp.fastReadSupport = 0x1; + descriptorStruct.componentSection.flcomp.fastreadClockFrequency = 0x1; + descriptorStruct.componentSection.flcomp.writeEraseClockFrequency = 0x0; + descriptorStruct.componentSection.flcomp.readStatusClockFrequency = 0x0; + descriptorStruct.componentSection.flcomp.reserved4 = 0x0; + /* FLILL */ + descriptorStruct.componentSection.flill = 0x00000000; + /* FLPB */ + descriptorStruct.componentSection.flpb = 0x00000000; + /* Padding */ + for (i = 0; i < 36; i++) { + descriptorStruct.componentSection.padding[i] = 0xFF; + } + + /* Flash Descriptor Region Section */ + /* FLREG0 (Descriptor) */ + descriptorStruct.regionSection.flReg0.BASE = 0x0000; + descriptorStruct.regionSection.flReg0.reserved1 = 0x0; + descriptorStruct.regionSection.flReg0.LIMIT = 0x0000; + descriptorStruct.regionSection.flReg0.reserved2 = 0x0; + /* FLREG1 (BIOS) */ + descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + (hasGbe ? GBEREGIONSIZE_8K : 0)) >> FLREGIONBITSHIFT; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg1.reserved1 = 0x0; + descriptorStruct.regionSection.flReg1.LIMIT = ((romSize >> FLREGIONBITSHIFT) - 1); /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg1.reserved2 = 0x0; + /* FLREG2 (ME) */ + descriptorStruct.regionSection.flReg2.BASE = 0x1fff; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg2.reserved1 = 0x0; + descriptorStruct.regionSection.flReg2.LIMIT = 0x0000; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg2.reserved2 = 0x0; + /* FLREG3 (Gbe) */ + descriptorStruct.regionSection.flReg3.BASE = hasGbe ? (DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT) : 0x1fff; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg3.reserved1 = 0x0; + descriptorStruct.regionSection.flReg3.LIMIT = hasGbe ? (GBEREGIONSIZE_8K >> FLREGIONBITSHIFT) : 0x0000; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg3.reserved2 = 0x0; + /* FLREG4 (Platform) */ + descriptorStruct.regionSection.flReg4.BASE = 0x1fff; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg4.reserved1 = 0x0; + descriptorStruct.regionSection.flReg4.LIMIT = 0x0000; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg4.reserved2 = 0x0; + /* Padding */ + for (i = 0; i < 12; i++) { + descriptorStruct.regionSection.padding[i] = 0xFF; + } + + /* Master Access Section */ + /* FLMSTR1 (Host CPU / BIOS) */ + descriptorStruct.masterAccessSection.flMstr1.requesterId = 0x0000; + descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.reserved1 = 0x0; + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.reserved2 = 0x0; + /* FLMSTR2 (ME) */ + descriptorStruct.masterAccessSection.flMstr2.requesterId = 0x0000; + descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.reserved1 = 0x0; + descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.reserved2 = 0x0; + /* FLMSTR3 (Gbe) */ + descriptorStruct.masterAccessSection.flMstr3.requesterId = 0x0218; + descriptorStruct.masterAccessSection.flMstr3.fdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.biosRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.meRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.gbeRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr3.pdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.reserved1 = 0x0; + descriptorStruct.masterAccessSection.flMstr3.fdRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.biosRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.meRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.gbeRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr3.pdRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.reserved2 = 0x0; + /* Padding */ + for (i = 0; i < 148; i++) { + descriptorStruct.masterAccessSection.padding[i] = 0xFF; + } + + /* ICH straps */ + /* ICHSTRAP0 */ + descriptorStruct.ichStraps.ichStrap0.meDisable = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.ichStraps.ichStrap0.reserved1 = 0x04; + descriptorStruct.ichStraps.ichStrap0.tcoMode = 0x1; + descriptorStruct.ichStraps.ichStrap0.smBusAddress = 0x64; + descriptorStruct.ichStraps.ichStrap0.bmcMode = 0x0; + descriptorStruct.ichStraps.ichStrap0.tripPointSelect = 0x0; + descriptorStruct.ichStraps.ichStrap0.reserved2 = 0x0; + descriptorStruct.ichStraps.ichStrap0.integratedGbe = hasGbe ? 0x1 : 0x0; + descriptorStruct.ichStraps.ichStrap0.lanPhy = hasGbe ? 0x1 : 0x0; + descriptorStruct.ichStraps.ichStrap0.reserved3 = 0x0; + descriptorStruct.ichStraps.ichStrap0.dmiRequesterId = 0x0; + descriptorStruct.ichStraps.ichStrap0.smBus2Address = 0x00; + /* ICHSTRAP1 */ + descriptorStruct.ichStraps.ichStrap1.northMlink = 0x1; + descriptorStruct.ichStraps.ichStrap1.southMlink = 0x1; + descriptorStruct.ichStraps.ichStrap1.meSmbus = 0x1; + descriptorStruct.ichStraps.ichStrap1.sstDynamic = 0x1; + descriptorStruct.ichStraps.ichStrap1.reserved1 = 0x0; + descriptorStruct.ichStraps.ichStrap1.northMlink2 = 0x1; + descriptorStruct.ichStraps.ichStrap1.reserved2 = 0x00; + descriptorStruct.ichStraps.ichStrap1.reserved3 = 0x0000; + /* Padding */ + for (i = 0; i < 248; i++) { + descriptorStruct.ichStraps.padding[i] = 0xFF; + } + + /* MCH straps */ + /* MCHSTRAP0 */ + descriptorStruct.mchStraps.mchStrap0.meDisable = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.mchStraps.mchStrap0.meBootFromFlash = 0x0; + descriptorStruct.mchStraps.mchStrap0.tpmDisable = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.mchStraps.mchStrap0.reserved1 = 0x7; + descriptorStruct.mchStraps.mchStrap0.spiFingerprint = 0x1; + descriptorStruct.mchStraps.mchStrap0.meAlternateDisable = 0x0; + descriptorStruct.mchStraps.mchStrap0.reserved2 = 0xff; + descriptorStruct.mchStraps.mchStrap0.reserved3 = 0xffff; + /* Padding */ + for (i = 0; i < 3292; i++) { + descriptorStruct.mchStraps.padding[i] = 0xFF; + } + + /* ME VSCC Table */ + descriptorStruct.meVsccTable.jid0 = 0x001720c2; + descriptorStruct.meVsccTable.vscc0 = 0x20052005; + descriptorStruct.meVsccTable.jid1 = 0x001730ef; + descriptorStruct.meVsccTable.vscc1 = 0x20052005; + descriptorStruct.meVsccTable.jid2 = 0x0000481f; + descriptorStruct.meVsccTable.vscc2 = 0x20152015; + /* Padding */ + for (i = 0; i < 4; i++) { + descriptorStruct.meVsccTable.padding[i] = 0xFF; + } + + /* Descriptor Map 2 Record */ + descriptorStruct.descriptor2Map.meVsccTableBaseAddress = 0xee; + descriptorStruct.descriptor2Map.meVsccTableLength = 0x06; + descriptorStruct.descriptor2Map.reserved = 0x0000; + + /* OEM section */ + /* see ../descriptor/descriptor.c */ + /* Magic String (ascii characters) */ + descriptorStruct.oemSection.magicString[0] = 0x4c; + descriptorStruct.oemSection.magicString[1] = 0x49; + descriptorStruct.oemSection.magicString[2] = 0x42; + descriptorStruct.oemSection.magicString[3] = 0x45; + descriptorStruct.oemSection.magicString[4] = 0x52; + descriptorStruct.oemSection.magicString[5] = 0x41; + descriptorStruct.oemSection.magicString[6] = 0x54; + descriptorStruct.oemSection.magicString[7] = 0x45; + /* Padding */ + for (i = 0; i < 248; i++) { + descriptorStruct.oemSection.padding[i] = 0xFF; + } + + return descriptorStruct; +} + diff --git a/util/ich9deblob/src/ich9gen/mkdescriptor.h b/util/ich9deblob/src/ich9gen/mkdescriptor.h new file mode 100644 index 0000000..8663db8 --- /dev/null +++ b/util/ich9deblob/src/ich9gen/mkdescriptor.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef ICH9GEN_MKDESCRIPTOR_H +#define ICH9GEN_MKDESCRIPTOR_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> +#include "../descriptor/descriptor.h" + +struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe); +#endif diff --git a/util/ich9deblob/src/ich9gen/mkgbe.c b/util/ich9deblob/src/ich9gen/mkgbe.c new file mode 100644 index 0000000..bebe1ce --- /dev/null +++ b/util/ich9deblob/src/ich9gen/mkgbe.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2014 Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "mkgbe.h" + +/* Generate a 4KiB Gbe struct, with default values. */ +/* Read ../gbe/gbe.h for an explanation of the default values used here */ + +struct GBEREGIONRECORD_4K generatedGbeStruct4k() +{ + int i; + struct GBEREGIONRECORD_4K gbeStruct4k; + + /* MAC address (words 00h to 02h) */ + /* see ../gbe/gbe.c */ + gbeStruct4k.macAddress[0] = 0x00; + gbeStruct4k.macAddress[1] = 0xf5; + gbeStruct4k.macAddress[2] = 0xf0; + gbeStruct4k.macAddress[3] = 0x40; + gbeStruct4k.macAddress[4] = 0x71; + gbeStruct4k.macAddress[5] = 0xfe; + + /* Word 03h (Reserved) */ + gbeStruct4k.reservedWord03h.reserved1_0 = 0x00; + gbeStruct4k.reservedWord03h.reserved1_1 = 0x0; + gbeStruct4k.reservedWord03h.ibaLom = 0x1; + gbeStruct4k.reservedWord03h.reserved2 = 0x0; + + /* Word 04h (Reserved) */ + gbeStruct4k.reservedWord04h = 0xffff; + + /* Word 05h (Image Version Information) */ + gbeStruct4k.imageVersionInformation = 0x1083; + + /* Words 06h and 07h (Reserved) */ + gbeStruct4k.reservedWords06h07h[0] = 0xffff; + gbeStruct4k.reservedWords06h07h[1] = 0xffff; + + /* Word 08h and 09h (PBA Low and PBA High) */ + gbeStruct4k.pbaLow = 0x1008; + gbeStruct4k.pbaHigh = 0xffff; + + /* Word 0Ah (PCI Initialization Control Word) */ + gbeStruct4k.pciInitializationControlWord.loadVendorDeviceId = 0x1; + gbeStruct4k.pciInitializationControlWord.loadSubsystemId = 0x1; + gbeStruct4k.pciInitializationControlWord.reserved1 = 0x0; + gbeStruct4k.pciInitializationControlWord.reserved2 = 0x0; + gbeStruct4k.pciInitializationControlWord.pmEnable = 0x1; + gbeStruct4k.pciInitializationControlWord.auxPwr = 0x1; + gbeStruct4k.pciInitializationControlWord.reserved3 = 0x0; + gbeStruct4k.pciInitializationControlWord.reserved4 = 0x1; + + /* Word 0Bh (Subsystem ID) */ + gbeStruct4k.subsystemId = 0x20ee; + + /* Word 0Ch (Subsystem Vendor ID) */ + gbeStruct4k.subsystemVendorId = 0x17aa; + + /* Word 0Dh (Device ID) */ + gbeStruct4k.deviceId = 0x10f5; + + /* Word 0Eh (Vendor ID) */ + gbeStruct4k.vendorId = 0x8086; + + /* Word 0Fh (Device Revision ID) */ + gbeStruct4k.deviceRevId = 0x0000; + + /* Word 10h (LAN Power Consumption) */ + gbeStruct4k.lanPowerConsumption.lanD3Power = 0x01; + gbeStruct4k.lanPowerConsumption.reserved = 0x0; + gbeStruct4k.lanPowerConsumption.lanD0Power = 0x0d; + + /* Words 11h and 12h (Reserved) */ + gbeStruct4k.reservedWords11h12h[0] = 0x0000; + gbeStruct4k.reservedWords11h12h[1] = 0x0000; + + /* Word 13h (Shared Initialization Control Word) */ + gbeStruct4k.sharedInitializationControlWord.reserved1 = 0x5; + gbeStruct4k.sharedInitializationControlWord.forceDuplex = 0x0; + gbeStruct4k.sharedInitializationControlWord.forceSpeedEnable = 0x0; + gbeStruct4k.sharedInitializationControlWord.reserved2_0 = 0x0; + gbeStruct4k.sharedInitializationControlWord.reserved2_1 = 0x0; + gbeStruct4k.sharedInitializationControlWord.phyPowerDownEnable = 0x1; + gbeStruct4k.sharedInitializationControlWord.reserved3 = 0x1; + gbeStruct4k.sharedInitializationControlWord.reserved4 = 0x0; + gbeStruct4k.sharedInitializationControlWord.sign = 0x2; + + /* Word 14h (Extended Configuration Control Word 1) */ + gbeStruct4k.extendedConfigurationControlWord1.extendedConfigurationPointer = 0x020; + gbeStruct4k.extendedConfigurationControlWord1.oemWriteEnable = 0x1; + gbeStruct4k.extendedConfigurationControlWord1.reserved1 = 0x1; + gbeStruct4k.extendedConfigurationControlWord1.reserved2 = 0x0; + gbeStruct4k.extendedConfigurationControlWord1.reserved3 = 0x0; + + /* Word 15h (Extended Configuration Control Word 2) */ + gbeStruct4k.extendedConfigurationControlWord2.reserved = 0x00; + gbeStruct4k.extendedConfigurationControlWord2.extendedPhyLength = 0x0a; + + /* Word 16h (Extended Configuration Control Word 3) */ + gbeStruct4k.extendedConfigurationControlWord3 = 0x0000; + + /* Word 17h (LED 1 Configuration and Power Management) */ + gbeStruct4k.ledCtl1.led1Mode = 0xb; + gbeStruct4k.ledCtl1.reserved1 = 0x0; + gbeStruct4k.ledCtl1.led1BlinkMode = 0x0; + gbeStruct4k.ledCtl1.led1Invert = 0x0; + gbeStruct4k.ledCtl1.led1Blink = 0x1; + gbeStruct4k.ledCtl1.reserved2 = 0x1; + gbeStruct4k.ledCtl1.lpluEnable = 0x0; + gbeStruct4k.ledCtl1.lpluEnableNonD0a = 0x1; + gbeStruct4k.ledCtl1.gbeDisableNonD0a = 0x1; + gbeStruct4k.ledCtl1.reserved3 = 0x0; + gbeStruct4k.ledCtl1.gbeDisable = 0x0; + gbeStruct4k.ledCtl1.reserved4 = 0x1; + + /* Word 18h (LED 0 and 2 Configuration Defaults) */ + gbeStruct4k.ledCtl02.led0Mode = 0x2; + gbeStruct4k.ledCtl02.reserved1 = 0x0; + gbeStruct4k.ledCtl02.led0BlinkMode = 0x0; + gbeStruct4k.ledCtl02.led0Invert = 0x0; + gbeStruct4k.ledCtl02.led0Blink = 0x0; + gbeStruct4k.ledCtl02.led2Mode = 0x6; + gbeStruct4k.ledCtl02.reserved2 = 0x0; + gbeStruct4k.ledCtl02.led2BlinkMode = 0x0; + gbeStruct4k.ledCtl02.led2Invert = 0x0; + gbeStruct4k.ledCtl02.led2Blink = 0x0; + + /* Word 19h (Reserved) */ + gbeStruct4k.reservedWord19h = 0x2b40; + + /* Word 1Ah (Reserved) */ + gbeStruct4k.reservedWord1Ah = 0x0043; + + /* Word 1Bh (Reserved) */ + gbeStruct4k.reservedWord1Bh = 0x0000; + + /* Word 1Ch (Reserved) */ + gbeStruct4k.reservedWord1Ch = 0x10f5; + + /* Word 1Dh (Reserved) */ + gbeStruct4k.reservedWord1Dh = 0xbaad; + + /* Word 1Eh (Device ID for Intel 82567LM gigabit ethernet controller) */ + gbeStruct4k._82567lmDeviceId = 0x10f5; + + /* Word 1Fh (Device ID for Intel 82567LF gigabit ethernet controller) */ + gbeStruct4k._82567lfDeviceId = 0x10bf; + + /* Word 20h (Reserved) */ + gbeStruct4k.reservedWord20h = 0xbaad; + + /* Word 21h (Device ID for Intel 82567V gigabit ethernet controller) */ + gbeStruct4k._82567vDeviceId = 0x10cb; + + /* Word 22h (Reserved) */ + gbeStruct4k.reservedWord22h = 0xbaad; + + /* Word 23h (Reserved) */ + gbeStruct4k.reservedWord23h = 0xbaad; + + /* Words 24h to 2Fh (Reserved) */ + gbeStruct4k.reservedWords24to2Fh[0] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[1] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[2] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[3] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[4] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[5] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[6] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[7] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[8] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[9] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[10] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[11] = 0x0000; + + /* Words 30h to 3Eh (PXE Software Region) */ + /* Boot Agent Main Setup Options (Word 30h) */ + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.protocolSelect = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved1 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.defaultBootSelection = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved2 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.promptTime = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.displaySetupMessage = 0x1; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved3 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceSpeed = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceFullDuplex = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved4 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.efiPresence = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.pxePresence = 0x0; + /* Boot Agent Configuration Customization Options (Word 31h) */ + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableSetupMenu = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableTitleMessage = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableProtocolSelect = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableBootSelection = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableLegacyWakeupSupport = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableFlashUpdate = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved1 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.ibaBootOrderSetupMode = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved2 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.signature = 0x1; + /* Boot Agent Configuration Customization Options (Word 32h) */ + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber = 0x18; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.minorVersionNumber = 0x3; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.majorVersionNumber = 0x1; + /* IBA Capabilities (Word 33h) */ + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.baseCodePresent = 0x1; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.undiCapabilityPresent = 0x1; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved1 = 0x1; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.efiUndiCapabilityPresent = 0x0; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_0 = 0x0; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_1 = 0x00; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.signature = 0x1; + /* Padding (Words 34h to 3Eh) */ + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[0] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[1] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[2] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[3] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[4] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[5] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[6] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[7] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[8] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[9] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[10] = 0xffff; + + /* Word 3Fh (Checksum) */ + gbeStruct4k.checkSum = 0x348a; + + /* The rest of Gbe (word 40h or byte 80h onwards) is just padding (0xFF) */ + for (i = 0; i < 3968; i++) { + gbeStruct4k.padding[i] = 0xFF; + } + + return gbeStruct4k; +} + +struct GBEREGIONRECORD_8K generatedGbeStruct8k() +{ + struct GBEREGIONRECORD_8K gbeStruct8k; + gbeStruct8k.main = generatedGbeStruct4k(); + memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K); + return gbeStruct8k; +} + diff --git a/util/ich9deblob/src/ich9gen/mkgbe.h b/util/ich9deblob/src/ich9gen/mkgbe.h new file mode 100644 index 0000000..1697417 --- /dev/null +++ b/util/ich9deblob/src/ich9gen/mkgbe.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 Leah Rowe <info(a)minifree.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef ICH9GEN_MKGBE_H +#define ICH9GEN_MKGBE_H + +#include <stdio.h> +#include <string.h> +#include <stdint.h> +#include "../gbe/gbe.h" + +struct GBEREGIONRECORD_4K generatedGbeStruct4k(); +struct GBEREGIONRECORD_8K generatedGbeStruct8k(); + +#endif

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Patch merged into coreboot/master: soc/intel/apollolake: Enable write-protect SPI flash range support
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit ffb3a2d22506a86e205a757029f60abccfef0486 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 24 15:28:23 2016 -0700 soc/intel/apollolake: Enable write-protect SPI flash range support Use intel common infrastructure to enable support for write-protecting SPI flash range. Also, enable this protection for RW_MRC_CACHE. BUG=chrome-os-partner:58896 TEST=Verified that write to RW_MRC_CACHE fails in OS using "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin" Change-Id: I35df12bc295d141e314ec2cb092d904842432394 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17117 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17117 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Use intel common support to write-protect SPI flash
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit 723a84e2920c8ba52257cf4bf445b23ff01d8754 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 24 15:27:21 2016 -0700 soc/intel/skylake: Use intel common support to write-protect SPI flash BUG=chrome-os-partner:58896 Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17116 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17116 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/common: Enable support to write protect SPI flash range
by gerrit＠coreboot.org 26 Oct '16

26 Oct '16

the following patch was just integrated into master: commit aedbfc8f0917b332e648fe6c4333567bd8e58b0d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 24 15:23:40 2016 -0700 soc/intel/common: Enable support to write protect SPI flash range Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17115 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17115 for details. -gerrit

1 0

Patch merged into coreboot/master: riscv: add the lowrisc System On Chip support
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 5817a1555754709da92cae7f254d540e2b488cec Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Oct 24 16:27:19 2016 -0700 riscv: add the lowrisc System On Chip support Change-Id: I8d81b9cf280e724c935106c8f00692300094ad3f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://review.coreboot.org/17119 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> See https://review.coreboot.org/17119 for details. -gerrit

1 0

Patch set updated for coreboot: mainboard/google/reef: clarify memory part number details
by Aaron Durbin 25 Oct '16

25 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17129 -gerrit commit 5bc4e79510feb8769f4737463de35f77c63772c1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 25 15:16:26 2016 -0500 mainboard/google/reef: clarify memory part number details Explain the reasoning for the part_num strings used in the memory SKU table explaining the necessity of keeping mosys in sync with the strings used. It's possible that actual part numbers could change as the higher speed material gets cheaper, for example. BUG=chrome-os-partner:58966 Change-Id: If895e52791dc56e283261b3438106116b8b2ea05 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/memory.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index c4667f3..23cb631 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -62,9 +62,15 @@ const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { }, }; +/* + * The strings in the part_num field aren't necessarily the exact part + * numbers used in all the designs. The reason is that the mosys userland + * tool uses these strings for dumping more information. Different speed bins + * could change in future systems, but the strings still need to match. + */ static const struct lpddr4_sku skus[] = { /* - * K4F6E304HB-MGCJ - both logical channels While the parts + * K4F6E304HB-MG - both logical channels While the parts * are listed at 16Gb there are 2 ranks per channel so indicate * the deneisty as 8Gb per rank. */ @@ -76,7 +82,7 @@ static const struct lpddr4_sku skus[] = { .ch1_dual_rank = 1, .part_num = "K4F6E304HB-MGCJ", }, - /* K4F8E304HB-MGCJ - both logical channels */ + /* K4F8E304HB-MG - both logical channels */ [1] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, @@ -84,7 +90,7 @@ static const struct lpddr4_sku skus[] = { .part_num = "K4F8E304HB-MGCJ", }, /* - * MT53B512M32D2NP-062WT:C - both logical channels. While the parts + * MT53B512M32D2NP - both logical channels. While the parts * are listed at 16Gb there are 2 ranks per channel so indicate * the deneisty as 8Gb per rank. */ @@ -97,7 +103,7 @@ static const struct lpddr4_sku skus[] = { .part_num = "MT53B512M32D2NP", .disable_periodic_retraining = 1, }, - /* MT53B256M32D1NP-062 WT:C - both logical channels */ + /* MT53B256M32D1NP - both logical channels */ [3] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY, @@ -106,7 +112,7 @@ static const struct lpddr4_sku skus[] = { .disable_periodic_retraining = 1, }, /* - * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * H9HCNNNBPUMLHR - both logical channels. While the parts * are listed at 16Gb there are 2 ranks per channel so indicate the * density as 8Gb per rank. */ @@ -118,7 +124,7 @@ static const struct lpddr4_sku skus[] = { .ch1_dual_rank = 1, .part_num = "H9HCNNNBPUMLHR", }, - /* H9HCNNN8KUMLHR-NLE - both logical channels */ + /* H9HCNNN8KUMLHR - both logical channels */ [5] = { .speed = LP4_SPEED_2400, .ch0_rank_density = LP4_8Gb_DENSITY,

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Patch set updated for coreboot: mainboard/google/reef: drop disabling periodic training for micron
by Aaron Durbin 25 Oct '16

25 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17130 -gerrit commit e04d16fe1c89fbc47866fcc3a80c26e48da8e52d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 25 15:19:54 2016 -0500 mainboard/google/reef: drop disabling periodic training for micron In anticipation of getting fixed material remove the disabling of periodic training for MT53B512M32D2NP and MT53B256M32D1NP. BUG=chrome-os-partner:59003 Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/memory.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index 23cb631..50e93c7 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -101,7 +101,6 @@ static const struct lpddr4_sku skus[] = { .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "MT53B512M32D2NP", - .disable_periodic_retraining = 1, }, /* MT53B256M32D1NP - both logical channels */ [3] = { @@ -109,7 +108,6 @@ static const struct lpddr4_sku skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", - .disable_periodic_retraining = 1, }, /* * H9HCNNNBPUMLHR - both logical channels. While the parts

1 0

New patch to review for coreboot: mainboard/google/reef: drop disabling periodic training for micron
by Aaron Durbin 25 Oct '16

25 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17130 -gerrit commit 8cd58a9de074ef2a2f369190c5e78c2cb05ad866 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 25 15:19:54 2016 -0500 mainboard/google/reef: drop disabling periodic training for micron In anticipation of getting fixed material remove the disabling of periodic training for MT53B512M32D2NP and MT53B256M32D1NP. BUG=chrome-os-partner:59003 Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/memory.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index ab39a21..bf69313 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -101,7 +101,6 @@ static const struct lpddr4_sku skus[] = { .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "MT53B512M32D2NP", - .disable_periodic_retraining = 1, }, /* MT53B256M32D1NP - both logical channels */ [3] = { @@ -109,7 +108,6 @@ static const struct lpddr4_sku skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", - .disable_periodic_retraining = 1, }, /* * H9HCNNNBPUMLHR - both logical channels. While the parts

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coreboot-gerrit October 2016