coreboot-gerrit October 2016

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New patch to review for coreboot: northbridge/amd: Update all names and IDs for 00670F00
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17143 -gerrit commit 20f25d0dad1d858fa5e8f0283125ecafb3ea4d5e Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:30:17 2016 -0600 northbridge/amd: Update all names and IDs for 00670F00 Modify the new Stoney support files to match the APU's IDs and codename. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit de626730758def76e558294762a06d8ec9950cb9) Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/Kconfig | 8 ++++---- src/northbridge/amd/pi/00670F00/chip.h | 6 +++--- src/northbridge/amd/pi/00670F00/dimmSpd.c | 2 +- src/northbridge/amd/pi/00670F00/northbridge.c | 10 +++++----- src/northbridge/amd/pi/Kconfig | 1 + src/northbridge/amd/pi/Makefile.inc | 1 + 6 files changed, 15 insertions(+), 13 deletions(-) diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index f5d234d..4204241 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -12,11 +12,11 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -config NORTHBRIDGE_AMD_PI_00660F01 +config NORTHBRIDGE_AMD_PI_00670F00 bool select MMCONF_SUPPORT -if NORTHBRIDGE_AMD_PI_00660F01 +if NORTHBRIDGE_AMD_PI_00670F00 config HW_MEM_HOLE_SIZEK hex @@ -36,13 +36,13 @@ config MMCONF_BUS_NUMBER config VGA_BIOS_ID string - default "1002,9870" + default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c. config VGA_BIOS_FILE string - default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" + default "3rdparty/blobs/northbridge/amd/00670F00/VBIOS.bin" endif diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h index ab0e3d2..917bc65 100644 --- a/src/northbridge/amd/pi/00670F00/chip.h +++ b/src/northbridge/amd/pi/00670F00/chip.h @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#ifndef _PI_FAM15CZ_CHIP_H_ -#define _PI_FAM15CZ_CHIP_H_ +#ifndef _PI_FAM15ST_CHIP_H_ +#define _PI_FAM15ST_CHIP_H_ -struct northbridge_amd_pi_00660F01_config +struct northbridge_amd_pi_00670F00_config { u8 spdAddrLookup[2][2][4]; }; diff --git a/src/northbridge/amd/pi/00670F00/dimmSpd.c b/src/northbridge/amd/pi/00670F00/dimmSpd.c index 5c81f36..2880d4e 100644 --- a/src/northbridge/amd/pi/00670F00/dimmSpd.c +++ b/src/northbridge/amd/pi/00670F00/dimmSpd.c @@ -28,7 +28,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress; ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; + ROMSTAGE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info; if ((dev == 0) || (config == 0)) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 1caecf9..51d6960 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -582,7 +582,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, }; static void fam15_finalize(void *chip_info) @@ -600,7 +600,7 @@ static void fam15_finalize(void *chip_info) pci_write_config32(dev, 0x60, value); } -struct chip_operations northbridge_amd_pi_00660F01_ops = { +struct chip_operations northbridge_amd_pi_00670F00_ops = { CHIP_NAME("AMD FAM15 Northbridge") .enable_dev = 0, .final = fam15_finalize, @@ -1140,8 +1140,8 @@ static void root_complex_enable_dev(struct device *dev) } } -struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = { - CHIP_NAME("AMD FAM16 Root Complex") +struct chip_operations northbridge_amd_pi_00670F00_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") .enable_dev = root_complex_enable_dev, }; @@ -1152,7 +1152,7 @@ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev; new_vendev = - ((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev; + ((0x100298E0 <= vendev) && (vendev <= 0x100298EF)) ? 0x100298E0 : vendev; if (vendev != new_vendev) printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index cb72416..04dd73c 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -30,6 +30,7 @@ config S3_VGA_ROM_RUN source src/northbridge/amd/pi/00630F01/Kconfig source src/northbridge/amd/pi/00730F01/Kconfig +source src/northbridge/amd/pi/00670F00/Kconfig source src/northbridge/amd/pi/00660F01/Kconfig config HW_MEM_HOLE_SIZEK diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index 5c2d8e0..a16c43e 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -17,6 +17,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y) subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 romstage-y += agesawrapper.c

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New patch to review for coreboot: northbridge/amd: Copy 00660F01 directories to 00670F00
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17142 -gerrit commit 2409212cf07fb4532ee5adbcd69b4dc684e4f272 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:14:15 2016 -0600 northbridge/amd: Copy 00660F01 directories to 00670F00 Prepare for new 00670FF00 support. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 037cf16883fafd329a15f903ddf97e24a879bcce) Change-Id: I130d4f13beb2c1d71e4e4e9be5011f7993b34660 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/Kconfig | 48 + src/northbridge/amd/pi/00670F00/Makefile.inc | 18 + .../amd/pi/00670F00/acpi/northbridge.asl | 131 +++ src/northbridge/amd/pi/00670F00/chip.h | 24 + src/northbridge/amd/pi/00670F00/dimmSpd.c | 49 + src/northbridge/amd/pi/00670F00/northbridge.c | 1161 ++++++++++++++++++++ src/northbridge/amd/pi/00670F00/northbridge.h | 22 + 7 files changed, 1453 insertions(+) diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig new file mode 100644 index 0000000..f5d234d --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -0,0 +1,48 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +config NORTHBRIDGE_AMD_PI_00660F01 + bool + select MMCONF_SUPPORT + +if NORTHBRIDGE_AMD_PI_00660F01 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 + +config MMCONF_BUS_NUMBER + int + default 64 + +config VGA_BIOS_ID + string + default "1002,9870" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in northbridge.c. + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" + +endif diff --git a/src/northbridge/amd/pi/00670F00/Makefile.inc b/src/northbridge/amd/pi/00670F00/Makefile.inc new file mode 100644 index 0000000..7107d84 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/Makefile.inc @@ -0,0 +1,18 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += dimmSpd.c + +ramstage-y += northbridge.c diff --git a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl new file mode 100644 index 0000000..cde5182 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ +Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + +/* Describe the Northbridge devices */ + +Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ +{ + Return(Zero) +} + +Method(_STA, 0, NotSerialized) +{ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0, NotSerialized) +{ + If(PMOD) + { + Return(APR0) /* APIC mode */ + } + Return (PR0) /* PIC Mode */ +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Gpp 0 */ +Device(PBR4) { + Name(_ADR, 0x00020001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Gpp 1 */ +Device(PBR5) { + Name(_ADR, 0x00020002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Gpp 2 */ +Device(PBR6) { + Name(_ADR, 0x00020003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* Gpp 3 */ +Device(PBR7) { + Name(_ADR, 0x00020004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +/* Gpp 4 */ +Device(PBR8) { + Name(_ADR, 0x00020005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS8) } /* APIC mode */ + Return (PS8) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 1 */ +Device(PBR9) { + Name(_ADR, 0x00030002) +} /* end PBR8 */ + +/* GFX 2 */ +Device(PBRA) { + Name(_ADR, 0x00030003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSA) } /* APIC mode */ + Return (PSA) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 3 */ +Device(PBRB) { + Name(_ADR, 0x00030004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSB) } /* APIC mode */ + Return (PSB) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 4 */ +Device(PBRC) { + Name(_ADR, 0x00030005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSC) } /* APIC mode */ + Return (PSC) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h new file mode 100644 index 0000000..ab0e3d2 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PI_FAM15CZ_CHIP_H_ +#define _PI_FAM15CZ_CHIP_H_ + +struct northbridge_amd_pi_00660F01_config +{ + u8 spdAddrLookup[2][2][4]; +}; + +#endif diff --git a/src/northbridge/amd/pi/00670F00/dimmSpd.c b/src/northbridge/amd/pi/00670F00/dimmSpd.c new file mode 100644 index 0000000..5c81f36 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/dimmSpd.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <device/device.h> +#include <stdlib.h> + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "chip.h" +#include "northbridge/amd/pi/dimmSpd.h" + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +{ + int spdAddress; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; + + if ((dev == 0) || (config == 0)) + return AGESA_ERROR; + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + spdAddress = config->spdAddrLookup + [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) + return AGESA_ERROR; + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + if (err) + return AGESA_ERROR; + return AGESA_SUCCESS; +} diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c new file mode 100644 index 0000000..1caecf9 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -0,0 +1,1161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <lib.h> +#include <cpu/cpu.h> +#include <cbmem.h> + +#include <Porting.h> +#include <AGESA.h> +#include <FieldAccessors.h> +#include <Options.h> +#include <Topology.h> +#include <cpu/amd/amdfam15.h> +#include <cpuRegisters.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include "northbridge.h" + +#include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp << 21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.base |= temp << 21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit + for (i = 0; i < node_nums; i++) + pci_write_config32(__f1_dev[i], reg + 4, tempreg); + tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? + for (i = 0; i < node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static device_t get_node_pci(u32 nodeid, u32 fn) +{ +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } +#else + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); +#endif +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for (i = 0; i < fx_devs; i++) { + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid << 4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resoure does not exist, usable + * @retval 0 resource exists, not usable + * @retval 1 resource exist, resource has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + + if (!res) + result = 2; + else if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + else + result = 0; + + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result >= 1) { + free_reg = reg; + } + if (result == 1) { + /* resource allocated */ + break; + } + } + resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result >= 1) { + free_reg = reg; + } + if (result == 1) { + /* I have been allocated this one */ + break; + } + } + resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); + return resource; +} + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_IO_HOST_ALIGN); + resource->gran = log2(HT_IO_HOST_ALIGN); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + +static void enable_mmconf_resource(device_t dev) +{ + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) + enable_mmconf_resource(dev); +} + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) + return; + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) + return; + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) + return; + + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + snprintf(buf, sizeof(buf), " <node %x link %x>", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + /* do we need this? */ + create_vga_resource(dev, nodeid); + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void northbridge_init(struct device *dev) +{ +} + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +static void northbridge_fill_ssdt_generator(device_t device) +{ + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current, acpi_fill_hest); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + return current; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT, +}; + +static void fam15_finalize(void *chip_info) +{ + device_t dev; + u32 value; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); +} + +struct chip_operations northbridge_amd_pi_00660F01_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, + .final = fam15_finalize, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg < 0xc0) { // mmio + nodeid = (limit & 0xf) + (base & 0x30); + } else { // io + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + + pci_domain_read_resources(dev); +} + +static void domain_enable_resources(device_t dev) +{ + if (acpi_is_wakeup_s3()) + AGESAWRAPPER(fchs3laterestore); + + /* Must be called after PCI enumeration and resource allocation */ + if (!acpi_is_wakeup_s3()) + AGESAWRAPPER(amdinitmid); + + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 2) { + /* we find the hole */ + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + /* We need to double check if there is special set on base reg and limit reg + * are not continuous instead of hole, it will find out its hole_startk. + */ + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t base_k, limit_k; + d = get_dram_base_mask(i); + if (!(d.base & 1)) + continue; + base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (base_k > 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +#define ONE_MB_SHIFT 20 +#define ONE_GB_SHIFT 30 + +static void setup_uma_memory(void) +{ +#if CONFIG_GFXUMA + uint64_t topmem = bsp_topmem(); + uint64_t topmem2 = bsp_topmem2(); + uint32_t sysmem_mb, sysmem_gb; + + /* refer to UMA_AUTO size computation in Family15h BKDG. */ + /* Please reference MemNGetUmaSizeML() */ + /* + * Total system memory UMASize + * >= 6G 1024M + * >= 4G 512M + * >= 2G 256M + * < 2G 128M + */ + + sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; // Ignore 16MB allocated for C6 when finding UMA size + sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; + sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); + printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size %lluMB, topmem size %lluMB\n", + __func__, (unsigned long)sysmem_gb, (topmem2 >> ONE_MB_SHIFT), (topmem >> ONE_MB_SHIFT)); + if (sysmem_gb >= 6) { + uma_memory_size = 1024 << ONE_MB_SHIFT; + } else if (sysmem_gb >= 4) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sysmem_gb >= 2) { + uma_memory_size = 256 << ONE_MB_SHIFT; + } else { + uma_memory_size = 128 << ONE_MB_SHIFT; + } + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#endif +} + + +static void domain_set_resources(device_t dev) +{ + unsigned long mmio_basek; + u32 pci_tolm; + u64 ramtop = 0; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + * MMIO hole. If you fix this here, please fix amdk8, too. + */ + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) + continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + /* split the region to accommodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + if (!ramtop) + ramtop = mmio_basek * 1024; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + uint64_t topmem2 = bsp_topmem2(); + basek = 4*1024*1024; + sizek = topmem2/1024 - basek; + } + } + + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (!ramtop) + ramtop = limitk * 1024; + } + +#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); +#endif + + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +static void cpu_bus_scan(device_t dev) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + u32 modules = 0; + VOID* modules_ptr = &modules; + BUILD_OPT_CFG* options = NULL; + int ioapic_count = 0; + + AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); + AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); + modules = (*(u32*)modules_ptr) && ((1ull << (sizeof(modules) * 8)) - 1); + ASSERT(modules > 0); + ASSERT(options); + ioapic_count = (int)options->CfgPlatNumIoApics; + ASSERT(ioapic_count > 0); + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums > 32) { + /* need to put node 32 to node 63 to bus 0xfe */ + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for (fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + add_more_links(cdb_dev, 4); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 6 || family == 7) { + /* f15 and f16 */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + /* default one core */ + siblings = 0; + } + int enable_node = cdb_dev && cdb_dev->enabled; + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + u32 lapicid_start = 0; + + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ + if ((node_nums * core_max) + ioapic_count >= 0x10) { + lapicid_start = (ioapic_count - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, apic_id); + + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); + } //j + } +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_read_resources(device_t dev) +{ +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " <mmconfig>"); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + static int done = 0; + + /* Do not delay UMA setup, as a device on the PCI bus may evaluate + the global uma_memory variables already in its enable function. */ + if (!done) { + setup_bsp_ramtop(); + setup_uma_memory(); + done = 1; + } + + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = { + CHIP_NAME("AMD FAM16 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + +/********************************************************************* + * Change the vendor / device IDs to match the generic VBIOS header. * + *********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev; + new_vendev = + ((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev; + + if (vendev != new_vendev) + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); + + return new_vendev; +} diff --git a/src/northbridge/amd/pi/00670F00/northbridge.h b/src/northbridge/amd/pi/00670F00/northbridge.h new file mode 100644 index 0000000..e095f9a --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/northbridge.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H +#define NORTHBRIDGE_AMD_AGESA_FAM16H_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */

1 0

New patch to review for coreboot: pci_ids.h: Add ID for amd/00670F00 northbridge
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17141 -gerrit commit f16b1a1ee3d16626141b4ceb99bd7e3a9b197a00 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 22:30:15 2016 -0400 pci_ids.h: Add ID for amd/00670F00 northbridge Add the D18F0 device ID for the Stoney APU. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit c0fd7f70527c273bcbdce5655a21ca4de4854428) Change-Id: Ib599fc6119a3cef53f4f179c2fcd0e45905d81a4 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/include/device/pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 72f1ece..cd0a66e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -290,6 +290,7 @@ #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 #define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT 0x1570 +#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT 0x15B0 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423

1 0

New patch to review for coreboot: cpu/amd: Update files for 00670F00
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17140 -gerrit commit 8daf9f1bc9f62b20209c03b2ddd496ddede16256 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:27:46 2016 -0600 cpu/amd: Update files for 00670F00 Add Stoney specific IDs, code, and fix Makefles and Kconfig files. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 0bd1dc834792453d8e66216fa9a70afe2f7537d7) Change-Id: Id79f316a89b3baeae95e221fb872dc8a86e7b0f1 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00670F00/Kconfig | 4 ++-- src/cpu/amd/pi/00670F00/chip_name.c | 2 +- src/cpu/amd/pi/00670F00/model_15_init.c | 3 +-- src/cpu/amd/pi/Kconfig | 2 ++ src/cpu/amd/pi/Makefile.inc | 1 + 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index de74d3c..456bf4b 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -13,12 +13,12 @@ # GNU General Public License for more details. # -config CPU_AMD_PI_00660F01 +config CPU_AMD_PI_00670F00 bool select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS -if CPU_AMD_PI_00660F01 +if CPU_AMD_PI_00670F00 config CPU_ADDR_BITS int diff --git a/src/cpu/amd/pi/00670F00/chip_name.c b/src/cpu/amd/pi/00670F00/chip_name.c index ff2bc06..98692c6 100644 --- a/src/cpu/amd/pi/00670F00/chip_name.c +++ b/src/cpu/amd/pi/00670F00/chip_name.c @@ -15,6 +15,6 @@ #include <device/device.h> -struct chip_operations cpu_amd_pi_00660F01_ops = { +struct chip_operations cpu_amd_pi_00670F00_ops = { CHIP_NAME("AMD CPU Family 15h") }; diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index e252c3d..041d036 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -130,8 +130,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x660f00 }, - { X86_VENDOR_AMD, 0x660f01 }, + { X86_VENDOR_AMD, 0x670f00 }, { 0, 0 }, }; diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 3e8d5c7..0bfe77c 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -17,6 +17,7 @@ config CPU_AMD_PI bool default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 + default y if CPU_AMD_PI_00670F00 default y if CPU_AMD_PI_00660F01 default n select ARCH_BOOTBLOCK_X86_32 @@ -69,4 +70,5 @@ endif # CPU_AMD_PI source src/cpu/amd/pi/00630F01/Kconfig source src/cpu/amd/pi/00730F01/Kconfig +source src/cpu/amd/pi/00670F00/Kconfig source src/cpu/amd/pi/00660F01/Kconfig diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 569c7af..f85d9b6 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -15,6 +15,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 +subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 romstage-y += s3_resume.c

1 0

New patch to review for coreboot: cpu/amd: Copy 00660F01 to 00670F00
by Marc Jones 26 Oct '16

26 Oct '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17139 -gerrit commit 8f380ccd9ca1b5e63bc43e32e6a626db26f255f2 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:06:43 2016 -0600 cpu/amd: Copy 00660F01 to 00670F00 Prepare for new 00670F00 support. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 87d26e05189247685df0ca6492dc3181a1bad5e8) Change-Id: Ib296ad32a061669b28dae742cac08bb75fdd0de4 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00670F00/Kconfig | 52 ++++++++++++ src/cpu/amd/pi/00670F00/Makefile.inc | 27 ++++++ src/cpu/amd/pi/00670F00/acpi/cpu.asl | 78 ++++++++++++++++++ src/cpu/amd/pi/00670F00/chip_name.c | 20 +++++ src/cpu/amd/pi/00670F00/fixme.c | 94 +++++++++++++++++++++ src/cpu/amd/pi/00670F00/model_15_init.c | 141 ++++++++++++++++++++++++++++++++ 6 files changed, 412 insertions(+) diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig new file mode 100644 index 0000000..de74d3c --- /dev/null +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -0,0 +1,52 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config CPU_AMD_PI_00660F01 + bool + select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_PI_00660F01 + +config CPU_ADDR_BITS + int + default 48 + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_SIZE + hex + default 0x100000 + +config HAVE_INIT_TIMER + bool + default y + +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0xA1000 + +endif diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc new file mode 100644 index 0000000..6c6a2b8 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/Makefile.inc @@ -0,0 +1,27 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += fixme.c +ramstage-y += fixme.c +ramstage-y += chip_name.c +ramstage-y += model_15_init.c + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00670F00/acpi/cpu.asl b/src/cpu/amd/pi/00670F00/acpi/cpu.asl new file mode 100644 index 0000000..aae3287 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/acpi/cpu.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } +} /* End _PR scope */ diff --git a/src/cpu/amd/pi/00670F00/chip_name.c b/src/cpu/amd/pi/00670F00/chip_name.c new file mode 100644 index 0000000..ff2bc06 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/chip_name.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +struct chip_operations cpu_amd_pi_00660F01_ops = { + CHIP_NAME("AMD CPU Family 15h") +}; diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c new file mode 100644 index 0000000..9a38bd8 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include "amdlib.h" + +void amd_initcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} + +void amd_initmmio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); +} diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c new file mode 100644 index 0000000..e252c3d --- /dev/null +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/amdfam15.h> +#include <arch/acpi.h> +#include <cpu/amd/pi/s3_resume.h> + +#include <amdlib.h> +#include <PspBaseLib.h> + +void PSPProgBar3Msr(void *Buffer); + +void PSPProgBar3Msr(void *Buffer) +{ + u32 Bar3Addr; + u64 Tmp64; + /* Get Bar3 Addr */ + Bar3Addr = PspLibPciReadPspConfig (0x20); + Tmp64 = Bar3Addr; + printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); + LibAmdMsrWrite (0xC00110A2, &Tmp64, NULL); + LibAmdMsrRead (0xC00110A2, &Tmp64, NULL); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS + u32 siblings; +#endif + + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + if (acpi_is_wakeup()) + restore_mtrr(); + + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + + /* Enable the local CPU APICs */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + PSPProgBar3Msr(NULL); + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x660f00 }, + { X86_VENDOR_AMD, 0x660f01 }, + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +};

1 0

New patch to review for coreboot: skylake: Use COMMON_FADT
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17138 -gerrit commit 833d2bbdd710623ae09dbb90c4129a993ae05f20 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 17 19:47:51 2016 -0700 skylake: Use COMMON_FADT Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/fadt.c | 47 ------------------------------------ src/mainboard/google/glados/fadt.c | 47 ------------------------------------ src/mainboard/google/lars/fadt.c | 47 ------------------------------------ src/mainboard/intel/kunimitsu/fadt.c | 47 ------------------------------------ src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/acpi.c | 5 +++- 6 files changed, 5 insertions(+), 189 deletions(-) diff --git a/src/mainboard/google/chell/fadt.c b/src/mainboard/google/chell/fadt.c deleted file mode 100644 index 92987f9..0000000 --- a/src/mainboard/google/chell/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/glados/fadt.c b/src/mainboard/google/glados/fadt.c deleted file mode 100644 index 92987f9..0000000 --- a/src/mainboard/google/glados/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/lars/fadt.c b/src/mainboard/google/lars/fadt.c deleted file mode 100644 index 05fea01..0000000 --- a/src/mainboard/google/lars/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/intel/kunimitsu/fadt.c b/src/mainboard/intel/kunimitsu/fadt.c deleted file mode 100644 index 05fea01..0000000 --- a/src/mainboard/intel/kunimitsu/fadt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a5fb0e8..7591d66 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS + select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB select HAVE_HARD_RESET diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 196302e..26e2e3a 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -219,12 +219,15 @@ unsigned long acpi_fill_madt(unsigned long current) return acpi_madt_irq_overrides(current); } -void acpi_fill_in_fadt(acpi_fadt_t *fadt) +void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); config_t *config = dev->chip_info; + /* Use ACPI 5.0 revision */ + fadt->header.revision = ACPI_FADT_REV_ACPI_5_0; + fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

1 0

New patch to review for coreboot: skylake: Fix wake source reporting with Deep S3
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17137 -gerrit commit 0c1579bb2f64730f800796e2f1c7ff044954af99 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:07:22 2016 -0700 skylake: Fix wake source reporting with Deep S3 The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 28a0a6e..196302e 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -584,23 +584,37 @@ void southcluster_inject_dsdt(device_t device) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = dev->chip_info; struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; + uint32_t gpe0_std; int i; ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps == NULL) return -1; - /* PM1_EN state is lost in Deep S3 so enable basic wake events */ - pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS; + pm1_en = ps->pm1_en; + gpe0_std = ps->gpe0_en[3]; + + /* Chipet state is lost in Deep S3 so enable Deep S3 wake events */ + if (ps->prev_sleep_state == ACPI_S3 && config->deep_s3_enable) { + pm1_en |= PWRBTN_STS; + if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN) + gpe0_std |= LAN_WAK_EN; + if (config->deep_sx_config & DSX_EN_WAKE_PIN) + pm1_en |= PCIEXPWAK_STS; + } + *pm1 = ps->pm1_sts & pm1_en; /* Mask off GPE0 status bits that are not enabled */ *gpe0 = &gpe0_sts[0]; - for (i = 0; i < GPE0_REG_MAX; i++) + for (i = 0; i < (GPE0_REG_MAX-1); i++) gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; + gpe0_sts[3] = ps->gpe0_sts[3] & gpe0_std; return GPE0_REG_MAX; }

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New patch to review for coreboot: skylake: Support for early I2C TPM driver
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17136 -gerrit commit 7c60288ab7eb9fdff70bb247897c36253145338d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:05:31 2016 -0700 skylake: Support for early I2C TPM driver Add the SOC definition for acpi_get_gpe() so it can be used by the I2C TPM driver. Also add the I2C support code to verstage so it can get used by vboot. BUG=chrome-os-partner:58666 TEST=boot with I2C TPM on skylake board Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/pmutil.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index d7f772d..b06c85b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -31,6 +31,7 @@ verstage-y += flash_controller.c verstage-y += monotonic_timer.c verstage-y += pch.c verstage-y += pmutil.c +verstage-y += bootblock/i2c.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c romstage-y += flash_controller.c diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 6ead7ed..203a430 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -356,6 +356,26 @@ u32 clear_gpe_status(void) gpe0_sts_3_bits); } +/* Read and clear GPE status (defined in arch/acpi.h) */ +int acpi_get_gpe(int gpe) +{ + int bank; + uint32_t mask, sts; + + if (gpe < 0 || gpe > GPE0_WADT) + return -1; + + bank = gpe / 32; + mask = 1 << (gpe % 32); + + sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); + if (sts & mask) { + outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + return 1; + } + return 0; +} + /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) {

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New patch to review for coreboot: skylake: Setup GPE in bootblock
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17135 -gerrit commit 10a549964138f6b3377b3d1e216eafc2dff3980e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 20:03:56 2016 -0700 skylake: Setup GPE in bootblock Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/bootblock/pch.c | 3 ++ src/soc/intel/skylake/include/soc/pci_devs.h | 2 +- src/soc/intel/skylake/include/soc/pm.h | 3 ++ src/soc/intel/skylake/pmc.c | 39 +--------------------- src/soc/intel/skylake/pmutil.c | 48 ++++++++++++++++++++++++++++ 6 files changed, 57 insertions(+), 39 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index bf429ef..d7f772d 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -30,6 +30,7 @@ bootblock-y += tsc_freq.c verstage-y += flash_controller.c verstage-y += monotonic_timer.c verstage-y += pch.c +verstage-y += pmutil.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c romstage-y += flash_controller.c diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 57b5fed..9f5df02 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -301,6 +301,9 @@ void pch_early_init(void) /* Program SMBUS_BASE_ADDRESS and Enable it */ enable_smbus(); + /* Set up GPE configuration. */ + pmc_gpe_init(); + soc_config_rtc(); enable_heci(); diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 476e2c6..974f1d8 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -23,7 +23,7 @@ #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 91f037a..0045fa0 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -187,6 +187,9 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Initialize GPEs */ +void pmc_gpe_init(void); + static inline int deep_s3_enabled(void) { uint32_t deep_s3_pol; diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index fd04287..23a289b 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -129,42 +129,6 @@ static void pch_rtc_init(void) cmos_init(rtc_failed); } -static void pmc_gpe_init(config_t *config) -{ - uint8_t *pmc_regs; - uint32_t gpio_cfg; - uint32_t gpio_cfg_reg; - const uint32_t gpio_cfg_mask = - (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW2_SHIFT); - - pmc_regs = pmc_mmio_regs(); - gpio_cfg = 0; - - /* Route the GPIOs to the GPE0 block. Determine that all values - * are different, and if they aren't use the reset values. */ - if (config->gpe0_dw0 == config->gpe0_dw1 || - config->gpe0_dw1 == config->gpe0_dw2) { - printk(BIOS_INFO, "PMC: Using default GPE route.\n"); - gpio_cfg = read32(pmc_regs + GPIO_CFG); - } else { - gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; - gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; - gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; - } - gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; - gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; - write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); - - /* Set the routes in the GPIO communities as well. */ - gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); - - /* Set GPE enables based on devictree. */ - enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, - config->gpe0_en_3, config->gpe0_en_4); -} - static void pch_power_options(void) { u16 reg16; @@ -172,7 +136,6 @@ static void pch_power_options(void) /*PMC Controller Device 0x1F, Func 02*/ device_t dev = PCH_DEV_PMC; /* Get the chip configuration */ - config_t *config = dev->chip_info; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* @@ -207,7 +170,7 @@ static void pch_power_options(void) printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ - pmc_gpe_init(config); + pmc_gpe_init(); } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index e450ce8..6ead7ed 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -19,6 +19,8 @@ * and the differences between PCH variants. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -27,6 +29,7 @@ #include <halt.h> #include <rules.h> #include <stdlib.h> +#include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -34,6 +37,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include "chip.h" /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -446,3 +450,47 @@ void poweroff(void) if (!ENV_SMM) halt(); } + +void pmc_gpe_init(void) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + uint8_t *pmc_regs; + uint32_t gpio_cfg; + uint32_t gpio_cfg_reg; + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT); + + /* Look up the device in devicetree */ + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + pmc_regs = pmc_mmio_regs(); + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. */ + gpio_cfg = 0; + if (config->gpe0_dw0 == config->gpe0_dw1 || + config->gpe0_dw1 == config->gpe0_dw2) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32(pmc_regs + GPIO_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + } + gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); + + /* Set GPE enables based on devictree. */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); +}

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New patch to review for coreboot: skylake: Add support for eSPI SMI events
by Duncan Laurie 26 Oct '16

26 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17134 -gerrit commit 9b252f7c67208f80264ab9b5d69744fff297a305 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 19:58:27 2016 -0700 skylake: Add support for eSPI SMI events Add the necessary infrastructure to support eSPI SMI events, and a mainboard handler to pass control to the EC. BUG=chrome-os-partner:58666 TEST=tested on eve board with eSPI enabled, verified that lid close event from the EC during firmware will result in an SMI and shut down the system. Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/include/soc/pm.h | 1 + src/soc/intel/skylake/include/soc/smm.h | 2 ++ src/soc/intel/skylake/pmutil.c | 3 ++- src/soc/intel/skylake/smi.c | 3 ++- src/soc/intel/skylake/smihandler.c | 7 +++++++ 5 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 235ad89..91f037a 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -46,6 +46,7 @@ #define SMI_EN 0x30 #define XHCI_SMI_EN (1 << 31) #define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) #define GPIO_UNLOCK_SMI_EN (1 << 27) #define INTEL_USB2_EN (1 << 18) #define LEGACY_USB2_EN (1 << 17) diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 1beaaa4..71083b3 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -50,6 +50,8 @@ struct smm_relocation_params { /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); +/* Mainboard handler for eSPI SMIs */ +void mainboard_smi_espi_handler(void); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 31de242..e450ce8 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -173,7 +173,8 @@ static u32 print_smi_status(u32 smi_sts) [20] = "PCI_EXP_SMI", [21] = "MONITOR", [26] = "SPI", - [27] = "GPIO_UNLOCK" + [27] = "GPIO_UNLOCK", + [28] = "ESPI_SMI", }; if (!smi_sts) diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c index 77f3951..442607f 100644 --- a/src/soc/intel/skylake/smi.c +++ b/src/soc/intel/skylake/smi.c @@ -62,11 +62,12 @@ void southbridge_smm_enable_smi(void) * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) * No SMIs: * - on microcontroller writes (io 0x62/0x66) * - on TCO events */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS); } void southbridge_trigger_smi(void) diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 1834815..872cce1 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -361,6 +361,12 @@ static void southbridge_smi_gpi(void) gpi_clear_get_smi_status(&smi_sts); } +void __attribute__((weak)) mainboard_smi_espi_handler(void) { } +static void southbridge_smi_espi(void) +{ + mainboard_smi_espi_handler(); +} + static void southbridge_smi_mc(void) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -482,6 +488,7 @@ static smi_handler_t southbridge_smi[SMI_STS_BITS] = { [PM1_STS_BIT] = southbridge_smi_pm1, [GPE0_STS_BIT] = southbridge_smi_gpe0, [GPIO_STS_BIT] = southbridge_smi_gpi, + [ESPI_SMI_STS_BIT] = southbridge_smi_espi, [MCSMI_STS_BIT] = southbridge_smi_mc, [TCO_STS_BIT] = southbridge_smi_tco, [PERIODIC_STS_BIT] = southbridge_smi_periodic,

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coreboot-gerrit October 2016