coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

1 participants
814 discussions

Patch merged into coreboot/master: rockchip: rk3288: fix phsync & pvsync bug
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 84fb0bfdbbfc298849bb246c1b192505f5aca10d Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Jul 21 22:47:55 2015 -0500 rockchip: rk3288: fix phsync & pvsync bug Struct edid defien pvsync & phsync as an character, like '+' or '-', so we need to check sync polarity by comparing with characters '+' and '-' instead of treating as boolean. BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, light monitor normally Change-Id: I92d233e19b6df8917fb8ff9a327ccb842c152d65 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2d22d4b6e7108474f67200e0fb1e4894cd88db85 Original-Change-Id: I14c72aa8994227092a1059d2b25c1dd2249b9db1 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/289963 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/11380 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11380 for details. -gerrit

1 0

Patch merged into coreboot/master: stdlib: don't hide the malloc et all declarations
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 8d0ab89e5d5befd57bc72f1d46cc572caa6ba5bc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 27 14:04:02 2015 -0500 stdlib: don't hide the malloc et all declarations It doesn't hurt to expose declarations. Instead of a compile-time error there'll be a link error if someone tries to malloc() anything. Change-Id: Ief6f22c168c660a6084558b5889ea4cc42fefdde Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11406 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11406 for details. -gerrit

1 0

Patch set updated for coreboot: stdlib: don't hide the malloc et all declarations
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11406 -gerrit commit 313b03c7056294cadef2737acab6a05e4a917a5a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 27 14:04:02 2015 -0500 stdlib: don't hide the malloc et all declarations It doesn't hurt to expose declarations. Instead of a compile-time error there'll be a link error if someone tries to malloc() anything. Change-Id: Ief6f22c168c660a6084558b5889ea4cc42fefdde Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/stdlib.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 35e8b32..13f48e2 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -20,12 +20,10 @@ #define min(a,b) MIN((a),(b)) #define max(a,b) MAX((a),(b)) -#if !defined(__PRE_RAM__) void *memalign(size_t boundary, size_t size); void *malloc(size_t size); /* We never free memory */ static inline void free(void *ptr) {} -#endif #ifndef __ROMCC__ static inline unsigned long div_round_up(unsigned int n, unsigned int d)

1 0

Patch set updated for coreboot: Kconfig: Remove EXPERT mode
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11365 -gerrit commit c1db6a2da173432d57ada7b820758ee0ff685fe6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 26 10:11:02 2015 -0400 Kconfig: Remove EXPERT mode After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- payloads/external/SeaBIOS/Kconfig | 1 - src/Kconfig | 11 ----------- src/device/Kconfig | 4 ++-- src/northbridge/amd/amdfam10/Kconfig | 2 +- src/northbridge/amd/amdht/h3finit.c | 4 ++-- 5 files changed, 5 insertions(+), 17 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index b2ff21e..699b986 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -18,7 +18,6 @@ endchoice config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 - depends on EXPERT int help Some PS/2 keyboard controllers don't respond to commands immediately diff --git a/src/Kconfig b/src/Kconfig index 9c01687..2c75750 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -22,14 +22,6 @@ mainmenu "coreboot configuration" menu "General setup" -config EXPERT - bool "Expert mode" - help - This allows you to select certain advanced configuration options. - - Warning: Only enable this option if you really know what you are - doing! You have been warned! - config LOCALVERSION string "Local version string" help @@ -111,7 +103,6 @@ config CCACHE config FMD_GENPARSER bool "Generate flashmap descriptor parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the flashmap descriptor parser and made changes to fmd_scanner.l or fmd_parser.y. @@ -121,7 +112,6 @@ config FMD_GENPARSER config SCONFIG_GENPARSER bool "Generate SCONFIG parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l or sconfig.y. @@ -283,7 +273,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n - depends on EXPERT help Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. diff --git a/src/device/Kconfig b/src/device/Kconfig index d9d1bab..3bee877 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI || EXPERT + depends on PCI help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 13954d4..4d7147d 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -120,7 +120,7 @@ config SVI_HIGH_FREQ menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT + depends on (NORTHBRIDGE_AMD_AMDFAM10) choice prompt "HyperTransport downlink width" diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 0138cd9..849f4a8 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1399,13 +1399,13 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 +#if CONFIG_LIMIT_HT_DOWN_WIDTH_8 cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_UP_WIDTH_8 +#if CONFIG_LIMIT_HT_UP_WIDTH_8 cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16;

1 0

Patch set updated for coreboot: Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11293 -gerrit commit 1f45cba5c2dd09a8a9a1ed713a673c8a67e774a7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 20 16:25:02 2015 -0400 Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/device/Kconfig | 4 ++-- src/mainboard/google/cyan/Kconfig | 2 -- src/mainboard/google/rambi/Kconfig | 2 -- src/mainboard/intel/strago/Kconfig | 2 -- src/soc/intel/broadwell/Kconfig | 2 -- src/soc/intel/skylake/Kconfig | 2 -- 6 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d780d13..d9d1bab 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on PCI || EXPERT help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index f3bb851..e4dc322 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -2,8 +2,6 @@ if BOARD_GOOGLE_CYAN config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 1ad2d6d..825df9a 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,8 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 1d4d4d8..1512a46 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -2,8 +2,6 @@ if BOARD_INTEL_STRAGO config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 524366c..0106255 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f42d3ab..9805b6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

1 0

Patch merged into coreboot/master: packardbell/ms2290/mainboard.c: Do not guard int15 includes
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit d18065b59c7523e35b422ba419d85495729ad7ca Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 26 23:04:34 2015 -0700 packardbell/ms2290/mainboard.c: Do not guard int15 includes Do not guard the inclusion of "drivers/intel/gma/int15.h" and "arch/interrupt.h" with configs that control option rom execution. These headers already have the proper guards. The install_intel_vga_int15_handler() is unconditionally called, even when the header that declares it is guarded out. Change-Id: Ia273437486f5802aa2b53212f2a1b5704c9485fa Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/11379 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11379 for details. -gerrit

1 0

New patch to review for coreboot: stdlib: don't hide the malloc et all declarations
by Aaron Durbin 27 Aug '15

27 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11406 -gerrit commit 6e0bfc9fdec2ec32bf98ff238420eaf93e8b0c02 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 27 14:04:02 2015 -0500 stdlib: don't hide the malloc et all declarations It doesn't hurt to expose declarations. Instead of a compile-time error there'll be a link error if someone tries to malloc() anything. Change-Id: Ief6f22c168c660a6084558b5889ea4cc42fefdde Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/stdlib.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 35e8b32..13f48e2 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -20,12 +20,10 @@ #define min(a,b) MIN((a),(b)) #define max(a,b) MAX((a),(b)) -#if !defined(__PRE_RAM__) void *memalign(size_t boundary, size_t size); void *malloc(size_t size); /* We never free memory */ static inline void free(void *ptr) {} -#endif #ifndef __ROMCC__ static inline unsigned long div_round_up(unsigned int n, unsigned int d)

1 0

Patch set updated for coreboot: riscv-memlayout: fix existing memlayout issues, add sbi interface
by Thaminda Edirisooriya 27 Aug '15

27 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370 -gerrit commit 63b1390ad7cc6779af175aa777470da810dfdeec Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:39:16 2015 -0700 riscv-memlayout: fix existing memlayout issues, add sbi interface Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Update Makefile to include all the files necessary for sbi interface. Clean up unused include in src/arch/riscv/include/atomic.h and whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/Makefile.inc | 3 + src/arch/riscv/bootblock.S | 108 ++++++++++++++++++++--- src/arch/riscv/include/atomic.h | 1 - src/mainboard/emulation/spike-riscv/memlayout.ld | 10 +-- 4 files changed, 102 insertions(+), 20 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c7a2c16..64d5ce9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ @@ -85,6 +86,8 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += trap_handler.c +ramstage-y += virtual_memory.c ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index a26b144..4caeea6 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,7 +1,7 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2013Google Inc. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,34 +22,112 @@ .section ".text._start", "ax", %progbits // Maybe there's a better way. -.space 0x200 +# machine mode handler when in supervisor mode +.space 0x140 +supervisor_machine_handler: + j supervisor_trap_entry + +# handler for when +.space 0x7c +.globl machine_handler +machine_handler: +# call trap_handler + j trap_entry + +.space 0x3c .globl _start _start: // pending figuring out this f-ing toolchain. Hardcode what we know works. -// la sp, 0x4ef0 // .stacktop -// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv - la sp, 0x7FF00 // stack start + stack size + la sp, 0x80FFF0 // stack start + stack size - // make room for HLS + # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - + csrr a0, mhartid + call hls_init //poison the stack - la t1, 0x40000 + la t1, 0x800000 li t0, 0xdeadbeef sd t0, 0(t1) -// la gp, _gp + la t0, exception_handler + csrw stvec, t0 # clear any pending interrupts -#if __GNUC__ < 5 - csrwi clear_ipi, 0 -#else csrwi sip, 0 -#endif + # set up the mstatus register for VM + call mstatus_init call main +.=0x2000 + .space 0x800 +# sbi interface lives here + +# hart_id +.align 5 +li a7, 0 +ecall +ret + +# num_harts +.align 4 +li a0, 1 +ret + +# query_memory +.align 4 +li a7, 8 +ecall +ret + +# console_putchar +.align 4 +li a7, 1 +ecall +ret + +# send_device_request +.align 4 +li a7, 2 +ecall +ret + +# receive_device_response +.align 4 +li a7, 3 +ecall +ret + +# send ipi +.align 4 +li a7, 4 +ecall +ret + +# clear ipi +.align 4 +li a7, 5 +ecall +ret + +# timebase +.align 4 +li a0, 10000000 # temporary, we should provide the correct answer +ret + +# shutdown +.align 4 +li a7, 6 +ecall + +# set_timer +.align 4 +li a7, 7 +ecall +ret + +# end of SBI trampolines .=0x4000 .stack: .align 8 @@ -59,7 +137,9 @@ _start: .align 3 .stack_size: .quad 0xf00 - +.globl test_trap +exception_handler: + call trap_handler reset: init_stack_loop: diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h index 8d7295d..f63f6e1 100644 --- a/src/arch/riscv/include/atomic.h +++ b/src/arch/riscv/include/atomic.h @@ -3,7 +3,6 @@ #ifndef _RISCV_ATOMIC_H #define _RISCV_ATOMIC_H -//#include "config.h" #include <arch/encoding.h> #define disable_irqsave() clear_csr(sstatus, SSTATUS_IE) diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8801f35..8e2e7ee 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,10 +23,10 @@ SECTIONS { - DRAM_START(0x0) + DRAM_START(0x0) BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + STACK(8M, 64K) + ROMSTAGE(8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(8M + 192k, 8K) + RAMSTAGE(8M + 200K, 256K) }

1 0

Patch set updated for coreboot: riscv-memlayout: fix existing memlayout issues, add sbi interface
by Thaminda Edirisooriya 27 Aug '15

27 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370 -gerrit commit 427593cd35b13573dbe27b77daa8840a60bd22e3 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:39:16 2015 -0700 riscv-memlayout: fix existing memlayout issues, add sbi interface Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Update Makefile to include all the files necessary for sbi interface. To build, update to src/arch/riscv/include/atomic.h was required to remove compiler warnings Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/Makefile.inc | 3 + src/arch/riscv/bootblock.S | 108 ++++++++++++++++++++--- src/arch/riscv/include/atomic.h | 1 - src/mainboard/emulation/spike-riscv/memlayout.ld | 10 +-- 4 files changed, 102 insertions(+), 20 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c7a2c16..64d5ce9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ @@ -85,6 +86,8 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += trap_handler.c +ramstage-y += virtual_memory.c ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index a26b144..4caeea6 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,7 +1,7 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2013Google Inc. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,34 +22,112 @@ .section ".text._start", "ax", %progbits // Maybe there's a better way. -.space 0x200 +# machine mode handler when in supervisor mode +.space 0x140 +supervisor_machine_handler: + j supervisor_trap_entry + +# handler for when +.space 0x7c +.globl machine_handler +machine_handler: +# call trap_handler + j trap_entry + +.space 0x3c .globl _start _start: // pending figuring out this f-ing toolchain. Hardcode what we know works. -// la sp, 0x4ef0 // .stacktop -// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv - la sp, 0x7FF00 // stack start + stack size + la sp, 0x80FFF0 // stack start + stack size - // make room for HLS + # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - + csrr a0, mhartid + call hls_init //poison the stack - la t1, 0x40000 + la t1, 0x800000 li t0, 0xdeadbeef sd t0, 0(t1) -// la gp, _gp + la t0, exception_handler + csrw stvec, t0 # clear any pending interrupts -#if __GNUC__ < 5 - csrwi clear_ipi, 0 -#else csrwi sip, 0 -#endif + # set up the mstatus register for VM + call mstatus_init call main +.=0x2000 + .space 0x800 +# sbi interface lives here + +# hart_id +.align 5 +li a7, 0 +ecall +ret + +# num_harts +.align 4 +li a0, 1 +ret + +# query_memory +.align 4 +li a7, 8 +ecall +ret + +# console_putchar +.align 4 +li a7, 1 +ecall +ret + +# send_device_request +.align 4 +li a7, 2 +ecall +ret + +# receive_device_response +.align 4 +li a7, 3 +ecall +ret + +# send ipi +.align 4 +li a7, 4 +ecall +ret + +# clear ipi +.align 4 +li a7, 5 +ecall +ret + +# timebase +.align 4 +li a0, 10000000 # temporary, we should provide the correct answer +ret + +# shutdown +.align 4 +li a7, 6 +ecall + +# set_timer +.align 4 +li a7, 7 +ecall +ret + +# end of SBI trampolines .=0x4000 .stack: .align 8 @@ -59,7 +137,9 @@ _start: .align 3 .stack_size: .quad 0xf00 - +.globl test_trap +exception_handler: + call trap_handler reset: init_stack_loop: diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h index 8d7295d..f63f6e1 100644 --- a/src/arch/riscv/include/atomic.h +++ b/src/arch/riscv/include/atomic.h @@ -3,7 +3,6 @@ #ifndef _RISCV_ATOMIC_H #define _RISCV_ATOMIC_H -//#include "config.h" #include <arch/encoding.h> #define disable_irqsave() clear_csr(sstatus, SSTATUS_IE) diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8801f35..8e2e7ee 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,10 +23,10 @@ SECTIONS { - DRAM_START(0x0) + DRAM_START(0x0) BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + STACK(8M, 64K) + ROMSTAGE(8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(8M + 192k, 8K) + RAMSTAGE(8M + 200K, 256K) }

1 0

Patch set updated for coreboot: riscv-virtual-memory: Add virtual memory setup
by Thaminda Edirisooriya 27 Aug '15

27 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11369 -gerrit commit a9e9ec3be876ad9fb2d88a336ea295cf92a073bd Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:28:04 2015 -0700 riscv-virtual-memory: Add virtual memory setup Execution in supervisor level code in RISCV requires early setup of virtual memory. Add initialization calls in src/arch/riscv/virtual_memory.c to implement the required page table setup, and helper functions to use when jumping to the payload correctly in riscv. Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/include/vm.h | 74 +++++++++++++++++++++ src/arch/riscv/virtual_memory.c | 142 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 216 insertions(+) diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h new file mode 100644 index 0000000..f9ffc40 --- /dev/null +++ b/src/arch/riscv/include/vm.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _VM_H +#define _VM_H + +#include <string.h> +#include <stdint.h> + +#define SUPERPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS)) +#define VM_CHOICE VM_SV39 +#define VA_BITS 39 +#define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) + +#define PROT_READ 1 +#define PROT_WRITE 2 +#define PROT_EXEC 4 + +#define MAP_PRIVATE 0x2 +#define MAP_FIXED 0x10 +#define MAP_ANONYMOUS 0x20 +#define MAP_POPULATE 0x8000 +#define MREMAP_FIXED 0x2 + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define supervisor_paddr_valid(start, length) \ + ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \ + && (uintptr_t)(start) + (length) < mem_size \ + && (uintptr_t)(start) + (length) >= (uintptr_t)(start)) + +typedef uintptr_t pte_t; +extern pte_t* root_page_table; + +void enter_supervisor(void); +void initVirtualMemory(void); + +size_t pte_ppn(pte_t pte); +pte_t ptd_create(uintptr_t ppn); +pte_t pte_create(uintptr_t ppn, int prot, int user); + +void walk_page_table(void); + +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); +void mstatus_init(void); // need to setup mstatus so we know we have virtual memory + +void flush_tlb(void); + +#endif diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c new file mode 100644 index 0000000..2095bfa --- /dev/null +++ b/src/arch/riscv/virtual_memory.c @@ -0,0 +1,142 @@ +/* + * Early initialization code for riscv virtual memory + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <vm.h> +#include <arch/encoding.h> +#include <atomic.h> +#include <stdint.h> +#include <console/console.h> + +pte_t* root_page_table; + +void walk_page_table(void) { + // TODO: implement a full walk to make sure memory was set up + //const size_t pte_per_page = RISCV_PGSIZE/sizeof(void*); + pte_t* t = root_page_table; + printk(BIOS_DEBUG, "root_page_table: %p\n", t); +} + +void enter_supervisor(void) { + // enter supervisor mode + asm volatile("la t0, 1f; csrw mepc, t0; eret; 1:" ::: "t0"); +} + +void flush_tlb(void) +{ + asm volatile("sfence.vm"); +} + +size_t pte_ppn(pte_t pte) +{ + return pte >> PTE_PPN_SHIFT; +} + +pte_t ptd_create(uintptr_t ppn) +{ + return (ppn << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_TABLE; +} + +pte_t pte_create(uintptr_t ppn, int prot, int user) +{ + pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_V; + if (prot & PROT_WRITE) pte |= PTE_TYPE_URW_SRW; + if (prot & PROT_EXEC) pte |= PTE_TYPE_URX_SRX; + if (!user) pte |= PTE_TYPE_SR; + return pte; +} + +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) { + pte_t* sbi_pt = (pte_t*) pageTableStart; + memset(sbi_pt, 0, RISCV_PGSIZE); + // need to leave room for sbi page + uintptr_t memorySize = 0x7F000000; // 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE + + // middle page table + pte_t* middle_pt = (void*)sbi_pt + RISCV_PGSIZE; + size_t num_middle_pts = 2; // 3 level page table, 39 bit virtual address space for now + + // root page table + pte_t* root_pt = (void*)middle_pt + num_middle_pts * RISCV_PGSIZE; + memset(middle_pt, 0, (num_middle_pts + 1) * RISCV_PGSIZE); // 0's out middle_pt and root_pt + for (size_t i = 0; i < num_middle_pts; i++) + root_pt[(1<<RISCV_PGLEVEL_BITS)-num_middle_pts+i] = ptd_create(((uintptr_t)middle_pt >> RISCV_PGSHIFT) + i); + + // fill the middle page table + for (uintptr_t vaddr = virtMemStart, paddr = physMemStart; paddr < memorySize; vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) { + int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; + size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); + l2_idx += ((vaddr - virtMemStart) >> l2_shift); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + } + + // map SBI at top of vaddr space + uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + uintptr_t sbiStartAddress = 0x2000; // the start of the sbi mapping + uintptr_t sbiAddr = sbiStartAddress; + for (uintptr_t i = 0; i < num_sbi_pages; i++) { + uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbiAddr += RISCV_PGSIZE; + } + pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); + *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + + mb(); + root_page_table = root_pt; + write_csr(sptbr, root_pt); +} + +void initVirtualMemory(void) { + printk(BIOS_DEBUG, "Initializing virtual memory...\n"); + uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs + uintptr_t virtualStart = 0xffffffff81000000; + uintptr_t pageTableStart = 0x1f0000; + init_vm(virtualStart, physicalStart, pageTableStart); + mb(); + printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); + walk_page_table(); +} + +void mstatus_init(void) +{ + // supervisor support is required + + uintptr_t ms = 0; + ms = INSERT_FIELD(ms, MSTATUS_PRV, PRV_M); + ms = INSERT_FIELD(ms, MSTATUS_PRV1, PRV_S); + ms = INSERT_FIELD(ms, MSTATUS_PRV2, PRV_U); + ms = INSERT_FIELD(ms, MSTATUS_IE2, 1); + ms = INSERT_FIELD(ms, MSTATUS_VM, VM_CHOICE); + ms = INSERT_FIELD(ms, MSTATUS_FS, 3); + ms = INSERT_FIELD(ms, MSTATUS_XS, 3); + write_csr(mstatus, ms); + ms = read_csr(mstatus); + + if (EXTRACT_FIELD(ms, MSTATUS_VM) != VM_CHOICE) { + printk(BIOS_DEBUG, "we don't have virtual memory...\n"); + } else { + printk(BIOS_DEBUG, "-----------------------------\n"); + printk(BIOS_DEBUG, "virtual memory status enabled\n"); + printk(BIOS_DEBUG, "-----------------------------\n"); + } + + clear_csr(mip, MIP_MSIP); + set_csr(mie, MIP_MSIP); +}

1 0

← Newer
1
...
18
19
20
21
22
23
24
...
82
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2015