coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

New patch to review for coreboot: Braswell : Adding conditional statements to turn on/off DPTF WIFI and WWAN
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11411 -gerrit commit bb27dedcc4809d96a73cb056695d0c7902943b36 Author: Prince Agyeman <prince.agyeman(a)intel.com> Date: Wed Aug 5 20:17:38 2015 -0700 Braswell : Adding conditional statements to turn on/off DPTF WIFI and WWAN TEST=Builds and boot on Cyan verified by DPTF team BUG=None BRANCH=None Change-Id: I38ddf4a104eb3183d424b5df6b5eab9d406327ef Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 47cbf3893f7d5f1dfad73f57a71ade9382b0a06a Original-Change-Id: Ide4b3987bfa5e7ec60ee4f47d0663bb71f8330b9 Original-Signed-off-by: Prince Agyeman <prince.agyeman(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291063 Original-Commit-Queue: Prince Agyeman <popagy(a)gmail.com> Original-Tested-by: Prince Agyeman <popagy(a)gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/braswell/acpi/dptf/dptf.asl | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl index f8d8347..686a719 100644 --- a/src/soc/intel/braswell/acpi/dptf/dptf.asl +++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl @@ -1,4 +1,3 @@ - Device (DPTF) { Name (_HID, EISAID ("INT3400")) @@ -75,7 +74,12 @@ Device (DPTF) #include "charger.asl" #endif - /* Include Network Participants */ + /* Include Network Participants */ +#ifdef DPTF_ENABLE_WIFI #include "wifi.asl" +#endif + +#ifdef DPTF_ENABLE_WWAN #include "wwan.asl" +#endif }

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New patch to review for coreboot: braswell: remove CBFS_SIZE option in SoC directory
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11410 -gerrit commit 049547843c8d0f74469258caa618f8e47f09dccd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 13:30:03 2015 -0500 braswell: remove CBFS_SIZE option in SoC directory CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. BUG=chrome-os-partner:43419 BRANCH=None TEST=None Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175 Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289832 Original-Reviewed-by: Martin Roth <martinroth(a)google.com> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/braswell/Kconfig | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4f7ed6a..a3f6025 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -117,18 +117,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE the system will reset otherwise the ramstage will be reloaded from cbfs. -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x100000 - help - The firmware image has to store a lot more than just coreboot, - including: - - a firmware descriptor - - Intel Management Engine firmware - - MRC cache information - This option allows to limit the size of the CBFS portion in the - firmware image. - config LOCK_MANAGEMENT_ENGINE bool "Lock Management Engine section" default n

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New patch to review for coreboot: intel/braswell: fix build
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11409 -gerrit commit 5bf861302101f5e23b50dd2f17341e4a5e735976 Author: Jenny TC <jenny.tc(a)intel.com> Date: Thu Jun 18 14:02:00 2015 +0530 intel/braswell: fix build Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained additions to braswell's chip.h which were lost during merging. BRANCH=None BUG=None TEST=google/strago builds Change-Id: Ia1e4f8112aaa728ed69a60a87afd021bf2de68ac Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912 Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e Original-Original-Signed-off-by: Jenny TC <jenny.tc(a)intel.com> Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155 Original-Reviewed-on: https://chromium-review.googlesource.com/288880 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/soc/intel/braswell/chip.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 191fc01..90af83a 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -37,6 +37,9 @@ #define MEM_DDR3 0 #define MEM_LPDDR3 1 +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable;

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New patch to review for coreboot: cbgfx: coreboot graphics library
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11408 -gerrit commit 988579c139abc5aa0de08e5851d555b2a2c0b0d9 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Jul 29 16:03:52 2015 -0700 cbgfx: coreboot graphics library This change introduces cbgfx, a graphics library, which provides APIs for drawing basic shapes, texts, graphic data, etc. on a screen. BUG=chrome-os-partner:43444 BRANCH=tot TEST=Drew boxes by draw command of depthcharge cli on Samus Change-Id: I6019e5998e65dca3ab4785a90669b5db02463d2e Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 5b3ebce8eae91be742e4f977d3407d24e1537580 Original-Reviewed-on: https://chromium-review.googlesource.com/290301 Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Original-Change-Id: I10db27715cb907bdc451a33ed99d257e3af241b7 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291065 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/drivers/Makefile.inc | 3 + payloads/libpayload/drivers/video/graphics.c | 148 +++++++++++++++++++++++++++ payloads/libpayload/include/cbgfx.h | 66 ++++++++++++ payloads/libpayload/include/libpayload.h | 1 + 4 files changed, 218 insertions(+) diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 25ff4fe..083f122 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -68,6 +68,9 @@ libc-$(CONFIG_LP_GEODELX_VIDEO_CONSOLE) += video/font8x16.c libc-$(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) += video/corebootfb.c libc-$(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) += video/font8x16.c +# cbgfx: coreboot graphics library +libc-y += video/graphics.c + # AHCI/ATAPI driver libc-$(CONFIG_LP_STORAGE) += storage/storage.c libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c new file mode 100644 index 0000000..d9270a5 --- /dev/null +++ b/payloads/libpayload/drivers/video/graphics.c @@ -0,0 +1,148 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Google, Inc. + */ + +#include <libpayload.h> +#include <sysinfo.h> + +/* + * 'canvas' is the drawing area located in the center of the screen. It's a + * square area, stretching vertically to the edges of the screen, leaving + * non-drawing areas on the left and right. The screen is assumed to be + * landscape. + */ +static struct vector canvas; +static uint32_t canvas_offset; /* horizontal position of canvas */ + +/* + * Framebuffer is assumed to assign a higher coordinate (larger x, y) to + * a higher address + */ +static struct cb_framebuffer *fbinfo; +static uint8_t *fbaddr; + +static char initialized = 0; +#define LOG(x...) printf("CBGFX: " x) + +static void add_vectors(struct vector *out, + const struct vector *v1, const struct vector *v2) +{ + out->x = v1->x + v2->x; + out->y = v1->y + v2->y; +} + +static void to_canvas(const struct vector *relative, struct vector *absolute) +{ + absolute->x = canvas.width * relative->x / CANVAS_SCALE; + absolute->y = canvas.height * relative->y / CANVAS_SCALE; +} + +static int within_canvas(const struct vector *v) +{ + return v->x < canvas.width && v->y < canvas.height; +} + +static inline uint32_t calculate_color(const struct rgb_color *rgb) +{ + uint32_t color = 0; + color |= (rgb->red >> (8 - fbinfo->red_mask_size)) + << fbinfo->red_mask_pos; + color |= (rgb->green >> (8 - fbinfo->green_mask_size)) + << fbinfo->green_mask_pos; + color |= (rgb->blue >> (8 - fbinfo->blue_mask_size)) + << fbinfo->blue_mask_pos; + return color; +} + +/* + * Plot a pixel in a framebuffer. This is called from tight loops. Keep it slim + * and do the validation at callers' site. + */ +static inline void set_pixel(struct vector *coord, uint32_t color) +{ + const int bpp = fbinfo->bits_per_pixel; + int i; + uint8_t * const pixel = fbaddr + (coord->x + canvas_offset + + coord->y * fbinfo->x_resolution) * bpp / 8; + for (i = 0; i < bpp / 8; i++) + pixel[i] = (color >> (i * 8)); +} + +/* + * Initializes the library. Automatically called by APIs. It sets up + * the canvas and the framebuffer. + */ +static int cbgfx_init(void) +{ + if (initialized) + return 0; + + fbinfo = lib_sysinfo.framebuffer; + if (!fbinfo) + return -1; + + fbaddr = phys_to_virt((uint8_t *)(uintptr_t)(fbinfo->physical_address)); + if (!fbaddr) + return -1; + + /* calculate canvas size, assuming the screen is landscape */ + canvas.height = fbinfo->y_resolution; + canvas.width = canvas.height; + canvas_offset = (fbinfo->x_resolution - canvas.width) / 2; + if (canvas_offset < 0) { + LOG("Portrait screens are not supported\n"); + return -1; + } + + initialized = 1; + LOG("cbgfx initialized: canvas width=%d, height=%d, offset=%d\n", + canvas.width, canvas.height, canvas_offset); + + return 0; +} + +int draw_box(const struct vector *top_left_rel, + const struct vector *size_rel, + const struct rgb_color *rgb) +{ + struct vector top_left; + struct vector size; + struct vector p, t; + const uint32_t color = calculate_color(rgb); + + if (cbgfx_init()) + return CBGFX_ERROR_INIT; + + to_canvas(top_left_rel, &top_left); + to_canvas(size_rel, &size); + add_vectors(&t, &top_left, &size); + if (!within_canvas(&t)) { + LOG("Box exceeds canvas boundary\n"); + return CBGFX_ERROR_BOUNDARY; + } + + for (p.y = top_left.y; p.y < t.y; p.y++) + for (p.x = top_left.x; p.x < t.x; p.x++) + set_pixel(&p, color); + + return CBGFX_SUCCESS; +} + +int clear_canvas(struct rgb_color *rgb) +{ + const struct vector coord = { + .x = 0, + .y = 0, + }; + const struct vector size = { + .width = CANVAS_SCALE, + .height = CANVAS_SCALE, + }; + + if (cbgfx_init()) + return CBGFX_ERROR_INIT; + + return draw_box(&coord, &size, rgb); +} diff --git a/payloads/libpayload/include/cbgfx.h b/payloads/libpayload/include/cbgfx.h new file mode 100644 index 0000000..1f3e0b4 --- /dev/null +++ b/payloads/libpayload/include/cbgfx.h @@ -0,0 +1,66 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Google, Inc. + */ + +#include <stdint.h> + +/* + * API error codes + */ +#define CBGFX_SUCCESS 0 +/* unknown error */ +#define CBGFX_ERROR_UNKNOWN 1 +/* failed to initialize cbgfx library */ +#define CBGFX_ERROR_INIT 2 +/* drawing beyond canvas boundary */ +#define CBGFX_ERROR_BOUNDARY 3 + +struct vector { + union { + uint32_t x; + uint32_t width; + }; + union { + uint32_t y; + uint32_t height; + }; +}; + +struct rgb_color { + uint8_t red; + uint8_t green; + uint8_t blue; +}; + +/* + * Resolution of scale parameters used to describe height, width, coordinate, + * etc. relative to the canvas. For example, if it's 100, scales range from 0 to + * 100%. + */ +#define CANVAS_SCALE 100 + +/* + * The coordinate system is expected to have (0, 0) at top left corner with + * y values increasing towards bottom of screen. + */ + +/* + * draw a box filled with a color on screen + * + * top_left_rel: coordinate of top left corner of the box, relative to canvas. + * (0 - CANVAS_SCALE). + * size_rel: width and height of the box, relative to canvas. (0 - CANVAS_SCALE) + * rgb: RGB color of the box. + * + * return: CBGFX_* error codes + */ +int draw_box(const struct vector *top_left_rel, + const struct vector *size_rel, + const struct rgb_color *rgb); + +/* + * Clear the canvas + */ +int clear_canvas(struct rgb_color *rgb); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 3ae3590..538f2d8 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -44,6 +44,7 @@ #define _LIBPAYLOAD_H #include <libpayload-config.h> +#include <cbgfx.h> #include <ctype.h> #include <die.h> #include <endian.h>

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New patch to review for coreboot: video: add video_printf
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11407 -gerrit commit d99752ae9cf7fac8dc163be5651292f3fdca9707 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Jul 31 15:22:58 2015 -0700 video: add video_printf video_printf prints strings on the screen with specified foreground and background color. BUG=none BRANCH=smaug TEST=verified messages printed on Smaug Change-Id: I619625f7d4c5bc19cd9de64a0ba07899cf9ba289 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: e0ac4cb4c0d43b40f5c8f8f5a90eac45b0263b77 Original-Reviewed-on: https://chromium-review.googlesource.com/290130 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-(cherry picked from commit 75ea2c025d629c8fabc0cb859c4e8ab8ba6ce6e3) Original-Change-Id: Ief6d1fc820330b54f37ad9260cf3119853460b70 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290373 --- payloads/libpayload/drivers/video/video.c | 21 +++++++++++++++++++++ payloads/libpayload/include/libpayload.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c index 834a121..f183517 100644 --- a/payloads/libpayload/drivers/video/video.c +++ b/payloads/libpayload/drivers/video/video.c @@ -162,6 +162,27 @@ void video_console_putchar(unsigned int ch) video_console_fixup_cursor(); } +void video_printf(int foreground, int background, const char *fmt, ...) +{ + int i = 0, len; + char str[200]; + + va_list ap; + va_start(ap, fmt); + len = vsnprintf(str, ARRAY_SIZE(str), fmt, ap); + va_end(ap); + if (len <= 0) + return; + + foreground &= 0xf; + foreground <<= 8; + background &= 0xf; + background <<= 12; + + while (str[i]) + video_console_putchar(str[i++] | foreground | background); +} + void video_console_get_cursor(unsigned int *x, unsigned int *y, unsigned int *en) { *x=0; diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 5e787e1..3ae3590 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -206,6 +206,11 @@ void video_console_clear(void); void video_console_cursor_enable(int state); void video_console_get_cursor(unsigned int *x, unsigned int *y, unsigned int *en); void video_console_set_cursor(unsigned int cursorx, unsigned int cursory); +/* + * print characters on video console with colors. note that there is a size + * restriction for the internal buffer. so, output string can be truncated. + */ +void video_printf(int foreground, int background, const char *fmt, ...); /** @} */ /**

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Patch merged into coreboot/master: libpayload: x86: Add read/write{8, 16, 32} variants that match coreboot
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 5c25d0e8cc150e6be5f6e305ed9a98abab1a8e2f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 19 16:04:15 2015 -0700 libpayload: x86: Add read/write{8,16,32} variants that match coreboot Add the now coreboot standard MMIO read/write accessors that were already defined for other architectures but not x86. This leaves the old read/write{b,w,l} variants in place as was done on the other architectures, presumably to support old payloads that have not been updated. BUG=chrome-os-partner:43072 BRANCH=none TEST=emerge-glados libpayload CQ-DEPEND=CL:294711 Change-Id: I5ae3d755adcef0f6ff27aaa7c35a5b12ddc32e22 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: c09dd557050e3002fa5b8504980d72d4cb79a56c Original-Change-Id: I58d928338335d3fe4bb7fe2bdc9c2967d8689118 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294565 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11405 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See http://review.coreboot.org/11405 for details. -gerrit

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Patch merged into coreboot/master: libpayload: usb: dwc2: Always return 'size' transferred bytes for OUT
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit e8a8a00342b8791b3c29827b33139aa5722b3f61 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 17 18:47:18 2015 -0700 libpayload: usb: dwc2: Always return 'size' transferred bytes for OUT Seems like our transferred bytes calculation for OUT transfers that span more than one packet had been wrong, and we just got lucky that we never noticed it before. The HCTSIZ.xfersize register field we're reading only counts bytes transferred by the last packet we sent. OUT endpoints cannot have short transfers -- every transfer should either finish all bytes we wanted to send or end in a proper error condition. Therefore, in the absence of an error we can just conclude that all input bytes have been transferred. BRANCH=veyron BUG=chrome-os-partner:35525 TEST=SMSC95xx netboot on Jerry now works. Change-Id: I57349e697c428df6b56e2f6f62e87652ef1e7a94 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 0abee13b6d89dec12c6fff581ece1836393c7703 Original-Change-Id: Id0a127e6919f5786ba05218277705dda1067b8c3 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293956 Original-Reviewed-by: yunzhi li <lyz(a)rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/11404 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11404 for details. -gerrit

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Patch merged into coreboot/master: arm64: xcompile: Add support for A53 erratum 843419
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 4bfa29e94788df12c5845adeb8d5fb915db89541 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 20 14:36:34 2015 -0700 arm64: xcompile: Add support for A53 erratum 843419 This patch adds support to enable a linker workaround to a hardware erratum on some early Cortex-A53 revisions. Since the linker option was added very recently, we use xcompile to test whether the toolchain supports it first. It is also guarded by a Kconfig since only a few ARM64 SoCs will need this and it incurs a performance penalty. BRANCH=none BUG=none TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared in verbose make output accordingly. Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7 Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294745 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/11403 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> See http://review.coreboot.org/11403 for details. -gerrit

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Patch merged into coreboot/master: arm64: Fix 'verstage-objs: command not found' error
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 3d092303e399a388aeb483dbedc64cee5222ac8b Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Aug 10 11:17:14 2015 +0800 arm64: Fix 'verstage-objs: command not found' error Fix following compilation error. LINK cbfs/fallback/verstage.debug /bin/sh: verstage-objs: command not found /usr/x86_64-pc-linux-gnu/aarch64-cros-linux-gnu/binutils-bin/2.24/ld.bfd.real: warning: cannot find entry symbol stage_entry; defaulting to 00000000000d7000 BRANCH=chromeos-2015.07 BUG=none TEST=emerge-oak coreboot Change-Id: I30e4c43625b2d1d076f24e8c2639ce951839661b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2a8936cdf34d315f580819df682335b2998f044f Original-Change-Id: I9afd57a5a868a348dff2c66cad0a8a09cdb2e911 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292557 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/11402 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11402 for details. -gerrit

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Patch merged into coreboot/master: t210: sdram_lp0: also save EmcBctSpare2 field
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 3ad69e8d4c1270d037786d9f9fcb8c24ab6b267c Author: Yen Lin <yelin(a)nvidia.com> Date: Thu Aug 20 15:19:07 2015 -0700 t210: sdram_lp0: also save EmcBctSpare2 field Need to save EmcBctSpare2 field to scratch register. Without it, system may not resume from LP0 suspend. BUG=chrome-os-partner:43797 BRANCH=none TEST=able to suspend/resume >30 times on a known failed board Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 6d1623c4c791f79e097193dfbc4bc894ef63e230 Original-Change-Id: I53ebf8c4d4c7cd19827128a84fbd97a377d78ff7 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294765 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit ce38d902e889068d0068150c9352c2ecdb2f8815) Original-Reviewed-on: https://chromium-review.googlesource.com/294864 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I2ff21afbe9278413033101877c2581df51913709 Reviewed-on: http://review.coreboot.org/11401 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11401 for details. -gerrit

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coreboot-gerrit August 2015