coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: edid: add function to manually specify mode
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit e205410728d8c327a2264ff760eb0698eac030e8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 7 18:41:37 2015 -0700 edid: add function to manually specify mode This patch will let you to choose a favourite mode to display, while not just taking the edid detail timing. But not all modes are able to set, only modes that are in established or standard timing, and we only support a few common common resolutions for now. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=tested dev mode on Mickey at 640x480@60Hz Change-Id: I8a9dedfe08057d42d85b8ca129935a258cb26762 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 090583f90ff720d88e5cfe69fcb2d541c716f0e6 Original-Change-Id: Iaa8c9a6fad106ee792f7cd1a0ac77e3dcbadf481 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289671 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11390 for details. -gerrit

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Patch merged into coreboot/master: edid: Memset output earlier in decode_edid()
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 40e89b4e5a04aa515bcfec896db4f8d29519d4f5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 13 15:51:00 2015 -0700 edid: Memset output earlier in decode_edid() This ensures the output buffer is initialized before exiting decode_edid() so that if the return value is ignored in higher-level logic (like when dealing with external displays) we don't leave the struct filled with garbage. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=none Change-Id: I557e2495157458342db6d8b0b1ecb39f7267f61f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: bb12dca133576543efa4d3bcc9aadf85d37c8b71 Original-Change-Id: I697436fffadc7dd3af239436061975165a97ec8c Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293547 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11389 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11389 for details. -gerrit

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Patch merged into coreboot/master: edid: Use edid_mode struct to reduce redundancy
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 7dbf9c6747ccdfa8b993d3843a22722742957611 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jul 30 18:49:48 2015 -0700 edid: Use edid_mode struct to reduce redundancy This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11388 for details. -gerrit

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Patch merged into coreboot/master: edid: Clean-up the edid struct
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit a3b898aaf0ddf48fc3a577f4c39dd1d8acf31b6f Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Aug 2 18:07:48 2015 -0700 edid: Clean-up the edid struct There are serveral members of the edid struct which are never used outside of the EDID parsing code itself. This patch moves them to a struct in edid.c. They might be useful some day but until then we can just pretty print them and not pollute the more general API. BUG=none BRANCH=firmware-veyron TEST=compiled for veyron_mickey, peppy, link, nyan_big, rush, smaug Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I660f28c850163e89fe1f59d6c5cfd6e63a56dda0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: ee8ea314a0d8f5993508f560fc24ab17604049df Original-Change-Id: I7fb8674619c0b780cc64f3ab786286225a3fe0e2 Original-Reviewed-on: https://chromium-review.googlesource.com/290333 Original-Reviewed-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/11387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11387 for details. -gerrit

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Patch merged into coreboot/master: veyron: mickey sdram-lpddr3-samsung-2GB.inc now 40 Ohm
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit ffe63e27966e4c370262ba50f55dc50603165618 Author: Douglas Anderson <dianders(a)chromium.org> Date: Thu Aug 6 09:28:03 2015 -0700 veyron: mickey sdram-lpddr3-samsung-2GB.inc now 40 Ohm The value of 0x4 (60 Ohm) apperas to be causing lots of problems. Since 0x1 (34.3 Ohm) was _almost_ right, let's try 0x2 (40 Ohm) and hope it's the sweet spot. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 06db96e00d39972edbaf8429cbe88bbc66804e15 Original-Change-Id: If8b7d51d058ae000c0af189a648c62fa38a872ac Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291121 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-(cherry picked from commit 0dabadca1ab3bb310f85646d020bdcf672014071) Original-Reviewed-on: https://chromium-review.googlesource.com/291291 Change-Id: Id32790c894c09616e32503aa790fa294093eca8a Reviewed-on: http://review.coreboot.org/11386 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11386 for details. -gerrit

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Patch merged into coreboot/master: veyron_rialto: Force 3G modem off
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit bf62b8cc8b67843d4b7600e1544ccf4598f2136f Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Aug 5 14:13:34 2015 -0700 veyron_rialto: Force 3G modem off This basically does the same thing for firmware what CL:290631 did in the kernel. We want to keep the modem off until it needs to be used to avoid enumeration/detection issues. BUG=chrome-os-partner:43271 BRANCH=none TEST=needs testing Change-Id: I3b63a77c732dc4895b728b30f1dd71210a9c0e90 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a90ccd7fbffe44abe05e96341cc77067442c85e4 Original-Change-Id: I3516de1ea9160f7186ad7f5fb3b5d29ac73143b5 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290890 Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Reviewed-on: http://review.coreboot.org/11385 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11385 for details. -gerrit

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Patch merged into coreboot/master: T210: Add 128MB VPR allocation/carveout
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 50967870a9b0a55a5c973785803d7fe8921c1107 Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Aug 4 13:08:50 2015 -0700 T210: Add 128MB VPR allocation/carveout The NV security team requested that coreboot allocate a 128MB region in SDRAM for VPR (Video Protection Region). We had previously just disabled the VPR by setting BOM/SIZE to 0. Once allocated, the VPR will be locked from further access. The ALLOW_TZ_WRITE_ACCESS bit is _not_ set, as dynamic VPR config is not supported at this time (i.e. trusted code can _not_ remap or resize the VPR). BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the VPR region in the boot spew (ID:3 [f6800000 - fe800000]). Dumped the MC VideoProtect registers and verified their values. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a7481dba31dc39f482f8a7bfdaba1d1f4fc3cb81 Original-Change-Id: Ia19af485430bc09dbba28fcef5de16de851f81aa Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290475 Original-Reviewed-by: Hyung Taek Ryoo <hryoo(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Hridya Valsaraju <hvalsaraju(a)nvidia.com> Original-(cherry picked from commit 9629b318eb17b145315531509f950da02483114f) Original-Reviewed-on: https://chromium-review.googlesource.com/291095 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I19a93c915990644177c491c8212f2cf356d4d17d Reviewed-on: http://review.coreboot.org/11384 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11384 for details. -gerrit

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Patch merged into coreboot/master: t210: Move page tables to end of TZDRAM
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 8b3851969d6546ae920f52eb681631cd9b9aff46 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Aug 5 17:03:34 2015 -0700 t210: Move page tables to end of TZDRAM BL31 makes an assumption that TZDRAM always starts at its base. This was not true in our case since coreboot page tables were located towards the start of TZDRAM. Instead move page tables to the end, thus satisfying the assumption that BL31 base is the base of TZDRAM as well. BUG=chrome-os-partner:42989 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: aabed336da6e9aea426650c5ca5977ccfc83a21b Original-Change-Id: Ic4d155525dbb4baab95c971f77848e47d5d54dba Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291020 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit a57127f1655ef311b82c41ce33ffc71db5f9db35) Original-Reviewed-on: https://chromium-review.googlesource.com/290987 Change-Id: Ie7166fd0301b46eb32f44107f7f782c6d79a278c Reviewed-on: http://review.coreboot.org/11383 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11383 for details. -gerrit

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Patch merged into coreboot/master: t210: Pass in required BL31 parameters
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit f8142155f9938beda215a3e1991f8544b4b1d690 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Aug 5 17:05:26 2015 -0700 t210: Pass in required BL31 parameters BUG=chrome-os-partner:42989 BRANCH=None TEST=Compiles successfully and boots to kernel prompt. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: ff42f0b4e7f81ea97e571ec03adac16b412e4a37 Original-Change-Id: If78857abfb9a348433b8707e58bea1f58416d243 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291021 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit 68eeb4bb4b817184eb42f4ee3a840317ede07dae) Original-Reviewed-on: https://chromium-review.googlesource.com/290988 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: Id555198bc8e5d77f8ceee710d1a432516bd1ae4c Reviewed-on: http://review.coreboot.org/11382 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11382 for details. -gerrit

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Patch merged into coreboot/master: Smaug: Add NVDEC and TSEC carveouts
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 0bdb88b106ec65e3d1296d61545e09ecdab0794f Author: Tom Warren <twarren(a)nvidia.com> Date: Mon Aug 3 14:58:11 2015 -0700 Smaug: Add NVDEC and TSEC carveouts The NV security team requested that coreboot allocate the NVDEC and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB) and TSEC (2 regions, splitting 2MB), and set their lock bits. Kernel/trusted code should be able to use the regions now. Note that this change sets the UNLOCKED bit in Carveout1Cfg0 and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files (both 3GB and 4GB BCTs) so that the BOMs can be written. Any future revisions to these BCT files should take this into account. BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the carveout regions in the boot spew, and CBMEM living just below the last region (TSEC). Dumped the MC GeneralizedCarveoutX registers and verified their values (same as BCT, with only BOM/CFG0 changed). Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23 Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290452 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60) Original-Reviewed-on: https://chromium-review.googlesource.com/291081 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5 Reviewed-on: http://review.coreboot.org/11381 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11381 for details. -gerrit

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coreboot-gerrit August 2015