coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

New patch to review for coreboot: kunimitsu: add WP to gpio table
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11421 -gerrit commit 4037c2961287dea329181d509a991510c8bce547 Author: Wenkai Du <wenkai.du(a)intel.com> Date: Thu Aug 20 15:17:13 2015 -0700 kunimitsu: add WP to gpio table This is needed to fix error in depthcharge: src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up for flag 3. BUG=chrome-os-partner:44214 TEST=Verify depthcharge prints EC ID on boot up BRANCH=None Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3 Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68 Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294715 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/chromeos.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 4447a6c..6767705 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -39,6 +39,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->count = GPIO_COUNT; gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", get_recovery_mode_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",

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New patch to review for coreboot: glados: configure gpio pads prior to SiliconInit()
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11420 -gerrit commit 6af060fb18ac4ee584f8e991a07437648c1e5d8b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 20 13:06:56 2015 -0500 glados: configure gpio pads prior to SiliconInit() Move the gpio pad configuration prior to SiliconInit() in case there are dependencies of the pads being configured in prior to SiliconInit(). BUG=chrome-os-partner:43522 BUG=chrome-os-partner:43492 BRANCH=None TEST=Built and booted glados. Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9 Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294642 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/mainboard.c | 3 --- src/mainboard/google/glados/ramstage.c | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 61a5485..5e48f17 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -22,12 +22,9 @@ #include <device/device.h> #include <stdlib.h> #include "ec.h" -#include "gpio.h" static void mainboard_init(device_t dev) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC)) mainboard_ec_init(); } diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c index 8801380..4816fec 100644 --- a/src/mainboard/google/glados/ramstage.c +++ b/src/mainboard/google/glados/ramstage.c @@ -19,7 +19,11 @@ */ #include <soc/ramstage.h> +#include "gpio.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); }

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New patch to review for coreboot: glados: fix kepler probing
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11419 -gerrit commit 0d6a1641736f842f45445f87f346f74d43707607 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 20 12:18:08 2015 -0500 glados: fix kepler probing On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/gpio.h | 8 ++++++++ src/mainboard/google/glados/romstage.c | 11 +++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index c4d3d92..fb37b3b 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -48,6 +48,7 @@ #define EC_SMI_GPI GPP_E15 #ifndef __ACPI__ +/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), @@ -219,6 +220,13 @@ static const struct pad_config gpio_table[] = { /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* LANPHYC */ /* GPD11 */ }; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +}; + #endif #endif diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 4d9aaf4..36a8453 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -27,10 +27,21 @@ #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> +#include "gpio.h" #include "spd/spd.h" +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + void mainboard_romstage_entry(struct romstage_params *params) { + early_config_gpio(); + /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data);

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New patch to review for coreboot: glados: Export GPIO for EC_IN_RW
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11418 -gerrit commit 69a325873614010542bc031dae964318104ed93b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 20 09:54:18 2015 -0700 glados: Export GPIO for EC_IN_RW Export the proper GPIO for EC_IN_RW so it can be picked up and used by depthcharge/vboot. BUG=chrome-os-partner:43072 BRANCH=none TEST=build and boot on glados P2 Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56 Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294712 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/chromeos.c | 14 +++++++------- src/mainboard/google/glados/gpio.h | 3 +++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 13d0fce..dba1cbb 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -35,16 +35,11 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio *start_gpio = gpios->gpios; + struct lb_gpio *gpio = start_gpio; - gpio = gpios->gpios; fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", get_write_protect_state()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", @@ -55,6 +50,11 @@ void fill_lb_gpios(struct lb_gpios *gpios) get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW", + gpio_get(GPIO_EC_IN_RW)); + + gpios->count = gpio - start_gpio; + gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index fc5ffff..c4d3d92 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -23,6 +23,9 @@ #include <soc/gpe.h> #include <soc/gpio.h> +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + /* BIOS Flash Write Protect */ #define GPIO_PCH_WP GPP_C23

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New patch to review for coreboot: skylake: Fix RMT disable of saved training data
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11417 -gerrit commit d31e4d6f240b5a4148e4f1b3bdb95f99fa559107 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 19 11:03:59 2015 -0700 skylake: Fix RMT disable of saved training data The RMT flag that was attempting to disable saved training to force a full memory train was happening too late. In testing I was actually hitting a case where FSP was training every time but it was not because it was properly being told to. This moves the check of the RMT flag from devicetree to happen ealier, before it is actually consumed by romstage_common(). BUG=chrome-os-partner:40635 BRANCH=none TEST=do both power off+on and warm resets to ensure that FSP is doing a full memory train every time with RMT enabled. Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7 Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294177 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/pei_data.c | 14 ++++++++++++++ src/soc/intel/skylake/romstage/romstage.c | 7 +------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c index 47198a7..caee078 100644 --- a/src/soc/intel/skylake/pei_data.c +++ b/src/soc/intel/skylake/pei_data.c @@ -18,11 +18,15 @@ * Foundation, Inc. */ +#include <chip.h> #include <console/console.h> #include <console/streams.h> +#include <device/device.h> +#include <device/pci_def.h> #include <stdlib.h> #include <stdint.h> #include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/smm.h> @@ -34,6 +38,16 @@ static void ABI_X86 send_to_console(unsigned char b) void soc_fill_pei_data(struct pei_data *pei_data) { + const struct device *dev; + const struct soc_intel_skylake_config *config; + + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCH_DEVFN_LPC); + config = dev->chip_info; + pei_data->pei_version = PEI_VERSION; pei_data->tx_byte = &send_to_console; + + /* Force a full memory train if RMT is enabled */ + pei_data->disable_saved_data = config->Rmt; } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e9f0d42..91a496e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -103,12 +103,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->SataMode = config->SataMode; upd->EnableTraceHub = config->EnableTraceHub; upd->SaGv = config->SaGv; - - if (config->Rmt) { - upd->RMT = 1; - /* Force a full memory train if RMT is enabled */ - params->pei_data->disable_saved_data = 1; - } + upd->RMT = config->Rmt; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

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New patch to review for coreboot: skylake: mask off txstate before setting new gpio value
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11416 -gerrit commit 0396fcf3c76b8994b01bd6e50830eb23e9171c31 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 19 21:07:14 2015 -0500 skylake: mask off txstate before setting new gpio value The previously driven TX state of the buffer was not being cleared before or'ing in the new value. Fix this oversight. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Also dumped assembly and saw the masking happen. Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294541 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 5493cbd..3610a6c 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -383,6 +383,7 @@ void gpio_set(gpio_t gpio_num, int value) return; reg = read32(&dw_regs[0]); + reg &= ~PAD_FIELD(GPIOTXSTATE, MASK); reg |= PAD_FIELD_VAL(GPIOTXSTATE, value); write32(&dw_regs[0], reg); /* GPIO port ids support posted write semantics. */

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New patch to review for coreboot: Skylake: Cleanup Serial IO DMA channels
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11415 -gerrit commit 7eecd144d8e130c0f5230bf826563ad61c2f0c53 Author: Archana Patni <archana.patni(a)intel.com> Date: Tue Jul 28 18:43:13 2015 +0530 Skylake: Cleanup Serial IO DMA channels This patch removes FixedDMA channels carryover code from BDW as in SKL Integrated DMA is present for each serial io controller. BRANCH=None BUG=BUG=chrome-os-partner:40383 TEST=Build and Boot kunimitsu. Tested IDMA on UART. Change-Id: I66c869d310febcda430809d194b53a903a21fd99 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 833a1980329fb03cf487482e9276c076ede0a0fa Original-Change-Id: If6ce19cd8d60c727c8f2ffcd9bb232521df63f08 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293060 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/serialio.asl | 64 ++------------------------------- 1 file changed, 3 insertions(+), 61 deletions(-) diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index 62b83e0..c6f5446 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -99,12 +99,6 @@ Device (I2C0) { LPSS_I2C0_IRQ } }) - /* DMA channels are only used if Serial IO DMA controller is enabled */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx - }) Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -116,6 +110,7 @@ Device (I2C0) } Return (RBUF) } + Method (_STA, 0, NotSerialized) { If (LEqual (\S0EN, 0)) { @@ -155,14 +150,6 @@ Device (I2C1) { LPSS_I2C1_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx - }) Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -174,6 +161,7 @@ Device (I2C1) } Return (RBUF) } + Method (_STA, 0, NotSerialized) { If (LEqual (\S1EN, 0)) { @@ -212,15 +200,6 @@ Device (I2C2) { LPSS_I2C2_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -231,7 +210,6 @@ Device (I2C2) Store (SIO_BAR_LEN, B0LN) } - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } @@ -272,15 +250,6 @@ Device (I2C3) { LPSS_I2C3_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -291,7 +260,6 @@ Device (I2C3) Store (SIO_BAR_LEN, B0LN) } - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } @@ -333,15 +301,6 @@ Device (I2C4) { LPSS_I2C4_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS*/ @@ -352,9 +311,9 @@ Device (I2C4) Store (SIO_BAR_LEN, B0LN) } - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } + Method (_STA, 0, NotSerialized) { If (LEqual (\S4EN, 0)) { @@ -392,15 +351,6 @@ Device (I2C5) { LPSS_I2C5_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -409,8 +359,6 @@ Device (I2C5) Store (0xFE02A000, B0AD) Store (SIO_BAR_LEN, B0LN) - - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } @@ -496,12 +444,6 @@ Device (SPI1) { LPSS_SPI1_IRQ } }) - /* DMA channels are only used if Serial IO DMA controller is enabled */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x10, 0, Width32Bit, DMA1) /* Tx */ - FixedDMA (0x11, 1, Width32Bit, DMA2) /* Rx */ - }) Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */

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New patch to review for coreboot: skylake: Force full memory train if RMT is enabled
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11414 -gerrit commit 9f728355c685e4aac252bf54245573612c88f6f7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Aug 17 18:10:54 2015 -0700 skylake: Force full memory train if RMT is enabled RMT is useless if the memory does not do a full training pass, and since FSP does not seem to handle that case itself have coreboot not pass in a valid set of saved training data so FSP will do a full memory train. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot twice on glados with p2 and RMT enabled and see it do a full memory train on each boot. Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6 Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294067 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/romstage/romstage.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 91a496e..e9f0d42 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -103,7 +103,12 @@ void soc_memory_init_params(struct romstage_params *params, upd->SataMode = config->SataMode; upd->EnableTraceHub = config->EnableTraceHub; upd->SaGv = config->SaGv; - upd->RMT = config->Rmt; + + if (config->Rmt) { + upd->RMT = 1; + /* Force a full memory train if RMT is enabled */ + params->pei_data->disable_saved_data = 1; + } } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

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New patch to review for coreboot: fsp raminit: Add romstage_params to soc_memory_init_params
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11413 -gerrit commit 48827a7b6103450dc4d3e974cf95185ff85a04eb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Aug 17 18:09:14 2015 -0700 fsp raminit: Add romstage_params to soc_memory_init_params The SOC handler for memory init params is only taking UPD as an input which does not allow it to use romstage_params. In addition the UPD input is called params which is confusing so rename it to upd so romstage_params can be passed properly. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294066 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/braswell/romstage/romstage.c | 21 ++++++++--------- src/soc/intel/common/raminit.c | 6 +++-- src/soc/intel/common/romstage.h | 3 ++- src/soc/intel/skylake/romstage/romstage.c | 36 +++++++++++++++--------------- 4 files changed, 35 insertions(+), 31 deletions(-) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 64a3dee..1dbff54 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -203,7 +203,8 @@ void soc_after_ram_init(struct romstage_params *params) } /* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(MEMORY_INIT_UPD *params) +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) { const struct device *dev; const struct soc_intel_braswell_config *config; @@ -212,16 +213,16 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - params->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; - params->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; - params->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; - params->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; - params->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; - params->PcdApertureSize = config->PcdApertureSize; - params->PcdGttSize = config->PcdGttSize; - params->PcdLegacySegDecode = config->PcdLegacySegDecode; - params->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; + upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; + upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; + upd->PcdApertureSize = config->PcdApertureSize; + upd->PcdGttSize = config->PcdGttSize; + upd->PcdLegacySegDecode = config->PcdLegacySegDecode; + upd->PcdDvfsEnable = config->PcdDvfsEnable; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c index 69ae114..ddf5675 100644 --- a/src/soc/intel/common/raminit.c +++ b/src/soc/intel/common/raminit.c @@ -100,7 +100,7 @@ void raminit(struct romstage_params *params) fsp_memory_init_params.HobListPtr = &hob_list_ptr; /* Update the UPD data */ - soc_memory_init_params(&memory_init_params); + soc_memory_init_params(params, &memory_init_params); mainboard_memory_init_params(params, &memory_init_params); post_code(0x36); @@ -309,7 +309,9 @@ __attribute__((weak)) void soc_display_memory_init_params( } /* Initialize the UPD parameters for MemoryInit */ -__attribute__((weak)) void soc_memory_init_params(MEMORY_INIT_UPD *params) +__attribute__((weak)) void soc_memory_init_params( + struct romstage_params *params, + MEMORY_INIT_UPD *upd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index 403016e..440cad7 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -93,7 +93,8 @@ void soc_after_ram_init(struct romstage_params *params); void soc_after_temp_ram_exit(void); void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new); -void soc_memory_init_params(MEMORY_INIT_UPD *params); +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd); void soc_pre_console_init(struct romstage_params *params); void soc_pre_ram_init(struct romstage_params *params); void soc_romstage_init(struct romstage_params *params); diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2ce5ce3..91a496e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -77,33 +77,33 @@ int vboot_get_sw_write_protect(void) #endif /* UPD parameters to be initialized before MemoryInit */ -void soc_memory_init_params(MEMORY_INIT_UPD *params) +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) { const struct device *dev; const struct soc_intel_skylake_config *config; - /* Set the parameters for MemoryInit */ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; - memcpy(params->PcieRpEnable, config->PcieRpEnable, - sizeof(params->PcieRpEnable)); - memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, - sizeof(params->PcieRpClkReqSupport)); - memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, - sizeof(params->PcieRpClkReqNumber)); + memcpy(upd->PcieRpEnable, config->PcieRpEnable, + sizeof(upd->PcieRpEnable)); + memcpy(upd->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(upd->PcieRpClkReqSupport)); + memcpy(upd->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(upd->PcieRpClkReqNumber)); - params->MmioSize = 0x800; /* 2GB in MB */ - params->TsegSize = CONFIG_SMM_TSEG_SIZE; - params->IedSize = CONFIG_IED_REGION_SIZE; - params->ProbelessTrace = config->ProbelessTrace; - params->EnableLan = config->EnableLan; - params->EnableSata = config->EnableSata; - params->SataMode = config->SataMode; - params->EnableTraceHub = config->EnableTraceHub; - params->SaGv = config->SaGv; - params->RMT = config->Rmt; + upd->MmioSize = 0x800; /* 2GB in MB */ + upd->TsegSize = CONFIG_SMM_TSEG_SIZE; + upd->IedSize = CONFIG_IED_REGION_SIZE; + upd->ProbelessTrace = config->ProbelessTrace; + upd->EnableLan = config->EnableLan; + upd->EnableSata = config->EnableSata; + upd->SataMode = config->SataMode; + upd->EnableTraceHub = config->EnableTraceHub; + upd->SaGv = config->SaGv; + upd->RMT = config->Rmt; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

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New patch to review for coreboot: braswell: allow dirty cache line evictions for SMRAM to stick
by Patrick Georgi 28 Aug '15

28 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11412 -gerrit commit fbefce6503f48544e701d68dfaad1389e7c58075 Author: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Date: Tue Aug 11 14:09:46 2015 -0700 braswell: allow dirty cache line evictions for SMRAM to stick The BUNIT controls the policy for read/write access to physical memory. For the SMRAM range the policy was not allowing dirty evictions to the SMRAM when the core causing the eviction was not in SMM mode. This could happen when the SMM handler dirtied a line and then RSM'd back into non-SMM mode. The cache line was dirtied while in SMM mode, but when that particular cache line was evicted it would be silently dropped. Fix this by allowing the BUNIT to honor writes to the SMRAM range while the evicting core is not in SMM mode. The core SMRR msr provides the mechanism for disallowing general access to the SMRAM region while it is not in SMM mode. BUG=chrome-os-partner:43091 BRANCH=None TEST=Run suspend_stress_test and ensure there is no hang SMI handler on suspend-path. Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2 Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f Original-Reviewed-on: https://chromium-review.googlesource.com/292890 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/cpu.c | 10 ++++++++++ src/soc/intel/braswell/include/soc/iosf.h | 6 ++++++ 2 files changed, 16 insertions(+) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index e648ce0..2ab8725 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -30,6 +30,7 @@ #include <cpu/x86/smm.h> #include <soc/intel/common/memmap.h> #include <reg_script.h> +#include <soc/iosf.h> #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> @@ -86,6 +87,7 @@ void soc_init_cpus(device_t dev) const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; void *default_smm_area; + uint32_t bsmrwac; printk(BIOS_SPEW, "%s/%s ( %s )\n", __FILE__, __func__, dev_name(dev)); @@ -104,6 +106,14 @@ void soc_init_cpus(device_t dev) default_smm_area = backup_default_smm_area(); + /* + * Configure the BUNIT to allow dirty cache line evictions in non-SMM + * mode for the lines that were dirtied while in SMM mode. Otherwise + * the writes would be silently dropped. + */ + bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; + iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); + /* Set package MSRs */ reg_script_run(package_msr_script); diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index 1cdfb8f..cf56a05 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -131,9 +131,15 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define BUNIT_MMCONF_REG 0x27 #define BUNIT_BMISC 0x28 /* The SMMRR registers define the SMM region in MiB granularity. */ +#define BUNIT_SMRWAC 0x2d #define BUNIT_SMRRL 0x2e #define BUNIT_SMRRH 0x2f +/* SA ID bits. */ +#define SAI_IA_UNTRUSTED (1 << 0) +#define SAI_IA_SMM (1 << 2) +#define SAI_IA_BOOT (1 << 4) + /* * LPSS Registers */

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coreboot-gerrit August 2015