coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: veyron_rialto: remove spurious GPIO assignments
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 3746465f4a6eede5acf2dcd9f9713de2c2663f3b Author: Alexandru M Stan <amstan(a)chromium.org> Date: Thu Aug 20 11:45:26 2015 -0700 veyron_rialto: remove spurious GPIO assignments GPIO(0, B, 3) and GPIO(7, C, 5) are not actually connected, GPIO(0, B, 4) is named differently. BUG=chrome-os-partner:43031 TEST=Rialto should still boot just fine, USB should still work BRANCH=master Change-Id: I11879385de6e9b57ac28bcae699333beb5a0d64c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a66bf1fd73ff8d15d4ec1a8f3602465941285c32 Original-Change-Id: Ib7d2baa6ed1ab38db786eb4d5e77316ad72cbfd4 Original-Signed-off-by: Alexandru M Stan <amstan(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294713 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/11400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11400 for details. -gerrit

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Patch merged into coreboot/master: veyron: add Nanya NT5CC256M16DP sdram
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit cbd7de72a43dafe8c5761fee9426be97ae3d3734 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Aug 20 14:06:31 2015 +0800 veyron: add Nanya NT5CC256M16DP sdram BRANCH=None TEST=Boot from veyron BUG=None Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 6fe83821013954f0f2069598fd90a2d49de81101 Original-Change-Id: I68b105aa4bc3e82ef6a2421b127391e319c34d6e Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-(cherry picked from commit c115d9a3ea2ca1cb62b2a1ee75996d8adb991d5d) Original-jwerner: Added Minnie Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294763 Change-Id: I2bd6521c209db0e2d7d0bdb8ef2cde2715f321a6 Reviewed-on: http://review.coreboot.org/11399 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11399 for details. -gerrit

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Patch merged into coreboot/master: veyron_rialto: Turn on all leds
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit affb88b27140bfcdaf2a8cbd44b9ff90d6dee8d8 Author: Alexandru M Stan <amstan(a)chromium.org> Date: Mon Aug 17 17:32:06 2015 -0700 veyron_rialto: Turn on all leds Without this, the leds would be stuck to whatever the pullup/down states the pins come with on rk3288. Ready2_LED, an orange led, is one of the leds in this state. This might confuse some users thinking there's an error. Turn all of them on instead. Later on depthcharge will use the same LEDs to indicate dev mode status. BUG=chrome-os-partner:44274 BRANCH=master TEST=Boot firmware without anything else, note all leds on Change-Id: I5cf19aabd2a59a61699ef491ae11424cf5a0c874 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2e1a332a5653fb76bbf8fe624274ec64d2b443a5 Original-Change-Id: I4c4e8940dd9cf1ac0301ac00bfc5992ba16e1589 Original-Signed-off-by: Alexandru M Stan <amstan(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294065 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/11398 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11398 for details. -gerrit

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Patch merged into coreboot/master: edid: fix know_modes timing error
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit bedbdc4566097d599f296dbe741d7ff70bba6236 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Aug 18 04:18:09 2015 -0500 edid: fix know_modes timing error BRANCH=None BUG=chrome-os-partner:43789 TEST=Mickey board, 640x480@60Hz display normally Change-Id: Iea298302fe1124edbef157d1d81c12610402e9c7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 0209422efe52c45cab3c0d787b27352f63578e76 Original-Change-Id: Idf4c8cd9f2da3c5daa589973d831a506ff549b8b Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293994 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11397 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11397 for details. -gerrit

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Patch merged into coreboot/master: veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odt
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 274cde56cd7b0e1b93688966a9ee89bf17cda6e3 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Aug 13 10:52:52 2015 +0800 veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odt only modify the MR3 value, there will always be some mickey not working properly. After enable ODT, we use many mickey do tests, now functioning properly. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 681c169d59f5638d35b777eb2b7543e3b0dd90c8 Original-Change-Id: Ieb2b8a56054f91b6be81260e4c574425fb72fed3 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293324 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org> Original-Trybot-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-(cherry picked from commit 5397c2f32f5851b9f514b0bd2ae68999a77cabbf) Original-Reviewed-on: https://chromium-review.googlesource.com/294126 Change-Id: Icb3c839bebebfcae54fc6e96e9958c7020d49eff Reviewed-on: http://review.coreboot.org/11396 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11396 for details. -gerrit

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Patch merged into coreboot/master: arm64: declare do_dcsw_op as function
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 46502c9e374c30018773f09d0be78577cbcf3d0e Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Thu Aug 13 10:48:49 2015 +0800 arm64: declare do_dcsw_op as function do_dcsw_op is coded as a label, it's possible that linker will place do_dcsw_op on unaligned address. To avoid this situation, we declare do_dcsw_op as a function. Also explicitly set the 2nd argument of ENTRY_WITH_ALIGN(name, bits) to 2. do_dcsw_op: cbz x3, exit c103d: b40003e3 cbz x3, c10b9 <exit> mov x10, xzr c1041: aa1f03ea mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address BRANCH=none BUG=none TEST=build and check do_dcsw_op in elf file Change-Id: Ieb5f4188d6126ac9f6ddb0bfcc67452f79de94ad Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 4ee26b76089fab82cf4fb9b21c9f15b29e57b453 Original-Change-Id: Id331e8ecab7ea8782e97c10b13e8810955747a51 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: http://review.coreboot.org/11395 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11395 for details. -gerrit

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Patch merged into coreboot/master: t210: lp0_resume: apply mbist WAR for audio on resume
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 4cd0d2f5693093f442a51b4ebb97d30ce4403abd Author: Christopher Freeman <cfreeman(a)nvidia.com> Date: Fri Aug 14 15:11:26 2015 -0700 t210: lp0_resume: apply mbist WAR for audio on resume When power is cut/restored to audio block, mbist workaround must be reapplied or I2S will not function. Handle this in lp0 resume firmware with the rest of the mbist WAR. This sequence for audio is also present in boot block code for T210. BUG=chrome-os-partner:41249 BRANCH=None TEST=lp0 suspend/resume with audio playback Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 84933da8188f8263c19f38ba37e88e32ca46cb3d Original-Change-Id: Ia6432e8556ee64f528d94f2dc3279b152294e132 Original-Signed-off-by: Christopher Freeman <cfreeman(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293618 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Anatol Pomazau <anatol(a)google.com> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Anatol Pomazau <anatol(a)google.com> Original-Tested-by: Anatol Pomazau <anatol(a)google.com> Original-(cherry picked from commit 1e529c3e2ff929975fd654ef75396bc98d3b785c) Original-Reviewed-on: https://chromium-review.googlesource.com/293886 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I3e72bc10f7e2bea2fa5f946e25803a7928ce9276 Reviewed-on: http://review.coreboot.org/11394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11394 for details. -gerrit

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Patch merged into coreboot/master: rockchip: rk3288: multiple NPLL rate in pll_para_config
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 8c3ab6a5f1e36ddf2c22abacee47afaddd7d0bb8 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Mon Jul 27 08:50:36 2015 -0500 rockchip: rk3288: multiple NPLL rate in pll_para_config Due to HDMI need to set dclk_rate to 27Mhz, and we can't caclu a suitable config paramters for this rate, so we need to multiple rate unless the vco larger then VCO_MAX. When NPLL rate multiple to 54MHz, pll_para_config could caclu a right paramters, and I have verify the clock jitter is okay to HDMI output. Jitter Reports: Dclk Rate NPLL Rate nr/no/nf jitter Margin 27MHz 54MHz 2/10/45 449.0ps +51.0% BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, show right recovery picture on TV, and 480p clock jitter test passed Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c Original-Reviewed-on: https://chromium-review.googlesource.com/288416 Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290331 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/11393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11393 for details. -gerrit

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Patch merged into coreboot/master: rk3288: Set HDMI display mode to 480p
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 9a640597e698af45558be8bb7aaab6c3b6f28d39 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Wed Jul 29 08:54:14 2015 -0500 rk3288: Set HDMI display mode to 480p If an HDMI display is detected (EDID can be read), set the display mode to 480p. If for some reason 480p is not supported then we'll fall back to the automatically detected display mode. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=dev mode screen shows up on Mickey at 480p resolution Change-Id: I2c431eff6673392d3c09e1b66c66ba12ecc6eeb0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 76203a683c4501f368c50fe24101f68746ddb7f0 Original-Change-Id: I90dea37daa2d78628230d7d47f7ef0e917cbd7bb Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290554 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11392 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11392 for details. -gerrit

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Patch merged into coreboot/master: rk3288: Ignore EDID errors for HDMI
by gerrit＠coreboot.org 28 Aug '15

28 Aug '15

the following patch was just integrated into master: commit 04002a94f944037272e5946cc2233ba8dfcc423f Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 13 15:43:55 2015 -0700 rk3288: Ignore EDID errors for HDMI Assume that HDMI implies usage of an external display, and that we want to try bringing up display if we can read an EDID. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=none; need a display with corrupt EDID to test with Change-Id: I11cc61140d905d70798a7b46db7847f3a1b3c886 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: ace7773623eac57f068ecd50baa9108ce028cf1b Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I9e22984a98b1a5f8cd9645b92dc9b87e8d968f01 Original-Reviewed-on: https://chromium-review.googlesource.com/293548 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11391 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11391 for details. -gerrit

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coreboot-gerrit August 2015