coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch set updated for coreboot: arm64: Fix 'verstage-objs: command not found' error
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11402 -gerrit commit d36f64d4ebab058275b1e0c6adbe81b7ae0c31dd Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Aug 10 11:17:14 2015 +0800 arm64: Fix 'verstage-objs: command not found' error Fix following compilation error. LINK cbfs/fallback/verstage.debug /bin/sh: verstage-objs: command not found /usr/x86_64-pc-linux-gnu/aarch64-cros-linux-gnu/binutils-bin/2.24/ld.bfd.real: warning: cannot find entry symbol stage_entry; defaulting to 00000000000d7000 BRANCH=chromeos-2015.07 BUG=none TEST=emerge-oak coreboot Change-Id: I30e4c43625b2d1d076f24e8c2639ce951839661b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2a8936cdf34d315f580819df682335b2998f044f Original-Change-Id: I9afd57a5a868a348dff2c66cad0a8a09cdb2e911 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292557 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index e7ee84c..3e14f8b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -86,7 +86,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-y += boot.c verstage-y += div0.c

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Patch set updated for coreboot: arm64: xcompile: Add support for A53 erratum 843419
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11403 -gerrit commit ccafe1c3c106f89386cbbf0da7efd40826b62ec9 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 20 14:36:34 2015 -0700 arm64: xcompile: Add support for A53 erratum 843419 This patch adds support to enable a linker workaround to a hardware erratum on some early Cortex-A53 revisions. Since the linker option was added very recently, we use xcompile to test whether the toolchain supports it first. It is also guarded by a Kconfig since only a few ARM64 SoCs will need this and it incurs a performance penalty. BRANCH=none BUG=none TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared in verbose make output accordingly. Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7 Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294745 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/arch/arm64/Kconfig | 8 ++++++++ payloads/libpayload/bin/lpgcc | 6 ++++++ src/arch/arm64/Kconfig | 9 +++++++++ util/xcompile/xcompile | 20 ++++++++++++++++++++ 4 files changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/arm64/Kconfig b/payloads/libpayload/arch/arm64/Kconfig index d2f8e56..a28a1f2 100644 --- a/payloads/libpayload/arch/arm64/Kconfig +++ b/payloads/libpayload/arch/arm64/Kconfig @@ -33,6 +33,14 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN +config ARM64_A53_ERRATUM_843419 + bool "Enable Cortex-A53 erratum 843419 linker workaround" + default n + help + Some early Cortex-A53 revisions had a hardware bug that results in + incorrect address calculations in rare cases. This option enables a + linker workaround to avoid those cases if your toolchain supports it. + config DMA_LIM_EXCL hex "DMA address limit(exclusive) in MiB units" default 0x1000 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 17d8eda..8d0260b 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -181,6 +181,12 @@ else echo "Could not find head.o" exit 1 fi + + if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config && + grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then + _LDFLAGS+=" -Wl,--fix-cortex-a53-843419" + fi + if [ $DEBUGME -eq 1 ]; then echo "$DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC" fi diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index b7cdc12..f2adf5c 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -55,3 +55,12 @@ config ARM64_SECURE_OS_FILE depends on ARM64_USE_SECURE_OS help Secure OS binary file. + +config ARM64_A53_ERRATUM_843419 + bool + default n + help + Some early Cortex-A53 revisions had a hardware bug that results in + incorrect address calculations in rare cases. This option enables a + linker workaround to avoid those cases if your toolchain supports it. + Should be selected automatically by SoCs that are affected. diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index e712ac3..46a30d1 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -87,6 +87,18 @@ testcc() { $1 -nostdlib -Werror $2 -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 } +testld() { + local gcc="$1" + local cflags="$2" + local ld="$3" + local ldflags="$4" + local tmp_o="$TMPFILE.o" + local tmp_elf="$TMPFILE.elf" + rm -f "$tmp_elf" + testcc $1 $2 && + $3 -nostdlib -static $4 -o "$tmp_elf" "$tmp_o" >/dev/null 2>&1 +} + testas() { local gccprefix="$1" local twidth="$2" @@ -163,6 +175,11 @@ detect_special_flags() { ;; x64) ;; + arm64) + testld "$GCC" "$CFLAGS_GCC" "${GCCPREFIX}ld${LINKER_SUFFIX}" \ + "$LDFLAGS --fix-cortex-a53-843419" && \ + LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419" + ;; mipsel) testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \ CFLAGS_GCC+=" -mno-abicalls -fno-pic" @@ -203,6 +220,9 @@ endif CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} +ifeq (\$(CONFIG_ARM64_A53_ERRATUM_843419)\$(CONFIG_LP_ARM64_A53_ERRATUM_843419),y) +LD_${TARCH}+=${LDFLAGS_ARM64_A53_ERRATUM_843419} +endif NM_${TARCH}:=${GCCPREFIX}nm OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy OBJDUMP_${TARCH}:=${GCCPREFIX}objdump

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Patch set updated for coreboot: veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odt
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11396 -gerrit commit 01f9fb2b72246a04789cb4e5f38e7a96f11bb8c3 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Aug 13 10:52:52 2015 +0800 veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odt only modify the MR3 value, there will always be some mickey not working properly. After enable ODT, we use many mickey do tests, now functioning properly. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 681c169d59f5638d35b777eb2b7543e3b0dd90c8 Original-Change-Id: Ieb2b8a56054f91b6be81260e4c574425fb72fed3 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293324 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org> Original-Trybot-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-(cherry picked from commit 5397c2f32f5851b9f514b0bd2ae68999a77cabbf) Original-Reviewed-on: https://chromium-review.googlesource.com/294126 Change-Id: Icb3c839bebebfcae54fc6e96e9958c7020d49eff --- .../google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc index 666b12f..89dfd69 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -75,5 +75,5 @@ .dramtype = LPDDR3, .num_channels = 2, .stride = 9, - .odt = 0, + .odt = 1, },

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Patch set updated for coreboot: edid: fix know_modes timing error
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11397 -gerrit commit 9eacc5debd460a28dc8e04955d73dbacfb4b2602 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Aug 18 04:18:09 2015 -0500 edid: fix know_modes timing error BRANCH=None BUG=chrome-os-partner:43789 TEST=Mickey board, 640x480@60Hz display normally Change-Id: Iea298302fe1124edbef157d1d81c12610402e9c7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 0209422efe52c45cab3c0d787b27352f63578e76 Original-Change-Id: Idf4c8cd9f2da3c5daa589973d831a506ff549b8b Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293994 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index be3d906..68cc38a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -987,22 +987,22 @@ static void dump_breakdown(unsigned char *edid) static struct edid_mode known_modes[NUM_KNOWN_MODES] = { [EDID_MODE_640x480_60Hz] = { .name = "640x480@60Hz", .pixel_clock = 25175, .refresh = 60, - .ha = 640, .hbl = 160, .hso = 16, .hborder = 96, + .ha = 640, .hbl = 160, .hso = 16, .hspw = 96, .va = 480, .vbl = 45, .vso = 10, .vspw = 2, .phsync = '-', .pvsync = '-' }, [EDID_MODE_720x480_60Hz] = { .name = "720x480@60Hz", .pixel_clock = 27000, .refresh = 60, - .ha = 720, .hbl = 78, .hso = 16, .hborder = 62, + .ha = 720, .hbl = 138, .hso = 16, .hspw = 62, .va = 480, .vbl = 45, .vso = 9, .vspw = 6, .phsync = '-', .pvsync = '-' }, [EDID_MODE_1280x720_60Hz] = { .name = "1280x720@60Hz", .pixel_clock = 74250, .refresh = 60, - .ha = 1280, .hbl = 370, .hso = 110, .hborder = 40, + .ha = 1280, .hbl = 370, .hso = 110, .hspw = 40, .va = 720, .vbl = 30, .vso = 5, .vspw = 20, .phsync = '+', .pvsync = '+' }, [EDID_MODE_1920x1080_60Hz] = { .name = "1920x1080@60Hz", .pixel_clock = 148500, .refresh = 60, - .ha = 1920, .hbl = 280, .hso = 88, .hborder = 44, + .ha = 1920, .hbl = 280, .hso = 88, .hspw = 44, .va = 1080, .vbl = 45, .vso = 4, .vspw = 5, .phsync = '+', .pvsync = '+' }, };

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Patch set updated for coreboot: veyron_rialto: Turn on all leds
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11398 -gerrit commit 05466895ba0f80fabad974dd45f8021151a428d2 Author: Alexandru M Stan <amstan(a)chromium.org> Date: Mon Aug 17 17:32:06 2015 -0700 veyron_rialto: Turn on all leds Without this, the leds would be stuck to whatever the pullup/down states the pins come with on rk3288. Ready2_LED, an orange led, is one of the leds in this state. This might confuse some users thinking there's an error. Turn all of them on instead. Later on depthcharge will use the same LEDs to indicate dev mode status. BUG=chrome-os-partner:44274 BRANCH=master TEST=Boot firmware without anything else, note all leds on Change-Id: I5cf19aabd2a59a61699ef491ae11424cf5a0c874 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2e1a332a5653fb76bbf8fe624274ec64d2b443a5 Original-Change-Id: I4c4e8940dd9cf1ac0301ac00bfc5992ba16e1589 Original-Signed-off-by: Alexandru M Stan <amstan(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294065 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/veyron_rialto/bootblock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 849bc95..38ae277 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -48,6 +48,12 @@ void bootblock_mainboard_init(void) if (rkclk_was_watchdog_reset()) reboot_from_watchdog(); + /* Turn on all leds */ + gpio_output(GPIO(7, A, 0), 1); /* LED_READY */ + gpio_output(GPIO(7, B, 5), 1); /* Ready2_LED */ + gpio_output(GPIO(7, B, 3), 1); /* LED_SYNCING */ + gpio_output(GPIO(7, B, 7), 1); /* LED_ERROR */ + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);

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Patch set updated for coreboot: veyron: add Nanya NT5CC256M16DP sdram
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11399 -gerrit commit 88f1e4e512c07640d98ff15bcc3212efcf71f547 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Aug 20 14:06:31 2015 +0800 veyron: add Nanya NT5CC256M16DP sdram BRANCH=None TEST=Boot from veyron BUG=None Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 6fe83821013954f0f2069598fd90a2d49de81101 Original-Change-Id: I68b105aa4bc3e82ef6a2421b127391e319c34d6e Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-(cherry picked from commit c115d9a3ea2ca1cb62b2a1ee75996d8adb991d5d) Original-jwerner: Added Minnie Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294763 Change-Id: I2bd6521c209db0e2d7d0bdb8ef2cde2715f321a6 --- src/mainboard/google/veyron_brain/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_danger/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_jerry/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_mickey/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_mighty/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_minnie/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_pinky/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_romy/sdram_configs.c | 2 +- .../veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_shark/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_speedy/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ 20 files changed, 790 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/veyron_brain/sdram_configs.c b/src/mainboard/google/veyron_brain/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_brain/sdram_configs.c +++ b/src/mainboard/google/veyron_brain/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_danger/sdram_configs.c b/src/mainboard/google/veyron_danger/sdram_configs.c index d7db069..84ceba5 100644 --- a/src/mainboard/google/veyron_danger/sdram_configs.c +++ b/src/mainboard/google/veyron_danger/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_jerry/sdram_configs.c +++ b/src/mainboard/google/veyron_jerry/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mighty/sdram_configs.c b/src/mainboard/google/veyron_mighty/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_mighty/sdram_configs.c +++ b/src/mainboard/google/veyron_mighty/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_minnie/sdram_configs.c b/src/mainboard/google/veyron_minnie/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_minnie/sdram_configs.c +++ b/src/mainboard/google/veyron_minnie/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_romy/sdram_configs.c +++ b/src/mainboard/google/veyron_romy/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_shark/sdram_configs.c b/src/mainboard/google/veyron_shark/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_shark/sdram_configs.c +++ b/src/mainboard/google/veyron_shark/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_speedy/sdram_configs.c +++ b/src/mainboard/google/veyron_speedy/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +},

1 0

Patch set updated for coreboot: rk3288: Set HDMI display mode to 480p
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11392 -gerrit commit 60600e5ce9d301ef28014d5affd86f46c059fd03 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Wed Jul 29 08:54:14 2015 -0500 rk3288: Set HDMI display mode to 480p If an HDMI display is detected (EDID can be read), set the display mode to 480p. If for some reason 480p is not supported then we'll fall back to the automatically detected display mode. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=dev mode screen shows up on Mickey at 480p resolution Change-Id: I2c431eff6673392d3c09e1b66c66ba12ecc6eeb0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 76203a683c4501f368c50fe24101f68746ddb7f0 Original-Change-Id: I90dea37daa2d78628230d7d47f7ef0e917cbd7bb Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290554 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/hdmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index e5bebe3..a520399 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -793,6 +793,10 @@ int rk_hdmi_get_edid(struct edid *edid) if (decode_edid(edid_buf, edid_size, edid)) hdmi_debug("failed to decode edid.\n"); + /* Try 480p for best compatibility. */ + if (set_display_mode(edid, EDID_MODE_640x480_60Hz)) + hdmi_debug("failed to set mode to 640x480@60Hz\n"); + return 0; }

1 0

Patch set updated for coreboot: rockchip: rk3288: multiple NPLL rate in pll_para_config
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11393 -gerrit commit d667ed7848c80f2bf6982fbd527bdcdd2ece79e2 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Mon Jul 27 08:50:36 2015 -0500 rockchip: rk3288: multiple NPLL rate in pll_para_config Due to HDMI need to set dclk_rate to 27Mhz, and we can't caclu a suitable config paramters for this rate, so we need to multiple rate unless the vco larger then VCO_MAX. When NPLL rate multiple to 54MHz, pll_para_config could caclu a right paramters, and I have verify the clock jitter is okay to HDMI output. Jitter Reports: Dclk Rate NPLL Rate nr/no/nf jitter Margin 27MHz 54MHz 2/10/45 449.0ps +51.0% BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, show right recovery picture on TV, and 480p clock jitter test passed Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c Original-Reviewed-on: https://chromium-review.googlesource.com/288416 Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290331 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 878c194..e4d2e3e 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -498,7 +498,7 @@ void rkclk_configure_tsadc(unsigned int hz) RK_CLRSETBITS(0x3f << 0, (div - 1) << 0)); } -static int pll_para_config(u32 freq_hz, struct pll_div *div) +static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div) { u32 ref_khz = OSC_HZ / KHz, nr, nf = 0; u32 fref_khz; @@ -512,17 +512,27 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) printk(BIOS_ERR, "%s: the frequency can not be 0 Hz\n", __func__); return -1; } + no = div_round_up(VCO_MIN_KHZ, freq_khz); + if (ext_div) { + *ext_div = div_round_up(no, max_no); + no = div_round_up(no, *ext_div); + } /* only even divisors (and 1) are supported */ if (no > 1) no = div_round_up(no, 2) * 2; + vco_khz = freq_khz * no; + if (ext_div) + vco_khz *= *ext_div; + if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { printk(BIOS_ERR, "%s: Cannot find out a supported VCO" " for Frequency (%uHz).\n", __func__, freq_hz); return -1; } + div->no = no; best_diff_khz = vco_khz; @@ -608,8 +618,9 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) { struct pll_div npll_config = {0}; + u32 lcdc_div; - if (pll_para_config(dclk_hz, &npll_config)) + if (pll_para_config(dclk_hz, &npll_config, &lcdc_div)) return -1; /* npll enter slow-mode */ @@ -633,12 +644,14 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) switch (vop_id) { case 0: write32(&cru_ptr->cru_clksel_con[27], - RK_CLRSETBITS(0xff << 8 | 3 << 0, 0 << 8 | 2 << 0)); + RK_CLRSETBITS(0xff << 8 | 3 << 0, + (lcdc_div - 1) << 8 | 2 << 0)); break; case 1: write32(&cru_ptr->cru_clksel_con[29], - RK_CLRSETBITS(0xff << 8 | 3 << 6, 0 << 8 | 2 << 6)); + RK_CLRSETBITS(0xff << 8 | 3 << 6, + (lcdc_div - 1) << 8 | 2 << 6)); break; } return 0;

1 0

Patch set updated for coreboot: t210: lp0_resume: apply mbist WAR for audio on resume
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11394 -gerrit commit 10cf2b0535e62246b2c32b1e0b21a0f751bd7fee Author: Christopher Freeman <cfreeman(a)nvidia.com> Date: Fri Aug 14 15:11:26 2015 -0700 t210: lp0_resume: apply mbist WAR for audio on resume When power is cut/restored to audio block, mbist workaround must be reapplied or I2S will not function. Handle this in lp0 resume firmware with the rest of the mbist WAR. This sequence for audio is also present in boot block code for T210. BUG=chrome-os-partner:41249 BRANCH=None TEST=lp0 suspend/resume with audio playback Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 84933da8188f8263c19f38ba37e88e32ca46cb3d Original-Change-Id: Ia6432e8556ee64f528d94f2dc3279b152294e132 Original-Signed-off-by: Christopher Freeman <cfreeman(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293618 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Anatol Pomazau <anatol(a)google.com> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Anatol Pomazau <anatol(a)google.com> Original-Tested-by: Anatol Pomazau <anatol(a)google.com> Original-(cherry picked from commit 1e529c3e2ff929975fd654ef75396bc98d3b785c) Original-Reviewed-on: https://chromium-review.googlesource.com/293886 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I3e72bc10f7e2bea2fa5f946e25803a7928ce9276 --- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 69 ++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 5ef03d0..956e8c5 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -31,7 +31,8 @@ enum { MC_CTLR_BASE = 0x70019000, FUSE_BASE = 0x7000F800, EMC_BASE = 0x7001B000, - I2C5_BASE = 0x7000D000 + I2C5_BASE = 0x7000D000, + I2S_BASE = 0x702d1000 }; /* UP tag registers. */ @@ -704,15 +705,77 @@ static void set_pmacro_training_wrptr(void) write32(pmacro_cfg_pm_global, ENABLE_CFG_BYTES); } +static uint32_t *i2s_0_master = (void *)(I2S_BASE + 0x0a0); +static uint32_t *i2s_1_master = (void *)(I2S_BASE + 0x1a0); +static uint32_t *i2s_2_master = (void *)(I2S_BASE + 0x2a0); +static uint32_t *i2s_3_master = (void *)(I2S_BASE + 0x3a0); +static uint32_t *i2s_4_master = (void *)(I2S_BASE + 0x4a0); + +static uint32_t *i2s_0_slcg = (void *)(I2S_BASE + 0x088); +static uint32_t *i2s_1_slcg = (void *)(I2S_BASE + 0x188); +static uint32_t *i2s_2_slcg = (void *)(I2S_BASE + 0x288); +static uint32_t *i2s_3_slcg = (void *)(I2S_BASE + 0x388); +static uint32_t *i2s_4_slcg = (void *)(I2S_BASE + 0x488); + +static uint32_t *clk_rst_ape_clear = (void *)(CLK_RST_BASE + 0x2ac); +static uint32_t *clk_rst_ape_set = (void *)(CLK_RST_BASE + 0x2a8); + static void mbist_workaround(void) { uint32_t clks_to_be_cleared; + uint32_t i2s_read; + + write32(clk_rst_ape_clear, 0x40); + udelay(2); + + i2s_read = read32(i2s_0_master); + i2s_read |= 0x400; + write32(i2s_0_master, i2s_read); + + i2s_read = read32(i2s_0_slcg); + i2s_read &= ~1; + write32(i2s_0_slcg, i2s_read); + + i2s_read = read32(i2s_1_master); + i2s_read |= 0x400; + write32(i2s_1_master, i2s_read); + + i2s_read = read32(i2s_1_slcg); + i2s_read &= ~1; + write32(i2s_1_slcg, i2s_read); + + i2s_read = read32(i2s_2_master); + i2s_read |= 0x400; + write32(i2s_2_master, i2s_read); + + i2s_read = read32(i2s_2_slcg); + i2s_read &= ~1; + write32(i2s_2_slcg, i2s_read); + + i2s_read = read32(i2s_3_master); + i2s_read |= 0x400; + write32(i2s_3_master, i2s_read); + + i2s_read = read32(i2s_3_slcg); + i2s_read &= ~1; + write32(i2s_3_slcg, i2s_read); + + i2s_read = read32(i2s_4_master); + i2s_read |= 0x400; + write32(i2s_4_master, i2s_read); + + i2s_read = read32(i2s_4_slcg); + i2s_read &= ~1; + write32(i2s_4_slcg, i2s_read); + + udelay(2); write32(clk_rst_lvl2_clk_gate_ovra_ptr, 0); write32(clk_rst_lvl2_clk_gate_ovrb_ptr, 0); - write32(clk_rst_lvl2_clk_gate_ovrc_ptr, 0); + write32(clk_rst_lvl2_clk_gate_ovrc_ptr, 0x00000002); write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */ - write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0); + write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0x00000c00); + clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr); clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0;

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Patch set updated for coreboot: arm64: declare do_dcsw_op as function
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11395 -gerrit commit 09f03e9cbb1017e4df020ae41bcdbc57199b52e3 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Thu Aug 13 10:48:49 2015 +0800 arm64: declare do_dcsw_op as function do_dcsw_op is coded as a label, it's possible that linker will place do_dcsw_op on unaligned address. To avoid this situation, we declare do_dcsw_op as a function. Also explicitly set the 2nd argument of ENTRY_WITH_ALIGN(name, bits) to 2. do_dcsw_op: cbz x3, exit c103d: b40003e3 cbz x3, c10b9 <exit> mov x10, xzr c1041: aa1f03ea mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address BRANCH=none BUG=none TEST=build and check do_dcsw_op in elf file Change-Id: Ieb5f4188d6126ac9f6ddb0bfcc67452f79de94ad Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 4ee26b76089fab82cf4fb9b21c9f15b29e57b453 Original-Change-Id: Id331e8ecab7ea8782e97c10b13e8810955747a51 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> --- src/arch/arm64/armv8/cache_helpers.S | 3 ++- src/arch/arm64/include/arch/asm.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/armv8/cache_helpers.S b/src/arch/arm64/armv8/cache_helpers.S index dc74dad..b94bc30 100644 --- a/src/arch/arm64/armv8/cache_helpers.S +++ b/src/arch/arm64/armv8/cache_helpers.S @@ -54,7 +54,7 @@ b do_dcsw_op .endm -do_dcsw_op: +ENTRY(do_dcsw_op) cbz x3, exit mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address @@ -92,6 +92,7 @@ level_done: isb exit: ret +ENDPROC(do_dcsw_op) .macro dcsw_loop _op loop2_\_op: diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index 851f3f9..878509e 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -30,7 +30,7 @@ .align bits; \ name: -#define ENTRY(name) ENTRY_WITH_ALIGN(name, 0) +#define ENTRY(name) ENTRY_WITH_ALIGN(name, 2) #define END(name) \ .size name, .-name

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coreboot-gerrit August 2015