coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch set updated for coreboot: t210: Pass in required BL31 parameters
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11382 -gerrit commit 3fc82e61d99d8cbaeb9822b9fdd37a5728ad3838 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Aug 5 17:05:26 2015 -0700 t210: Pass in required BL31 parameters BUG=chrome-os-partner:42989 BRANCH=None TEST=Compiles successfully and boots to kernel prompt. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: ff42f0b4e7f81ea97e571ec03adac16b412e4a37 Original-Change-Id: If78857abfb9a348433b8707e58bea1f58416d243 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291021 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit 68eeb4bb4b817184eb42f4ee3a840317ede07dae) Original-Reviewed-on: https://chromium-review.googlesource.com/290988 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: Id555198bc8e5d77f8ceee710d1a432516bd1ae4c --- src/soc/nvidia/tegra210/Makefile.inc | 1 + src/soc/nvidia/tegra210/arm_tf.c | 47 ++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 2d5bf58..0593f06 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -75,6 +75,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c ramstage-y += sdram_lp0.c ramstage-y += soc.c diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c new file mode 100644 index 0000000..56aa4ac --- /dev/null +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arm_tf.h> +#include <assert.h> +#include <soc/addressmap.h> +#include <stdlib.h> +#include <string.h> +#include <symbols.h> + +typedef struct bl31_plat_params { + uint32_t tzdram_size; +} bl31_plat_params_t; + +static bl31_plat_params_t t210_plat_params; + +void *soc_get_bl31_plat_params(bl31_params_t *params) +{ + uintptr_t tz_base_mib; + size_t tz_size_mib; + + carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); + + assert(tz_size_mib < 4096); + t210_plat_params.tzdram_size = tz_size_mib * MiB; + + dcache_clean_by_mva(&t210_plat_params, sizeof(t210_plat_params)); + + return &t210_plat_params; +}

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Patch set updated for coreboot: t210: Move page tables to end of TZDRAM
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11383 -gerrit commit f300ea8b7f3cebc51891a1268fb5039da0499b50 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Aug 5 17:03:34 2015 -0700 t210: Move page tables to end of TZDRAM BL31 makes an assumption that TZDRAM always starts at its base. This was not true in our case since coreboot page tables were located towards the start of TZDRAM. Instead move page tables to the end, thus satisfying the assumption that BL31 base is the base of TZDRAM as well. BUG=chrome-os-partner:42989 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: aabed336da6e9aea426650c5ca5977ccfc83a21b Original-Change-Id: Ic4d155525dbb4baab95c971f77848e47d5d54dba Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291020 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit a57127f1655ef311b82c41ce33ffc71db5f9db35) Original-Reviewed-on: https://chromium-review.googlesource.com/290987 Change-Id: Ie7166fd0301b46eb32f44107f7f782c6d79a278c --- src/soc/nvidia/tegra210/Makefile.inc | 9 +++----- src/soc/nvidia/tegra210/mmu_operations.c | 35 +++++++++++++++++++++++++++++--- 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 0593f06..fb38d38 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -161,14 +161,11 @@ endif # BL31 component is placed towards the end of 32-bit address space. This assumes # that TrustZone memory is placed at the end of 32-bit address space. Within the -# TZ memory, we place TTB at the beginning and then remaining space can be used -# up by BL31 and secure OS. Calculate TZDRAM_BASE i.e. base of BL31 component -# by: +# TZ memory, we place BL31 and BL32(if available) towards the beginning and TTB +# towards the end. Calculate TZDRAM_BASE i.e. base of BL31 component by: # 0x1000 = end of 32-bit address space in MiB # 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB -# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB) -# = skip TTB buffer and get base address of BL31 -BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)) << 20)) +BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) << 20)) BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210 # MTC fw diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index dd7437c..5578933 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -18,6 +18,7 @@ */ #include <arch/mmu.h> +#include <assert.h> #include <memrange.h> #include <soc/addressmap.h> #include <soc/mmu_operations.h> @@ -69,15 +70,43 @@ void tegra210_mmu_init(void) { uintptr_t tz_base_mib; size_t tz_size_mib; + uintptr_t ttb_base_mib; size_t ttb_size_mib; struct memranges *map = &t210_mmap_ranges; tegra210_memrange_init(map); mainboard_add_memory_ranges(map); - /* Place page tables at the base of the trust zone region. */ + /* + * Place page tables at the end of the trust zone region. + * TZDRAM layout is as follows: + * + * +--------------------------+ <----+DRAM_END + * | | + * | | + * | | + * +--------------------------+ <----+0x100000000 + * | | + * | coreboot page tables | + * +--------------------------+ + * | | + * | BL32 | + * +--------------------------+ + * | | + * | BL31 | + * +--------------------------+ <----+TZDRAM_BASE + * | | + * | | + * | | + * | | + * +--------------------------+ <----+DRAM_BASE + * + */ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); - tz_base_mib *= MiB; + + assert(tz_size_mib > CONFIG_TTB_SIZE_MB); + ttb_base_mib = (tz_base_mib + tz_size_mib - CONFIG_TTB_SIZE_MB) * MiB; + ttb_size_mib = CONFIG_TTB_SIZE_MB * MiB; - mmu_init(map, (void *)tz_base_mib, ttb_size_mib); + mmu_init(map, (void *)ttb_base_mib, ttb_size_mib); mmu_enable(); }

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Patch set updated for coreboot: rockchip: rk3288: fix phsync & pvsync bug
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11380 -gerrit commit dc4192ed4076d9c1ee83710eb812d87dfda6a48f Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Jul 21 22:47:55 2015 -0500 rockchip: rk3288: fix phsync & pvsync bug Struct edid defien pvsync & phsync as an character, like '+' or '-', so we need to check sync polarity by comparing with characters '+' and '-' instead of treating as boolean. BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, light monitor normally Change-Id: I92d233e19b6df8917fb8ff9a327ccb842c152d65 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2d22d4b6e7108474f67200e0fb1e4894cd88db85 Original-Change-Id: I14c72aa8994227092a1059d2b25c1dd2249b9db1 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/289963 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/rockchip/rk3288/hdmi.c | 4 ++-- src/soc/rockchip/rk3288/vop.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index c9cc232..582c834 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -494,11 +494,11 @@ static void hdmi_av_composer(const struct edid *edid) /* set up hdmi_fc_invidconf */ inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE; - inv_val |= (edid->pvsync ? + inv_val |= ((edid->pvsync == '+') ? HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); - inv_val |= (edid->phsync ? + inv_val |= ((edid->phsync == '+') ? HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c index 8c69321..30b73c2 100644 --- a/src/soc/rockchip/rk3288/vop.c +++ b/src/soc/rockchip/rk3288/vop.c @@ -125,8 +125,8 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, V_DSP_OUT_MODE(15) | - V_DSP_HSYNC_POL(!!edid->phsync) | - V_DSP_VSYNC_POL(!!edid->pvsync)); + V_DSP_HSYNC_POL(edid->phsync == '+') | + V_DSP_VSYNC_POL(edid->pvsync == '+')); write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));

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Patch set updated for coreboot: Smaug: Add NVDEC and TSEC carveouts
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11381 -gerrit commit d13b5aa4a219bdac0f119f41617b05e9234435c1 Author: Tom Warren <twarren(a)nvidia.com> Date: Mon Aug 3 14:58:11 2015 -0700 Smaug: Add NVDEC and TSEC carveouts The NV security team requested that coreboot allocate the NVDEC and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB) and TSEC (2 regions, splitting 2MB), and set their lock bits. Kernel/trusted code should be able to use the regions now. Note that this change sets the UNLOCKED bit in Carveout1Cfg0 and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files (both 3GB and 4GB BCTs) so that the BOMs can be written. Any future revisions to these BCT files should take this into account. BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the carveout regions in the boot spew, and CBMEM living just below the last region (TSEC). Dumped the MC GeneralizedCarveoutX registers and verified their values (same as BCT, with only BOM/CFG0 changed). Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23 Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290452 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60) Original-Reviewed-on: https://chromium-review.googlesource.com/291081 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5 --- .../google/smaug/bct/sdram-samsung-3GB-204.inc | 4 +- .../google/smaug/bct/sdram-samsung-4GB-204.inc | 4 +- src/soc/nvidia/tegra210/addressmap.c | 68 +++++++++++++++++++++- src/soc/nvidia/tegra210/include/soc/addressmap.h | 8 ++- src/soc/nvidia/tegra210/romstage.c | 3 + 5 files changed, 81 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc b/src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc index 745bb51..1f88c6b 100644 --- a/src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc +++ b/src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc @@ -450,7 +450,7 @@ .McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000, .McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000, .McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000, - .McGeneralizedCarveout4Cfg0 = 0x04002442, + .McGeneralizedCarveout4Cfg0 = 0x04002440, .McGeneralizedCarveout5Bom = 0x00000000, .McGeneralizedCarveout5BomHi = 0x00000000, .McGeneralizedCarveout5Size128kb = 0x00000008, @@ -464,7 +464,7 @@ .McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000, .McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000, .McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000, - .McGeneralizedCarveout5Cfg0 = 0x04002c42, + .McGeneralizedCarveout5Cfg0 = 0x04002c40, .EmcCaTrainingEnable = 0x00000000, .SwizzleRankByteEncode = 0x0000002e, .BootRomPatchControl = 0x00000000, diff --git a/src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc b/src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc index 2e7142e..7eb0c69 100644 --- a/src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc +++ b/src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc @@ -450,7 +450,7 @@ .McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000, .McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000, .McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000, - .McGeneralizedCarveout4Cfg0 = 0x04002442, + .McGeneralizedCarveout4Cfg0 = 0x04002440, .McGeneralizedCarveout5Bom = 0x00000000, .McGeneralizedCarveout5BomHi = 0x00000000, .McGeneralizedCarveout5Size128kb = 0x00000008, @@ -464,7 +464,7 @@ .McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000, .McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000, .McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000, - .McGeneralizedCarveout5Cfg0 = 0x04002c42, + .McGeneralizedCarveout5Cfg0 = 0x04002c40, .EmcCaTrainingEnable = 0x00000000, .SwizzleRankByteEncode = 0x0000002e, .BootRomPatchControl = 0x00000000, diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index 6e14d4a..ddf3f99 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -106,6 +106,31 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) read32(&mc->security_carveout2_bom_hi), region_size_mb); break; + case CARVEOUT_NVDEC: + /* These carveout regs use 128KB granularity - convert to MB */ + region_size_mb = DIV_ROUND_UP(read32(&mc->security_carveout1_size_128kb), 8); + + /* BOM address set in nvdec_region_init, below */ + carveout_from_regs(base_mib, size_mib, + read32(&mc->security_carveout1_bom), + read32(&mc->security_carveout1_bom_hi), + region_size_mb); + break; + case CARVEOUT_TSEC: + /* These carveout regs use 128KB granularity - convert to MB */ + region_size_mb = DIV_ROUND_UP(read32(&mc->security_carveout4_size_128kb), 8); + + /* BOM address set in tsec_region_init, below. + * Since the TSEC region consumes 2 carveouts, and is + * expected to be split evenly between the two, size_mib + * is doubled here. + */ + region_size_mb *= 2; + carveout_from_regs(base_mib, size_mib, + read32(&mc->security_carveout4_bom), + read32(&mc->security_carveout4_bom_hi), + region_size_mb); + break; default: break; } @@ -182,7 +207,6 @@ static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib, continue; carveout_range(i, &carveout_base, &carveout_size); - if (carveout_size == 0) continue; @@ -281,3 +305,45 @@ void gpu_region_init(void) /* Set the locked bit. This will lock out any other writes! */ setbits_le32(&mc->security_carveout3_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } + +void nvdec_region_init(void) +{ + struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; + uintptr_t nvdec_base_mib = 0, end = 4096; + size_t nvdec_size_mib = NVDEC_CARVEOUT_SIZE_MB; + + /* Get memory layout below 4GiB */ + memory_in_range(&nvdec_base_mib, &end, CARVEOUT_NVDEC); + nvdec_base_mib = end - nvdec_size_mib; + + /* Set the carveout1 base address. Everything else has been set in the BCT cfg/inc */ + write32(&mc->security_carveout1_bom, nvdec_base_mib << 20); + write32(&mc->security_carveout1_bom_hi, 0); + + /* Set the locked bit. This will lock out any other writes! */ + setbits_le32(&mc->security_carveout1_cfg0, MC_SECURITY_CARVEOUT_LOCKED); +} + +void tsec_region_init(void) +{ + struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; + uintptr_t tsec_base_mib = 0, end = 4096; + size_t tsec_size_mib = TSEC_CARVEOUT_SIZE_MB; + + /* Get memory layout below 4GiB */ + memory_in_range(&tsec_base_mib, &end, CARVEOUT_TSEC); + tsec_base_mib = end - tsec_size_mib; + + /* + * Set the carveout4/5 base address. Everything else has been set in the BCT cfg/inc + * Note that the TSEC range is split evenly between the 2 carveouts (i.e. 1MB each) + */ + write32(&mc->security_carveout4_bom, tsec_base_mib << 20); + write32(&mc->security_carveout4_bom_hi, 0); + write32(&mc->security_carveout5_bom, (tsec_base_mib + (TSEC_CARVEOUT_SIZE_MB / 2)) << 20); + write32(&mc->security_carveout5_bom_hi, 0); + + /* Set the locked bit. This will lock out any other writes! */ + setbits_le32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits_le32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED); +} diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index c3af00c..b9bec18 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -104,7 +104,9 @@ enum { TEGRA_I2C_BASE_COUNT = 6, }; -#define GPU_CARVEOUT_SIZE_MB 1 +#define GPU_CARVEOUT_SIZE_MB 1 +#define NVDEC_CARVEOUT_SIZE_MB 1 +#define TSEC_CARVEOUT_SIZE_MB 2 /* Return total size of DRAM memory configured on the platform. */ int sdram_size_mb(void); @@ -119,6 +121,8 @@ enum { CARVEOUT_MTS, CARVEOUT_VPR, CARVEOUT_GPU, + CARVEOUT_NVDEC, + CARVEOUT_TSEC, CARVEOUT_NUM, }; @@ -142,5 +146,7 @@ void mainboard_add_memory_ranges(struct memranges *map); */ void trustzone_region_init(void); void gpu_region_init(void); +void nvdec_region_init(void); +void tsec_region_init(void); #endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index c029e93..d8d191b 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -67,7 +67,10 @@ void romstage(void) */ trustzone_region_init(); + /* Now do various other carveouts */ gpu_region_init(); + nvdec_region_init(); + tsec_region_init(); /* * When romstage is running it's always on the reboot path -- never a

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Patch set updated for coreboot: veyron: mickey sdram-lpddr3-samsung-2GB.inc now 40 Ohm
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11386 -gerrit commit db95416b8dd6768b1dc739a30729c1bdb79533ed Author: Douglas Anderson <dianders(a)chromium.org> Date: Thu Aug 6 09:28:03 2015 -0700 veyron: mickey sdram-lpddr3-samsung-2GB.inc now 40 Ohm The value of 0x4 (60 Ohm) apperas to be causing lots of problems. Since 0x1 (34.3 Ohm) was _almost_ right, let's try 0x2 (40 Ohm) and hope it's the sweet spot. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 06db96e00d39972edbaf8429cbe88bbc66804e15 Original-Change-Id: If8b7d51d058ae000c0af189a648c62fa38a872ac Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291121 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-(cherry picked from commit 0dabadca1ab3bb310f85646d020bdcf672014071) Original-Reviewed-on: https://chromium-review.googlesource.com/291291 Change-Id: Id32790c894c09616e32503aa790fa294093eca8a --- .../google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc index cc39f62..666b12f 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -65,8 +65,8 @@ .mr[0] = 0x0, .mr[1] = 0xC3, .mr[2] = 0x6, - /* 60Ohms instead of 34.3 due to bad PCB routing on Mickey. */ - .mr[3] = 0x4 + /* 40 Ohms instead of 34.3 due to bad PCB routing on Mickey. */ + .mr[3] = 0x2 }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6,

1 0

Patch set updated for coreboot: edid: Clean-up the edid struct
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11387 -gerrit commit 742f55b5717c6b2d5b07567f671281d3fcdea854 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Aug 2 18:07:48 2015 -0700 edid: Clean-up the edid struct There are serveral members of the edid struct which are never used outside of the EDID parsing code itself. This patch moves them to a struct in edid.c. They might be useful some day but until then we can just pretty print them and not pollute the more general API. BUG=none BRANCH=firmware-veyron TEST=compiled for veyron_mickey, peppy, link, nyan_big, rush, smaug Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I660f28c850163e89fe1f59d6c5cfd6e63a56dda0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: ee8ea314a0d8f5993508f560fc24ab17604049df Original-Change-Id: I7fb8674619c0b780cc64f3ab786286225a3fe0e2 Original-Reviewed-on: https://chromium-review.googlesource.com/290333 Original-Reviewed-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/edid.h | 24 ----------- src/lib/edid.c | 123 +++++++++++++++++++++++++++++++---------------------- 2 files changed, 71 insertions(+), 76 deletions(-) diff --git a/src/include/edid.h b/src/include/edid.h index f775177..1422c1e 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -27,14 +27,6 @@ */ struct edid { - char manuf_name[4]; - unsigned int model; - unsigned int serial; - unsigned int year; - unsigned int week; - unsigned int version[2]; - unsigned int nonconformant; - unsigned int type; /* These next three things used to all be called bpp. * Merriment ensued. The identifier * 'bpp' is herewith banished from our @@ -56,17 +48,9 @@ struct edid { * all over the place. */ unsigned int panel_bits_per_pixel; - unsigned int xres; - unsigned int yres; - unsigned int voltage; - unsigned int sync; - unsigned int xsize_cm; - unsigned int ysize_cm; /* used to compute timing for graphics chips. */ unsigned char phsync; unsigned char pvsync; - unsigned int x_mm; - unsigned int y_mm; unsigned int pixel_clock; unsigned int link_clock; unsigned int ha; @@ -87,14 +71,6 @@ struct edid { u32 x_resolution; u32 y_resolution; u32 bytes_per_line; - /* it is unlikely we need these things. */ - /* if one of these is non-zero, use that one. */ - /* they're aspect * 10 to provide some additional resolution */ - unsigned int aspect_landscape; - unsigned int aspect_portrait; - const char *range_class; - const char *syncmethod; - const char *stereo; }; /* Defined in src/lib/edid.c */ diff --git a/src/lib/edid.c b/src/lib/edid.c index db0f412..e08535d 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -68,20 +68,43 @@ struct edid_context { int conformant; }; +/* Stuff that isn't used anywhere but is nice to pretty-print while + we're decoding everything else. */ +static struct { + char manuf_name[4]; + unsigned int model; + unsigned int serial; + unsigned int year; + unsigned int week; + unsigned int version[2]; + unsigned int nonconformant; + unsigned int type; + + unsigned int x_mm; + unsigned int y_mm; + + unsigned int voltage; + unsigned int sync; + + const char *syncmethod; + const char *range_class; + const char *stereo; +} extra_info; + static int vbe_valid; static struct lb_framebuffer edid_fb; -static char *manufacturer_name(struct edid *out, unsigned char *x) +static char *manufacturer_name(unsigned char *x) { - out->manuf_name[0] = ((x[0] & 0x7C) >> 2) + '@'; - out->manuf_name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; - out->manuf_name[2] = (x[1] & 0x1F) + '@'; - out->manuf_name[3] = 0; + extra_info.manuf_name[0] = ((x[0] & 0x7C) >> 2) + '@'; + extra_info.manuf_name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; + extra_info.manuf_name[2] = (x[1] & 0x1F) + '@'; + extra_info.manuf_name[3] = 0; - if (isupper(out->manuf_name[0]) && - isupper(out->manuf_name[1]) && - isupper(out->manuf_name[2])) - return out->manuf_name; + if (isupper(extra_info.manuf_name[0]) && + isupper(extra_info.manuf_name[1]) && + isupper(extra_info.manuf_name[2])) + return extra_info.manuf_name; return NULL; } @@ -258,7 +281,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, int v_max_offset = 0, v_min_offset = 0; int is_cvt = 0; c->has_range_descriptor = 1; - out->range_class = ""; + extra_info.range_class = ""; /* * XXX todo: implement feature flags, vtd blocks * XXX check: ranges are well-formed; block termination if no vtd @@ -285,25 +308,25 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, */ switch (x[10]) { case 0x00: /* default gtf */ - out->range_class = "GTF"; + extra_info.range_class = "GTF"; break; case 0x01: /* range limits only */ - out->range_class = "bare limits"; + extra_info.range_class = "bare limits"; if (!c->claims_one_point_four) c->has_valid_range_descriptor = 0; break; case 0x02: /* secondary gtf curve */ - out->range_class = "GTF with icing"; + extra_info.range_class = "GTF with icing"; break; case 0x04: /* cvt */ - out->range_class = "CVT"; + extra_info.range_class = "CVT"; is_cvt = 1; if (!c->claims_one_point_four) c->has_valid_range_descriptor = 0; break; default: /* invalid */ c->has_valid_range_descriptor = 0; - out->range_class = "invalid"; + extra_info.range_class = "invalid"; break; } @@ -312,7 +335,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, if (x[7] + h_min_offset > x[8] + h_max_offset) c->has_valid_range_descriptor = 0; printk(BIOS_SPEW, "Monitor ranges (%s): %d-%dHz V, %d-%dkHz H", - out->range_class, + extra_info.range_class, x[5] + v_min_offset, x[6] + v_max_offset, x[7] + h_min_offset, x[8] + h_max_offset); if (x[9]) @@ -423,8 +446,8 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, if (! c->did_detailed_timing){ /* Edid contains pixel clock in terms of 10KHz */ out->pixel_clock = (x[0] + (x[1] << 8)) * 10; - out->x_mm = (x[12] + ((x[14] & 0xF0) << 4)); - out->y_mm = (x[13] + ((x[14] & 0x0F) << 8)); + extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); + extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8)); out->ha = (x[2] + ((x[4] & 0xF0) << 4)); out->hbl = (x[3] + ((x[4] & 0x0F) << 8)); out->hso = (x[8] + ((x[11] & 0xC0) << 2)); @@ -464,41 +487,41 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, c->did_detailed_timing = 1; switch ((x[17] & 0x18) >> 3) { case 0x00: - out->syncmethod = " analog composite"; + extra_info.syncmethod = " analog composite"; break; case 0x01: - out->syncmethod = " bipolar analog composite"; + extra_info.syncmethod = " bipolar analog composite"; break; case 0x02: - out->syncmethod = " digital composite"; + extra_info.syncmethod = " digital composite"; break; case 0x03: - out->syncmethod = ""; + extra_info.syncmethod = ""; break; } out->pvsync = (x[17] & (1 << 2)) ? '+' : '-'; out->phsync = (x[17] & (1 << 1)) ? '+' : '-'; switch (x[17] & 0x61) { case 0x20: - out->stereo = "field sequential L/R"; + extra_info.stereo = "field sequential L/R"; break; case 0x40: - out->stereo = "field sequential R/L"; + extra_info.stereo = "field sequential R/L"; break; case 0x21: - out->stereo = "interleaved right even"; + extra_info.stereo = "interleaved right even"; break; case 0x41: - out->stereo = "interleaved left even"; + extra_info.stereo = "interleaved left even"; break; case 0x60: - out->stereo = "four way interleaved"; + extra_info.stereo = "four way interleaved"; break; case 0x61: - out->stereo = "side by side interleaved"; + extra_info.stereo = "side by side interleaved"; break; default: - out->stereo = ""; + extra_info.stereo = ""; break; } @@ -507,16 +530,16 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, " %04x %04x %04x %04x vborder %x\n" " %chsync %cvsync%s%s %s\n", out->pixel_clock, - out->x_mm, - out->y_mm, + extra_info.x_mm, + extra_info.y_mm, out->ha, out->ha + out->hso, out->ha + out->hso + out->hspw, out->ha + out->hbl, out->hborder, out->va, out->va + out->vso, out->va + out->vso + out->vspw, out->va + out->vbl, out->vborder, out->phsync, out->pvsync, - out->syncmethod, x[17] & 0x80 ?" interlaced" : "", - out->stereo - ); + extra_info.syncmethod, x[17] & 0x80 ?" interlaced" : "", + extra_info.stereo + ); return 1; } @@ -983,15 +1006,15 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) } memset(out, 0, sizeof(*out)); - if (manufacturer_name(out, edid + 0x08)) + if (manufacturer_name(edid + 0x08)) c.manufacturer_name_well_formed = 1; - out->model = (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)); - out->serial = (unsigned int)(edid[0x0C] + (edid[0x0D] << 8) + extra_info.model = (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)); + extra_info.serial = (unsigned int)(edid[0x0C] + (edid[0x0D] << 8) + (edid[0x0E] << 16) + (edid[0x0F] << 24)); printk(BIOS_SPEW, "Manufacturer: %s Model %x Serial Number %u\n", - out->manuf_name, + extra_info.manuf_name, (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)), (unsigned int)(edid[0x0C] + (edid[0x0D] << 8) + (edid[0x0E] << 16) + (edid[0x0F] << 24))); @@ -1004,24 +1027,24 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) c.has_valid_year = 1; printk(BIOS_SPEW, "Made week %hhd of model year %hhd\n", edid[0x10], edid[0x11]); - out->week = edid[0x10]; - out->year = edid[0x11]; + extra_info.week = edid[0x10]; + extra_info.year = edid[0x11]; } else { /* we know it's at least 2013, when this code was written */ if (edid[0x11] + 90 <= 2013) { c.has_valid_year = 1; printk(BIOS_SPEW, "Made week %hhd of %d\n", edid[0x10], edid[0x11] + 1990); - out->week = edid[0x10]; - out->year = edid[0x11] + 1990; + extra_info.week = edid[0x10]; + extra_info.year = edid[0x11] + 1990; } } } } printk(BIOS_SPEW, "EDID version: %hhd.%hhd\n", edid[0x12], edid[0x13]); - out->version[0] = edid[0x12]; - out->version[1] = edid[0x13]; + extra_info.version[0] = edid[0x12]; + extra_info.version[1] = edid[0x13]; if (edid[0x12] == 1) { if (edid[0x13] > 4) { @@ -1068,7 +1091,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) default: c.nonconformant_digital_display = 1; } - out->type = edid[0x14] & 0x0f; + extra_info.type = edid[0x14] & 0x0f; } else if (c.claims_one_point_two) { conformance_mask = 0x7E; if (edid[0x14] & 0x01) { @@ -1079,13 +1102,13 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (!c.nonconformant_digital_display) c.nonconformant_digital_display = edid[0x14] & conformance_mask; - out->nonconformant = c.nonconformant_digital_display; + extra_info.nonconformant = c.nonconformant_digital_display; } else { analog = 1; int voltage = (edid[0x14] & 0x60) >> 5; int sync = (edid[0x14] & 0x0F); - out->voltage = voltage; - out->sync = sync; + extra_info.voltage = voltage; + extra_info.sync = sync; printk(BIOS_SPEW, "Analog display, Input voltage level: %s V\n", voltage == 3 ? "0.7/0.7" : @@ -1117,19 +1140,15 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (edid[0x15] && edid[0x16]) { printk(BIOS_SPEW, "Maximum image size: %d cm x %d cm\n", edid[0x15], edid[0x16]); - out->xsize_cm = edid[0x15]; - out->ysize_cm = edid[0x16]; } else if (c.claims_one_point_four && (edid[0x15] || edid[0x16])) { if (edid[0x15]) { /* edid[0x15] != 0 && edid[0x16] == 0 */ unsigned int ratio = 100000/(edid[0x15] + 99); printk(BIOS_SPEW, "Aspect ratio is %u.%03u (landscape)\n", ratio / 1000, ratio % 1000); - out->aspect_landscape = ratio / 100; } else { /* edid[0x15] == 0 && edid[0x16] != 0 */ unsigned int ratio = 100000/(edid[0x16] + 99); printk(BIOS_SPEW, "Aspect ratio is %u.%03u (portrait)\n", ratio / 1000, ratio % 1000); - out->aspect_portrait = ratio / 100; } } else { /* Either or both can be zero for 1.3 and before */

1 0

Patch set updated for coreboot: T210: Add 128MB VPR allocation/carveout
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11384 -gerrit commit 98ebbebc64a0417f47cf20b53b9d494d8c8adccc Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Aug 4 13:08:50 2015 -0700 T210: Add 128MB VPR allocation/carveout The NV security team requested that coreboot allocate a 128MB region in SDRAM for VPR (Video Protection Region). We had previously just disabled the VPR by setting BOM/SIZE to 0. Once allocated, the VPR will be locked from further access. The ALLOW_TZ_WRITE_ACCESS bit is _not_ set, as dynamic VPR config is not supported at this time (i.e. trusted code can _not_ remap or resize the VPR). BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the VPR region in the boot spew (ID:3 [f6800000 - fe800000]). Dumped the MC VideoProtect registers and verified their values. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a7481dba31dc39f482f8a7bfdaba1d1f4fc3cb81 Original-Change-Id: Ia19af485430bc09dbba28fcef5de16de851f81aa Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290475 Original-Reviewed-by: Hyung Taek Ryoo <hryoo(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Hridya Valsaraju <hvalsaraju(a)nvidia.com> Original-(cherry picked from commit 9629b318eb17b145315531509f950da02483114f) Original-Reviewed-on: https://chromium-review.googlesource.com/291095 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I19a93c915990644177c491c8212f2cf356d4d17d --- src/soc/nvidia/tegra210/addressmap.c | 23 +++++++++++++++++++++++ src/soc/nvidia/tegra210/include/soc/addressmap.h | 2 ++ src/soc/nvidia/tegra210/romstage.c | 1 + src/soc/nvidia/tegra210/soc.c | 20 -------------------- 4 files changed, 26 insertions(+), 20 deletions(-) diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index ddf3f99..d177323 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -91,6 +91,10 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) read32(&mc->mts_carveout_size_mb)); break; case CARVEOUT_VPR: + /* + * A 128MB VPR carveout is felt to be sufficient as per syseng. + * Set it up in vpr_region_init, below. + */ carveout_from_regs(base_mib, size_mib, read32(&mc->video_protect_bom), read32(&mc->video_protect_bom_adr_hi), @@ -347,3 +351,22 @@ void tsec_region_init(void) setbits_le32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED); setbits_le32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } + +void vpr_region_init(void) +{ + struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; + uintptr_t vpr_base_mib = 0, end = 4096; + size_t vpr_size_mib = VPR_CARVEOUT_SIZE_MB; + + /* Get memory layout below 4GiB */ + memory_in_range(&vpr_base_mib, &end, CARVEOUT_VPR); + vpr_base_mib = end - vpr_size_mib; + + /* Set the carveout base address and size */ + write32(&mc->video_protect_bom, vpr_base_mib << 20); + write32(&mc->video_protect_bom_adr_hi, 0); + write32(&mc->video_protect_size_mb, vpr_size_mib); + + /* Set the locked bit. This will lock out any other writes! */ + write32(&mc->video_protect_reg_ctrl, MC_VPR_WR_ACCESS_DISABLE); +} diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index b9bec18..322a971 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -107,6 +107,7 @@ enum { #define GPU_CARVEOUT_SIZE_MB 1 #define NVDEC_CARVEOUT_SIZE_MB 1 #define TSEC_CARVEOUT_SIZE_MB 2 +#define VPR_CARVEOUT_SIZE_MB 128 /* Return total size of DRAM memory configured on the platform. */ int sdram_size_mb(void); @@ -148,5 +149,6 @@ void trustzone_region_init(void); void gpu_region_init(void); void nvdec_region_init(void); void tsec_region_init(void); +void vpr_region_init(void); #endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index d8d191b..16ba778 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -71,6 +71,7 @@ void romstage(void) gpu_region_init(); nvdec_region_init(); tsec_region_init(); + vpr_region_init(); /* * When romstage is running it's always on the reboot path -- never a diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 829acb2..9e67531 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -82,23 +82,6 @@ static struct cpu_control_ops cntrl_ops = { }; -static void lock_down_vpr(void) -{ - struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; - - write32(&regs->video_protect_bom, 0); - write32(&regs->video_protect_size_mb, 0); - - write32(&regs->video_protect_gpu_override_0, 1); - /* - * Set both _ACCESS bits so that kernel/secure code - * can reconfig VPR careveout as needed from the TrustZone. - */ - - write32(&regs->video_protect_reg_ctrl, - (MC_VPR_WR_ACCESS_DISABLE | MC_VPR_ALLOW_TZ_WR_ACCESS_ENABLE)); -} - static void soc_init(device_t dev) { struct soc_nvidia_tegra210_config *cfg; @@ -109,9 +92,6 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); - /* Lock down VPR */ - lock_down_vpr(); - #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) if (vboot_skip_display_init()) printk(BIOS_INFO, "Skipping display init.\n");

1 0

Patch set updated for coreboot: veyron_rialto: Force 3G modem off
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11385 -gerrit commit ee2f8bcd2d301dd074427407686aadb273129d27 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Aug 5 14:13:34 2015 -0700 veyron_rialto: Force 3G modem off This basically does the same thing for firmware what CL:290631 did in the kernel. We want to keep the modem off until it needs to be used to avoid enumeration/detection issues. BUG=chrome-os-partner:43271 BRANCH=none TEST=needs testing Change-Id: I3b63a77c732dc4895b728b30f1dd71210a9c0e90 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a90ccd7fbffe44abe05e96341cc77067442c85e4 Original-Change-Id: I3516de1ea9160f7186ad7f5fb3b5d29ac73143b5 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290890 Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> --- src/mainboard/google/veyron_rialto/mainboard.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 52a27bb..4dba666 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -72,6 +72,14 @@ static void configure_codec(void) rkclk_configure_i2s(12288000); } +static void configure_3g(void) +{ + /* Force 3G modem off to avoid confusing the EHCI host and + * causing problems during enumeration/init */ + gpio_output(GPIO(5, C, 1), 1); /* 3G_SHUTDOWN */ + gpio_output(GPIO(4, D, 2), 0); /* 3G_ON_OFF */ +} + static void mainboard_init(device_t dev) { gpio_output(GPIO_RESET, 0); @@ -79,6 +87,7 @@ static void mainboard_init(device_t dev) configure_usb(); configure_emmc(); configure_codec(); + configure_3g(); /* No video. */ elog_init();

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Patch set updated for coreboot: edid: add function to manually specify mode
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11390 -gerrit commit 5c542869bd5fa642bfdc0e02e76529fa2a4aa748 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 7 18:41:37 2015 -0700 edid: add function to manually specify mode This patch will let you to choose a favourite mode to display, while not just taking the edid detail timing. But not all modes are able to set, only modes that are in established or standard timing, and we only support a few common common resolutions for now. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=tested dev mode on Mickey at 640x480@60Hz Change-Id: I8a9dedfe08057d42d85b8ca129935a258cb26762 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 090583f90ff720d88e5cfe69fcb2d541c716f0e6 Original-Change-Id: Iaa8c9a6fad106ee792f7cd1a0ac77e3dcbadf481 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289671 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/include/edid.h | 9 +++++++- src/lib/edid.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 2 deletions(-) diff --git a/src/include/edid.h b/src/include/edid.h index 3de4dbc..72ae7f3 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -21,8 +21,13 @@ #define EDID_H enum edid_modes { - EDID_MODE_AUTO = 0, EDID_MODE_640x480_60Hz, + EDID_MODE_720x480_60Hz, + EDID_MODE_1280x720_60Hz, + EDID_MODE_1920x1080_60Hz, + NUM_KNOWN_MODES, + + EDID_MODE_AUTO }; struct edid_mode { @@ -75,6 +80,7 @@ struct edid { unsigned int panel_bits_per_pixel; /* used to compute timing for graphics chips. */ struct edid_mode mode; + u8 mode_is_supported[NUM_KNOWN_MODES]; unsigned int link_clock; /* 3 variables needed for coreboot framebuffer. * In most cases, they are the same as the ha @@ -89,5 +95,6 @@ struct edid { /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr); +int set_display_mode(struct edid *edid, enum edid_modes mode); #endif /* EDID_H */ diff --git a/src/lib/edid.c b/src/lib/edid.c index ed3565c..be3d906 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -977,6 +977,52 @@ static void dump_breakdown(unsigned char *edid) } /* + * Lookup table of some well-known modes that can be useful in case the + * auto-detected mode is unsuitable. + * ha = hdisplay; va = vdisplay; + * hbl = htotal - hdisplay; vbl = vtotal - vdisplay; + * hso = hsync_start - hdsiplay; vso = vsync_start - vdisplay; + * hspw = hsync_end - hsync_start; vspw = vsync_end - vsync_start; + */ +static struct edid_mode known_modes[NUM_KNOWN_MODES] = { + [EDID_MODE_640x480_60Hz] = { + .name = "640x480@60Hz", .pixel_clock = 25175, .refresh = 60, + .ha = 640, .hbl = 160, .hso = 16, .hborder = 96, + .va = 480, .vbl = 45, .vso = 10, .vspw = 2, + .phsync = '-', .pvsync = '-' }, + [EDID_MODE_720x480_60Hz] = { + .name = "720x480@60Hz", .pixel_clock = 27000, .refresh = 60, + .ha = 720, .hbl = 78, .hso = 16, .hborder = 62, + .va = 480, .vbl = 45, .vso = 9, .vspw = 6, + .phsync = '-', .pvsync = '-' }, + [EDID_MODE_1280x720_60Hz] = { + .name = "1280x720@60Hz", .pixel_clock = 74250, .refresh = 60, + .ha = 1280, .hbl = 370, .hso = 110, .hborder = 40, + .va = 720, .vbl = 30, .vso = 5, .vspw = 20, + .phsync = '+', .pvsync = '+' }, + [EDID_MODE_1920x1080_60Hz] = { + .name = "1920x1080@60Hz", .pixel_clock = 148500, .refresh = 60, + .ha = 1920, .hbl = 280, .hso = 88, .hborder = 44, + .va = 1080, .vbl = 45, .vso = 4, .vspw = 5, + .phsync = '+', .pvsync = '+' }, +}; + +int set_display_mode(struct edid *edid, enum edid_modes mode) +{ + if (mode == EDID_MODE_AUTO) + return 0; + + if (edid->mode_is_supported[mode]) { + printk(BIOS_DEBUG, "Forcing mode %s\n", known_modes[mode].name); + edid->mode = known_modes[mode]; + return 0; + } + + printk(BIOS_ERR, "Requested display mode not supported.\n"); + return -1; +} + +/* * Given a raw edid bloc, decode it into a form * that other parts of coreboot can use -- mainly * graphics bringup functions. The raw block is @@ -986,7 +1032,7 @@ static void dump_breakdown(unsigned char *edid) */ int decode_edid(unsigned char *edid, int size, struct edid *out) { - int analog, i; + int analog, i, j; struct edid_context c = { .has_valid_cvt = 1, .has_valid_dummy_block = 1, @@ -1210,6 +1256,14 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) printk(BIOS_SPEW, " %dx%d@%dHz\n", established_timings[i].x, established_timings[i].y, established_timings[i].refresh); } + + for (j = 0; j < NUM_KNOWN_MODES; j++) { + if (known_modes[j].ha == established_timings[i].x && + known_modes[j].va == established_timings[i].y && + known_modes[j].refresh == established_timings[i].refresh) + out->mode_is_supported[j] = 1; + } + } printk(BIOS_SPEW, "Standard timings supported:\n"); @@ -1245,6 +1299,11 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) refresh = 60 + (b2 & 0x3f); printk(BIOS_SPEW, " %dx%d@%dHz\n", x, y, refresh); + for (j = 0; j < NUM_KNOWN_MODES; j++) { + if (known_modes[j].ha == x && known_modes[j].va == y && + known_modes[j].refresh == refresh) + out->mode_is_supported[j] = 1; + } } /* detailed timings */

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Patch set updated for coreboot: rk3288: Ignore EDID errors for HDMI
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11391 -gerrit commit 0419d6383bd1536dd227b4abe160a08a9130422a Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 13 15:43:55 2015 -0700 rk3288: Ignore EDID errors for HDMI Assume that HDMI implies usage of an external display, and that we want to try bringing up display if we can read an EDID. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=none; need a display with corrupt EDID to test with Change-Id: I11cc61140d905d70798a7b46db7847f3a1b3c886 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: ace7773623eac57f068ecd50baa9108ce028cf1b Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I9e22984a98b1a5f8cd9645b92dc9b87e8d968f01 Original-Reviewed-on: https://chromium-review.googlesource.com/293548 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/hdmi.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index a7a9c40..e5bebe3 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -788,11 +788,10 @@ int rk_hdmi_get_edid(struct edid *edid) edid_size += HDMI_EDID_BLOCK_SIZE; } - ret = decode_edid(edid_buf, edid_size, edid); - if (ret) { + /* Assume usage of HDMI implies an external display in which case + * we should be lenient about errors that the EDID decoder finds. */ + if (decode_edid(edid_buf, edid_size, edid)) hdmi_debug("failed to decode edid.\n"); - return -1; - } return 0; }

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coreboot-gerrit August 2015