coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch merged into coreboot/master: Kunimitsu : FAB3 Adding BoardId support
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 3657eef8296efbe905330d71570d31c2d6357268 Author: pchandri <preetham.chandrian(a)intel.com> Date: Thu Aug 6 10:26:00 2015 -0700 Kunimitsu : FAB3 Adding BoardId support BRANCH=None BUG=chrome-os-partner:44087 TEST=Build and Boot kunimitsu. Original-Change-Id: I30ba8bad69a4fdf8ec29f9eb43a27d2e1c6b93dd Original-Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293832 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I8f85547865387091c9a6400611e3314f457076d5 Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Reviewed-on: http://review.coreboot.org/11275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11275 for details. -gerrit

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Patch merged into coreboot/master: Kunimitsu: enable deep S5
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 133dcd386f2ae620b635446bb3d7b34d3b95eca8 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Fri Jul 10 16:00:51 2015 +0530 Kunimitsu: enable deep S5 This patche enables the deep S5 and disables Deep S3. Kunimitsu does not resume from deep S3. This change will unblock the S3 resume path on kunimitsu board. BRANCH=None BUG=chrome-os-partner:42331 TEST=Built and booted on kunimitsu; check s3 works. Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291250 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I07b95a324a27ab658e80674686b47b86412ea097 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Reviewed-on: http://review.coreboot.org/11274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11274 for details. -gerrit

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New patch to review for coreboot: libpayload: x86: Add read/write{8, 16, 32} variants that match coreboot
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11405 -gerrit commit cb9270169adbc082231e6b85621d847fbb1f69b7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 19 16:04:15 2015 -0700 libpayload: x86: Add read/write{8,16,32} variants that match coreboot Add the now coreboot standard MMIO read/write accessors that were already defined for other architectures but not x86. This leaves the old read/write{b,w,l} variants in place as was done on the other architectures, presumably to support old payloads that have not been updated. BUG=chrome-os-partner:43072 BRANCH=none TEST=emerge-glados libpayload CQ-DEPEND=CL:294711 Change-Id: I5ae3d755adcef0f6ff27aaa7c35a5b12ddc32e22 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: c09dd557050e3002fa5b8504980d72d4cb79a56c Original-Change-Id: I58d928338335d3fe4bb7fe2bdc9c2967d8689118 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294565 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/include/x86/arch/io.h | 40 +++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index cd48d7c..c417ce0 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -31,6 +31,16 @@ #ifndef _ARCH_IO_H #define _ARCH_IO_H +#include <inttypes.h> + +/* + * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 + * instead for future development. + * + * TODO: make the existing code use read8/16/32 and write8/16/32 then remove + * readb/w/l and writeb/w/l. + */ + #define readb(_a) (*(volatile const unsigned char *) (_a)) #define readw(_a) (*(volatile const unsigned short *) (_a)) #define readl(_a) (*(volatile const unsigned int *) (_a)) @@ -39,6 +49,36 @@ #define writew(_v, _a) (*(volatile unsigned short *) (_a) = (_v)) #define writel(_v, _a) (*(volatile unsigned int *) (_a) = (_v)) +static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr) +{ + return *((volatile uint8_t *)(addr)); +} + +static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr) +{ + return *((volatile uint16_t *)(addr)); +} + +static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr) +{ + return *((volatile uint32_t *)(addr)); +} + +static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value) +{ + *((volatile uint8_t *)(addr)) = value; +} + +static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value) +{ + *((volatile uint16_t *)(addr)) = value; +} + +static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value) +{ + *((volatile uint32_t *)(addr)) = value; +} + static inline unsigned int inl(int port) { unsigned long val;

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New patch to review for coreboot: libpayload: usb: dwc2: Always return 'size' transferred bytes for OUT
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11404 -gerrit commit 7c0f08d78d6daeb632ebca486caf30dfc3b80d85 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 17 18:47:18 2015 -0700 libpayload: usb: dwc2: Always return 'size' transferred bytes for OUT Seems like our transferred bytes calculation for OUT transfers that span more than one packet had been wrong, and we just got lucky that we never noticed it before. The HCTSIZ.xfersize register field we're reading only counts bytes transferred by the last packet we sent. OUT endpoints cannot have short transfers -- every transfer should either finish all bytes we wanted to send or end in a proper error condition. Therefore, in the absence of an error we can just conclude that all input bytes have been transferred. BRANCH=veyron BUG=chrome-os-partner:35525 TEST=SMSC95xx netboot on Jerry now works. Change-Id: I57349e697c428df6b56e2f6f62e87652ef1e7a94 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 0abee13b6d89dec12c6fff581ece1836393c7703 Original-Change-Id: Id0a127e6919f5786ba05218277705dda1067b8c3 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293956 Original-Reviewed-by: yunzhi li <lyz(a)rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- payloads/libpayload/drivers/usb/dwc2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 9d19bc6..30e00fb 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -283,7 +283,7 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, if (ret >= 0) { /* Calculate actual transferred length */ - transferred = (dir == EPDIR_IN) ? inpkt_length - ret : ret; + transferred = (dir == EPDIR_IN) ? inpkt_length - ret : size; if (do_copy && (dir == EPDIR_IN)) memcpy(data_buf, aligned_buf, transferred);

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New patch to review for coreboot: arm64: xcompile: Add support for A53 erratum 843419
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11403 -gerrit commit ad39e26f608815cc69d925888befdfe8372d3849 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 20 14:36:34 2015 -0700 arm64: xcompile: Add support for A53 erratum 843419 This patch adds support to enable a linker workaround to a hardware erratum on some early Cortex-A53 revisions. Since the linker option was added very recently, we use xcompile to test whether the toolchain supports it first. It is also guarded by a Kconfig since only a few ARM64 SoCs will need this and it incurs a performance penalty. BRANCH=none BUG=none TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared in verbose make output accordingly. Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7 Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294745 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/arch/arm64/Kconfig | 8 ++++++++ payloads/libpayload/bin/lpgcc | 6 ++++++ src/arch/arm64/Kconfig | 9 +++++++++ util/xcompile/xcompile | 20 ++++++++++++++++++++ 4 files changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/arm64/Kconfig b/payloads/libpayload/arch/arm64/Kconfig index d2f8e56..a28a1f2 100644 --- a/payloads/libpayload/arch/arm64/Kconfig +++ b/payloads/libpayload/arch/arm64/Kconfig @@ -33,6 +33,14 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN +config ARM64_A53_ERRATUM_843419 + bool "Enable Cortex-A53 erratum 843419 linker workaround" + default n + help + Some early Cortex-A53 revisions had a hardware bug that results in + incorrect address calculations in rare cases. This option enables a + linker workaround to avoid those cases if your toolchain supports it. + config DMA_LIM_EXCL hex "DMA address limit(exclusive) in MiB units" default 0x1000 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 17d8eda..8d0260b 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -181,6 +181,12 @@ else echo "Could not find head.o" exit 1 fi + + if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config && + grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then + _LDFLAGS+=" -Wl,--fix-cortex-a53-843419" + fi + if [ $DEBUGME -eq 1 ]; then echo "$DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC" fi diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index b7cdc12..f2adf5c 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -55,3 +55,12 @@ config ARM64_SECURE_OS_FILE depends on ARM64_USE_SECURE_OS help Secure OS binary file. + +config ARM64_A53_ERRATUM_843419 + bool + default n + help + Some early Cortex-A53 revisions had a hardware bug that results in + incorrect address calculations in rare cases. This option enables a + linker workaround to avoid those cases if your toolchain supports it. + Should be selected automatically by SoCs that are affected. diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index e712ac3..46a30d1 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -87,6 +87,18 @@ testcc() { $1 -nostdlib -Werror $2 -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 } +testld() { + local gcc="$1" + local cflags="$2" + local ld="$3" + local ldflags="$4" + local tmp_o="$TMPFILE.o" + local tmp_elf="$TMPFILE.elf" + rm -f "$tmp_elf" + testcc $1 $2 && + $3 -nostdlib -static $4 -o "$tmp_elf" "$tmp_o" >/dev/null 2>&1 +} + testas() { local gccprefix="$1" local twidth="$2" @@ -163,6 +175,11 @@ detect_special_flags() { ;; x64) ;; + arm64) + testld "$GCC" "$CFLAGS_GCC" "${GCCPREFIX}ld${LINKER_SUFFIX}" \ + "$LDFLAGS --fix-cortex-a53-843419" && \ + LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419" + ;; mipsel) testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \ CFLAGS_GCC+=" -mno-abicalls -fno-pic" @@ -203,6 +220,9 @@ endif CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} +ifeq (\$(CONFIG_ARM64_A53_ERRATUM_843419)\$(CONFIG_LP_ARM64_A53_ERRATUM_843419),y) +LD_${TARCH}+=${LDFLAGS_ARM64_A53_ERRATUM_843419} +endif NM_${TARCH}:=${GCCPREFIX}nm OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy OBJDUMP_${TARCH}:=${GCCPREFIX}objdump

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New patch to review for coreboot: arm64: Fix 'verstage-objs: command not found' error
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11402 -gerrit commit c20f9aa8c828b9c05182cd10ca7d51a1c7609a98 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Aug 10 11:17:14 2015 +0800 arm64: Fix 'verstage-objs: command not found' error Fix following compilation error. LINK cbfs/fallback/verstage.debug /bin/sh: verstage-objs: command not found /usr/x86_64-pc-linux-gnu/aarch64-cros-linux-gnu/binutils-bin/2.24/ld.bfd.real: warning: cannot find entry symbol stage_entry; defaulting to 00000000000d7000 BRANCH=chromeos-2015.07 BUG=none TEST=emerge-oak coreboot Change-Id: I30e4c43625b2d1d076f24e8c2639ce951839661b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2a8936cdf34d315f580819df682335b2998f044f Original-Change-Id: I9afd57a5a868a348dff2c66cad0a8a09cdb2e911 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292557 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index e7ee84c..3e14f8b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -86,7 +86,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-y += boot.c verstage-y += div0.c

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New patch to review for coreboot: t210: sdram_lp0: also save EmcBctSpare2 field
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11401 -gerrit commit 86269c56bb3b6b5d3a5d8ccc0ccfd3b44479dd33 Author: Yen Lin <yelin(a)nvidia.com> Date: Thu Aug 20 15:19:07 2015 -0700 t210: sdram_lp0: also save EmcBctSpare2 field Need to save EmcBctSpare2 field to scratch register. Without it, system may not resume from LP0 suspend. BUG=chrome-os-partner:43797 BRANCH=none TEST=able to suspend/resume >30 times on a known failed board Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 6d1623c4c791f79e097193dfbc4bc894ef63e230 Original-Change-Id: I53ebf8c4d4c7cd19827128a84fbd97a377d78ff7 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294765 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-(cherry picked from commit ce38d902e889068d0068150c9352c2ecdb2f8815) Original-Reviewed-on: https://chromium-review.googlesource.com/294864 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I2ff21afbe9278413033101877c2581df51913709 --- src/soc/nvidia/tegra210/sdram_lp0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index f3f2af3..890c285 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -724,6 +724,7 @@ void sdram_lp0_save_params(const struct sdram_params *sdram) s32(EmcBctSpare5, scratch42); s32(EmcBctSpare4, scratch44); s32(SwizzleRankByteEncode, scratch45); + s32(EmcBctSpare2, scratch46); s32(EmcBctSpare1, scratch47); s32(EmcBctSpare0, scratch48); s32(EmcBctSpare9, scratch50);

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New patch to review for coreboot: veyron_rialto: remove spurious GPIO assignments
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11400 -gerrit commit dced1a3e6bbbd7b824a5998591e532173f502833 Author: Alexandru M Stan <amstan(a)chromium.org> Date: Thu Aug 20 11:45:26 2015 -0700 veyron_rialto: remove spurious GPIO assignments GPIO(0, B, 3) and GPIO(7, C, 5) are not actually connected, GPIO(0, B, 4) is named differently. BUG=chrome-os-partner:43031 TEST=Rialto should still boot just fine, USB should still work BRANCH=master Change-Id: I11879385de6e9b57ac28bcae699333beb5a0d64c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: a66bf1fd73ff8d15d4ec1a8f3602465941285c32 Original-Change-Id: Ib7d2baa6ed1ab38db786eb4d5e77316ad72cbfd4 Original-Signed-off-by: Alexandru M Stan <amstan(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294713 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/veyron_rialto/mainboard.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 4dba666..c2dde19 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -43,9 +43,7 @@ static void configure_usb(void) { - gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */ - gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */ - gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */ + gpio_output(GPIO(0, B, 4), 1); /* USB2_PWR_EN */ } static void configure_emmc(void)

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New patch to review for coreboot: veyron: add Nanya NT5CC256M16DP sdram
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11399 -gerrit commit a4be8a2bdb50cc3e5b45edc9fd84d3edfc8578c5 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Aug 20 14:06:31 2015 +0800 veyron: add Nanya NT5CC256M16DP sdram BRANCH=None TEST=Boot from veyron BUG=None Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 6fe83821013954f0f2069598fd90a2d49de81101 Original-Change-Id: I68b105aa4bc3e82ef6a2421b127391e319c34d6e Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-(cherry picked from commit c115d9a3ea2ca1cb62b2a1ee75996d8adb991d5d) Original-jwerner: Added Minnie Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294763 Change-Id: I2bd6521c209db0e2d7d0bdb8ef2cde2715f321a6 --- src/mainboard/google/veyron_brain/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_danger/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_jerry/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_mickey/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_mighty/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_minnie/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_pinky/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_romy/sdram_configs.c | 2 +- .../veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_shark/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_speedy/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++ 20 files changed, 790 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/veyron_brain/sdram_configs.c b/src/mainboard/google/veyron_brain/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_brain/sdram_configs.c +++ b/src/mainboard/google/veyron_brain/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_danger/sdram_configs.c b/src/mainboard/google/veyron_danger/sdram_configs.c index d7db069..84ceba5 100644 --- a/src/mainboard/google/veyron_danger/sdram_configs.c +++ b/src/mainboard/google/veyron_danger/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_jerry/sdram_configs.c +++ b/src/mainboard/google/veyron_jerry/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mighty/sdram_configs.c b/src/mainboard/google/veyron_mighty/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_mighty/sdram_configs.c +++ b/src/mainboard/google/veyron_mighty/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_minnie/sdram_configs.c b/src/mainboard/google/veyron_minnie/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_minnie/sdram_configs.c +++ b/src/mainboard/google/veyron_minnie/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_romy/sdram_configs.c +++ b/src/mainboard/google/veyron_romy/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_shark/sdram_configs.c b/src/mainboard/google/veyron_shark/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_shark/sdram_configs.c +++ b/src/mainboard/google/veyron_shark/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c index 63e7317..023eb37 100644 --- a/src/mainboard/google/veyron_speedy/sdram_configs.c +++ b/src/mainboard/google/veyron_speedy/sdram_configs.c @@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000..bd82e7b --- /dev/null +++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +},

1 0

New patch to review for coreboot: veyron_rialto: Turn on all leds
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11398 -gerrit commit bbed2260f89bb43a1316fb8c2acf3c2263dc320b Author: Alexandru M Stan <amstan(a)chromium.org> Date: Mon Aug 17 17:32:06 2015 -0700 veyron_rialto: Turn on all leds Without this, the leds would be stuck to whatever the pullup/down states the pins come with on rk3288. Ready2_LED, an orange led, is one of the leds in this state. This might confuse some users thinking there's an error. Turn all of them on instead. Later on depthcharge will use the same LEDs to indicate dev mode status. BUG=chrome-os-partner:44274 BRANCH=master TEST=Boot firmware without anything else, note all leds on Change-Id: I5cf19aabd2a59a61699ef491ae11424cf5a0c874 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2e1a332a5653fb76bbf8fe624274ec64d2b443a5 Original-Change-Id: I4c4e8940dd9cf1ac0301ac00bfc5992ba16e1589 Original-Signed-off-by: Alexandru M Stan <amstan(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294065 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/veyron_rialto/bootblock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 849bc95..38ae277 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -48,6 +48,12 @@ void bootblock_mainboard_init(void) if (rkclk_was_watchdog_reset()) reboot_from_watchdog(); + /* Turn on all leds */ + gpio_output(GPIO(7, A, 0), 1); /* LED_READY */ + gpio_output(GPIO(7, B, 5), 1); /* Ready2_LED */ + gpio_output(GPIO(7, B, 3), 1); /* LED_SYNCING */ + gpio_output(GPIO(7, B, 7), 1); /* LED_ERROR */ + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);

1 0

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coreboot-gerrit August 2015