coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: packardbell/ms2290/mainboard.c: Do not guard int15 includes
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11379 -gerrit commit 3fb4c8c36123ee89000c96353899d98cba1200e1 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 26 23:04:34 2015 -0700 packardbell/ms2290/mainboard.c: Do not guard int15 includes Do not guard the inclusion of "drivers/intel/gma/int15.h" and "arch/interrupt.h" with configs that control option rom execution. These headers already have the proper guards. The install_intel_vga_int15_handler() is unconditionally called, even when the header that declares it is guarded out. Change-Id: Ia273437486f5802aa2b53212f2a1b5704c9485fa Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/packardbell/ms2290/mainboard.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 5a4882f..bddc8a8 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -34,10 +34,8 @@ #include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE #include <drivers/intel/gma/int15.h> #include <arch/interrupt.h> -#endif #include <pc80/keyboard.h> #include <cpu/x86/lapic.h> #include <device/pci.h>

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Patch set updated for coreboot: Kconfig: Remove EXPERT mode
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11365 -gerrit commit e7d8bd1d91cb6577b9fca63f2e234b30c781198d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 26 10:11:02 2015 -0400 Kconfig: Remove EXPERT mode After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- payloads/external/SeaBIOS/Kconfig | 1 - src/Kconfig | 11 ----------- src/device/Kconfig | 4 ++-- src/northbridge/amd/amdfam10/Kconfig | 2 +- src/northbridge/amd/amdht/h3finit.c | 4 ++-- 5 files changed, 5 insertions(+), 17 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index b2ff21e..699b986 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -18,7 +18,6 @@ endchoice config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 - depends on EXPERT int help Some PS/2 keyboard controllers don't respond to commands immediately diff --git a/src/Kconfig b/src/Kconfig index 9c01687..2c75750 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -22,14 +22,6 @@ mainmenu "coreboot configuration" menu "General setup" -config EXPERT - bool "Expert mode" - help - This allows you to select certain advanced configuration options. - - Warning: Only enable this option if you really know what you are - doing! You have been warned! - config LOCALVERSION string "Local version string" help @@ -111,7 +103,6 @@ config CCACHE config FMD_GENPARSER bool "Generate flashmap descriptor parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the flashmap descriptor parser and made changes to fmd_scanner.l or fmd_parser.y. @@ -121,7 +112,6 @@ config FMD_GENPARSER config SCONFIG_GENPARSER bool "Generate SCONFIG parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l or sconfig.y. @@ -283,7 +273,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n - depends on EXPERT help Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. diff --git a/src/device/Kconfig b/src/device/Kconfig index 39e612d..3bee877 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT && EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && EXPERT + depends on PCI help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 13954d4..4d7147d 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -120,7 +120,7 @@ config SVI_HIGH_FREQ menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT + depends on (NORTHBRIDGE_AMD_AMDFAM10) choice prompt "HyperTransport downlink width" diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 0138cd9..849f4a8 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1399,13 +1399,13 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 +#if CONFIG_LIMIT_HT_DOWN_WIDTH_8 cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_UP_WIDTH_8 +#if CONFIG_LIMIT_HT_UP_WIDTH_8 cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16;

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Patch set updated for coreboot: Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11293 -gerrit commit f798ad49de1014858b016c18c744ab395e1e6bd7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 20 16:25:02 2015 -0400 Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/device/Kconfig | 4 ++-- src/mainboard/google/cyan/Kconfig | 2 -- src/mainboard/google/rambi/Kconfig | 2 -- src/mainboard/intel/strago/Kconfig | 2 -- src/soc/intel/broadwell/Kconfig | 2 -- src/soc/intel/skylake/Kconfig | 2 -- 6 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d780d13..39e612d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT && EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on PCI && EXPERT help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index f3bb851..e4dc322 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -2,8 +2,6 @@ if BOARD_GOOGLE_CYAN config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 1ad2d6d..825df9a 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,8 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 1d4d4d8..1512a46 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -2,8 +2,6 @@ if BOARD_INTEL_STRAGO config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 524366c..0106255 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f42d3ab..9805b6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

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Patch set updated for coreboot: Kconfig: Remove EXPERT mode
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11365 -gerrit commit e159e8b8521fd0307a81b2a668167995cdf8a4b7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 26 10:11:02 2015 -0400 Kconfig: Remove EXPERT mode After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- payloads/external/SeaBIOS/Kconfig | 1 - src/Kconfig | 11 ----------- src/device/Kconfig | 4 ++-- src/northbridge/amd/amdfam10/Kconfig | 2 +- src/northbridge/amd/amdht/h3finit.c | 4 ++-- 5 files changed, 5 insertions(+), 17 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index b2ff21e..699b986 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -18,7 +18,6 @@ endchoice config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 - depends on EXPERT int help Some PS/2 keyboard controllers don't respond to commands immediately diff --git a/src/Kconfig b/src/Kconfig index 9c01687..2c75750 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -22,14 +22,6 @@ mainmenu "coreboot configuration" menu "General setup" -config EXPERT - bool "Expert mode" - help - This allows you to select certain advanced configuration options. - - Warning: Only enable this option if you really know what you are - doing! You have been warned! - config LOCALVERSION string "Local version string" help @@ -111,7 +103,6 @@ config CCACHE config FMD_GENPARSER bool "Generate flashmap descriptor parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the flashmap descriptor parser and made changes to fmd_scanner.l or fmd_parser.y. @@ -121,7 +112,6 @@ config FMD_GENPARSER config SCONFIG_GENPARSER bool "Generate SCONFIG parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l or sconfig.y. @@ -283,7 +273,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n - depends on EXPERT help Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. diff --git a/src/device/Kconfig b/src/device/Kconfig index 39e612d..3bee877 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT && EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && EXPERT + depends on PCI help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 13954d4..4d7147d 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -120,7 +120,7 @@ config SVI_HIGH_FREQ menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT + depends on (NORTHBRIDGE_AMD_AMDFAM10) choice prompt "HyperTransport downlink width" diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 0138cd9..849f4a8 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1399,13 +1399,13 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 +#if CONFIG_LIMIT_HT_DOWN_WIDTH_8 cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_UP_WIDTH_8 +#if CONFIG_LIMIT_HT_UP_WIDTH_8 cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16;

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Patch set updated for coreboot: Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS
by Alexandru Gagniuc 27 Aug '15

27 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11293 -gerrit commit 01c0deee35e941d57d22529b09e4f6565e4db66a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 20 16:25:02 2015 -0400 Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/device/Kconfig | 4 ++-- src/mainboard/google/cyan/Kconfig | 2 -- src/mainboard/google/rambi/Kconfig | 2 -- src/mainboard/intel/strago/Kconfig | 2 -- src/soc/intel/broadwell/Kconfig | 2 -- src/soc/intel/skylake/Kconfig | 2 -- 6 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d780d13..39e612d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT && EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on PCI && EXPERT help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index f3bb851..e4dc322 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -2,8 +2,6 @@ if BOARD_GOOGLE_CYAN config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 1ad2d6d..825df9a 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,8 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 1d4d4d8..1512a46 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -2,8 +2,6 @@ if BOARD_INTEL_STRAGO config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 524366c..0106255 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f42d3ab..9805b6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

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New patch to review for coreboot: AMD Bettong: Add usb device into devicetree.
by Zheng Bao 27 Aug '15

27 Aug '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11378 -gerrit commit 166fe38f8083e2974f2564f6e9906303a1c8d1f7 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 26 22:29:07 2015 -0400 AMD Bettong: Add usb device into devicetree. Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/include/device/pci_ids.h | 1 + src/mainboard/amd/bettong/devicetree.cb | 4 +--- src/southbridge/amd/pi/hudson/usb.c | 1 + 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5ba183b..dcb8a42 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -434,6 +434,7 @@ #define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 #define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 #define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 +#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb index 90b0324..41a5655 100644 --- a/src/mainboard/amd/bettong/devicetree.cb +++ b/src/mainboard/amd/bettong/devicetree.cb @@ -44,11 +44,9 @@ chip northbridge/amd/pi/00660F01/root_complex chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device pci 9.0 on end # HDA device pci 9.2 on end # HDA + device pci 10.0 on end # USB device pci 11.0 on end # SATA device pci 12.0 on end # USB -# device pci 12.2 on end # USB - device pci 13.0 on end # USB -# device pci 13.2 on end # USB device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index f686521..ef8f675 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -49,6 +49,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_ATI_SB900_USB_20_5, PCI_DEVICE_ID_AMD_CZ_USB_0, PCI_DEVICE_ID_AMD_CZ_USB_1, + PCI_DEVICE_ID_AMD_CZ_USB3_0, 0 };

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New patch to review for coreboot: AMD Bettong: Set the USB3 port as unremoveable.
by Zheng Bao 27 Aug '15

27 Aug '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11377 -gerrit commit dfcf1a2b793a56eee1eeef158ea0d062fbe140b0 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Aug 26 03:37:40 2015 -0400 AMD Bettong: Set the USB3 port as unremoveable. Without this change, if one USB3 device is attached when the board is power up, the USB3 port can not be used. Change-Id: I98628975000c7d56b1540c2b321d580ace1ef70e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 0311baa..ad8dc40 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -87,6 +87,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Usb.Xhci0Enable = FALSE; #endif FchParams_env->Usb.Xhci1Enable = FALSE; + FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ /* sata configuration */ }

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New patch to review for coreboot: AMD Bettong: Lower the TOM to give more MMIO space
by Zheng Bao 27 Aug '15

27 Aug '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11376 -gerrit commit 0eeb5d91ba492400ec46925b0a6ff49b5185ab9f Author: zbao <fishbaozi(a)gmail.com> Date: Mon Aug 24 00:24:51 2015 -0400 AMD Bettong: Lower the TOM to give more MMIO space Change-Id: Idf28faa26a7ea5e94495af5ff027309df444766e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/northbridge/amd/pi/agesawrapper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 255b31d..9bdf340 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -140,6 +140,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; + PostParams->MemConfig.BottomIo = (UINT16)(0xD0000000 >> 24); status = AmdInitPost (PostParams); printk( BIOS_SPEW,

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New patch to review for coreboot: AMD bettong: Fix the PCIe lane map
by Zheng Bao 27 Aug '15

27 Aug '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11375 -gerrit commit 47a97e319d18f6b69ffed2a7aade49f5585cba2e Author: zbao <fishbaozi(a)gmail.com> Date: Sun Aug 16 22:45:59 2015 -0400 AMD bettong: Fix the PCIe lane map Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/PlatformGnbPcie.c | 27 +++++++++++++++++++-------- src/mainboard/amd/bettong/devicetree.cb | 2 ++ 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/src/mainboard/amd/bettong/PlatformGnbPcie.c b/src/mainboard/amd/bettong/PlatformGnbPcie.c index af272dd..16ac427 100644 --- a/src/mainboard/amd/bettong/PlatformGnbPcie.c +++ b/src/mainboard/amd/bettong/PlatformGnbPcie.c @@ -22,7 +22,7 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { - /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), @@ -46,33 +46,44 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0x04, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0x05, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */ { - DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0x06, 0) }, + /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x07, 0) + }, + }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb index 44ae75a..90b0324 100644 --- a/src/mainboard/amd/bettong/devicetree.cb +++ b/src/mainboard/amd/bettong/devicetree.cb @@ -37,6 +37,8 @@ chip northbridge/amd/pi/00660F01/root_complex device pci 2.3 on end # Realtek NIC device pci 2.4 on end # Edge Connector device pci 2.5 on end # Edge Connector + device pci 3.0 on end # Edge Connector + device pci 3.1 on end # Edge Connector end #chip northbridge/amd/pi/00660F01 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus

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New patch to review for coreboot: AMD bettong: Fix the interrupt routine.
by Zheng Bao 27 Aug '15

27 Aug '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11374 -gerrit commit 433ab04092f56f6a84e83eb2b93eff56f76c694e Author: zbao <fishbaozi(a)gmail.com> Date: Tue Aug 4 06:34:50 2015 -0400 AMD bettong: Fix the interrupt routine. The unchanged code worked because the OS uses MSI instead APIC. Change-Id: I893e73f2aab3227381e44406fa285613e4ba2904 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/acpi/routing.asl | 90 ++++++++++++++++------ .../amd/pi/00660F01/acpi/northbridge.asl | 35 +++++++++ 2 files changed, 100 insertions(+), 25 deletions(-) diff --git a/src/mainboard/amd/bettong/acpi/routing.asl b/src/mainboard/amd/bettong/acpi/routing.asl index 3cfdb79..2a559c8 100644 --- a/src/mainboard/amd/bettong/acpi/routing.asl +++ b/src/mainboard/amd/bettong/acpi/routing.asl @@ -109,12 +109,9 @@ Name(APR0, Package(){ Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, @@ -148,10 +145,10 @@ Name(PS4, Package(){ }) Name(APS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, }) /* GPP 0 */ @@ -162,10 +159,10 @@ Name(PS5, Package(){ Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, }) /* GPP 1 */ @@ -176,10 +173,10 @@ Name(PS6, Package(){ Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, }) /* GPP 2 */ @@ -190,10 +187,10 @@ Name(PS7, Package(){ Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, }) /* GPP 3 */ @@ -204,9 +201,52 @@ Name(PS8, Package(){ Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) + +/* GFX 2 */ +Name(PSA, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, }) +Name(APSA, Package(){ + Package(){0x0000FFFF, 0, 0, 52 }, + Package(){0x0000FFFF, 1, 0, 53 }, + Package(){0x0000FFFF, 2, 0, 54 }, + Package(){0x0000FFFF, 3, 0, 55 }, +}) + +/* GFX 3 */ +Name(PSB, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSB, Package(){ + Package(){0x0000FFFF, 0, 0, 27 }, + Package(){0x0000FFFF, 1, 0, 24 }, + Package(){0x0000FFFF, 2, 0, 25 }, + Package(){0x0000FFFF, 3, 0, 26 }, +}) + +/* GFX 4 */ +Name(PSC, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSC, Package(){ + Package(){0x0000FFFF, 0, 0, 31 }, + Package(){0x0000FFFF, 1, 0, 28 }, + Package(){0x0000FFFF, 2, 0, 29 }, + Package(){0x0000FFFF, 3, 0, 30 }, +}) + diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 7a9960f..b3df987 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -98,3 +98,38 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ + +/* GFX 1 */ +Device(PBR9) { + Name(_ADR, 0x00030002) +} /* end PBR8 */ + +/* GFX 2 */ +Device(PBRA) { + Name(_ADR, 0x00030003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSA) } /* APIC mode */ + Return (PSA) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 3 */ +Device(PBRB) { + Name(_ADR, 0x00030004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSB) } /* APIC mode */ + Return (PSB) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 4 */ +Device(PBRC) { + Name(_ADR, 0x00030005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSC) } /* APIC mode */ + Return (PSC) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */

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coreboot-gerrit August 2015