coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: riscv-memlayout: fix existing memlayout issues, add sbi interface
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370 -gerrit commit db385b74c2ac798e21ee3f6bf012947815240f2c Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:39:16 2015 -0700 riscv-memlayout: fix existing memlayout issues, add sbi interface Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Update Makefile to include all the files necessary for sbi interface. To build, update to src/arch/riscv/include/atomic.h was required to remove compiler warnings Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/Makefile.inc | 3 + src/arch/riscv/bootblock.S | 108 ++++++++++++++++++++--- src/arch/riscv/include/atomic.h | 1 - src/mainboard/emulation/spike-riscv/memlayout.ld | 10 +-- 4 files changed, 102 insertions(+), 20 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c7a2c16..64d5ce9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ @@ -85,6 +86,8 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += trap_handler.c +ramstage-y += virtual_memory.c ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index a26b144..4caeea6 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,7 +1,7 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2013Google Inc. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,34 +22,112 @@ .section ".text._start", "ax", %progbits // Maybe there's a better way. -.space 0x200 +# machine mode handler when in supervisor mode +.space 0x140 +supervisor_machine_handler: + j supervisor_trap_entry + +# handler for when +.space 0x7c +.globl machine_handler +machine_handler: +# call trap_handler + j trap_entry + +.space 0x3c .globl _start _start: // pending figuring out this f-ing toolchain. Hardcode what we know works. -// la sp, 0x4ef0 // .stacktop -// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv - la sp, 0x7FF00 // stack start + stack size + la sp, 0x80FFF0 // stack start + stack size - // make room for HLS + # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - + csrr a0, mhartid + call hls_init //poison the stack - la t1, 0x40000 + la t1, 0x800000 li t0, 0xdeadbeef sd t0, 0(t1) -// la gp, _gp + la t0, exception_handler + csrw stvec, t0 # clear any pending interrupts -#if __GNUC__ < 5 - csrwi clear_ipi, 0 -#else csrwi sip, 0 -#endif + # set up the mstatus register for VM + call mstatus_init call main +.=0x2000 + .space 0x800 +# sbi interface lives here + +# hart_id +.align 5 +li a7, 0 +ecall +ret + +# num_harts +.align 4 +li a0, 1 +ret + +# query_memory +.align 4 +li a7, 8 +ecall +ret + +# console_putchar +.align 4 +li a7, 1 +ecall +ret + +# send_device_request +.align 4 +li a7, 2 +ecall +ret + +# receive_device_response +.align 4 +li a7, 3 +ecall +ret + +# send ipi +.align 4 +li a7, 4 +ecall +ret + +# clear ipi +.align 4 +li a7, 5 +ecall +ret + +# timebase +.align 4 +li a0, 10000000 # temporary, we should provide the correct answer +ret + +# shutdown +.align 4 +li a7, 6 +ecall + +# set_timer +.align 4 +li a7, 7 +ecall +ret + +# end of SBI trampolines .=0x4000 .stack: .align 8 @@ -59,7 +137,9 @@ _start: .align 3 .stack_size: .quad 0xf00 - +.globl test_trap +exception_handler: + call trap_handler reset: init_stack_loop: diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h index 8d7295d..f63f6e1 100644 --- a/src/arch/riscv/include/atomic.h +++ b/src/arch/riscv/include/atomic.h @@ -3,7 +3,6 @@ #ifndef _RISCV_ATOMIC_H #define _RISCV_ATOMIC_H -//#include "config.h" #include <arch/encoding.h> #define disable_irqsave() clear_csr(sstatus, SSTATUS_IE) diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8801f35..8e2e7ee 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,10 +23,10 @@ SECTIONS { - DRAM_START(0x0) + DRAM_START(0x0) BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + STACK(8M, 64K) + ROMSTAGE(8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(8M + 192k, 8K) + RAMSTAGE(8M + 200K, 256K) }

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Patch set updated for coreboot: riscv-memlayout: fix existing memlayout issues, add sbi interface
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370 -gerrit commit 716838fc2abacee158f7e516fdabbd92361d2596 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:39:16 2015 -0700 riscv-memlayout: fix existing memlayout issues, add sbi interface Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Update Makefile to include all the files necessary for sbi interface. Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/Makefile.inc | 3 + src/arch/riscv/bootblock.S | 108 ++++++++++++++++++++--- src/mainboard/emulation/spike-riscv/memlayout.ld | 10 +-- 3 files changed, 102 insertions(+), 19 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c7a2c16..64d5ce9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ @@ -85,6 +86,8 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += trap_handler.c +ramstage-y += virtual_memory.c ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index a26b144..4caeea6 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,7 +1,7 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2013Google Inc. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,34 +22,112 @@ .section ".text._start", "ax", %progbits // Maybe there's a better way. -.space 0x200 +# machine mode handler when in supervisor mode +.space 0x140 +supervisor_machine_handler: + j supervisor_trap_entry + +# handler for when +.space 0x7c +.globl machine_handler +machine_handler: +# call trap_handler + j trap_entry + +.space 0x3c .globl _start _start: // pending figuring out this f-ing toolchain. Hardcode what we know works. -// la sp, 0x4ef0 // .stacktop -// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv - la sp, 0x7FF00 // stack start + stack size + la sp, 0x80FFF0 // stack start + stack size - // make room for HLS + # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - + csrr a0, mhartid + call hls_init //poison the stack - la t1, 0x40000 + la t1, 0x800000 li t0, 0xdeadbeef sd t0, 0(t1) -// la gp, _gp + la t0, exception_handler + csrw stvec, t0 # clear any pending interrupts -#if __GNUC__ < 5 - csrwi clear_ipi, 0 -#else csrwi sip, 0 -#endif + # set up the mstatus register for VM + call mstatus_init call main +.=0x2000 + .space 0x800 +# sbi interface lives here + +# hart_id +.align 5 +li a7, 0 +ecall +ret + +# num_harts +.align 4 +li a0, 1 +ret + +# query_memory +.align 4 +li a7, 8 +ecall +ret + +# console_putchar +.align 4 +li a7, 1 +ecall +ret + +# send_device_request +.align 4 +li a7, 2 +ecall +ret + +# receive_device_response +.align 4 +li a7, 3 +ecall +ret + +# send ipi +.align 4 +li a7, 4 +ecall +ret + +# clear ipi +.align 4 +li a7, 5 +ecall +ret + +# timebase +.align 4 +li a0, 10000000 # temporary, we should provide the correct answer +ret + +# shutdown +.align 4 +li a7, 6 +ecall + +# set_timer +.align 4 +li a7, 7 +ecall +ret + +# end of SBI trampolines .=0x4000 .stack: .align 8 @@ -59,7 +137,9 @@ _start: .align 3 .stack_size: .quad 0xf00 - +.globl test_trap +exception_handler: + call trap_handler reset: init_stack_loop: diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8801f35..8e2e7ee 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,10 +23,10 @@ SECTIONS { - DRAM_START(0x0) + DRAM_START(0x0) BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + STACK(8M, 64K) + ROMSTAGE(8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(8M + 192k, 8K) + RAMSTAGE(8M + 200K, 256K) }

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Patch set updated for coreboot: riscv-virtual-memory: Add virtual memory setup
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11369 -gerrit commit 1dbc9e6ff54c5477321e07a01be186d16a2120b3 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:28:04 2015 -0700 riscv-virtual-memory: Add virtual memory setup Execution in supervisor level code in RISCV requires early setup of virtual memory. Add initialization calls in src/arch/riscv/virtual_memory.c to implement the required page table setup, and helper functions to use when jumping to the payload correctly in riscv. Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/include/vm.h | 74 +++++++++++++++++++++ src/arch/riscv/virtual_memory.c | 142 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 216 insertions(+) diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h new file mode 100644 index 0000000..f9ffc40 --- /dev/null +++ b/src/arch/riscv/include/vm.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _VM_H +#define _VM_H + +#include <string.h> +#include <stdint.h> + +#define SUPERPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS)) +#define VM_CHOICE VM_SV39 +#define VA_BITS 39 +#define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) + +#define PROT_READ 1 +#define PROT_WRITE 2 +#define PROT_EXEC 4 + +#define MAP_PRIVATE 0x2 +#define MAP_FIXED 0x10 +#define MAP_ANONYMOUS 0x20 +#define MAP_POPULATE 0x8000 +#define MREMAP_FIXED 0x2 + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define supervisor_paddr_valid(start, length) \ + ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \ + && (uintptr_t)(start) + (length) < mem_size \ + && (uintptr_t)(start) + (length) >= (uintptr_t)(start)) + +typedef uintptr_t pte_t; +extern pte_t* root_page_table; + +void enter_supervisor(void); +void initVirtualMemory(void); + +size_t pte_ppn(pte_t pte); +pte_t ptd_create(uintptr_t ppn); +pte_t pte_create(uintptr_t ppn, int prot, int user); + +void walk_page_table(void); + +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); +void mstatus_init(void); // need to setup mstatus so we know we have virtual memory + +void flush_tlb(void); + +#endif diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c new file mode 100644 index 0000000..78405dd --- /dev/null +++ b/src/arch/riscv/virtual_memory.c @@ -0,0 +1,142 @@ +/* + * Early initialization code for riscv virtual memory + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <vm.h> +#include <arch/encoding.h> +#include <atomic.h> +#include <stdint.h> +#include <console/console.h> + +pte_t* root_page_table; + +void walk_page_table(void) { + // TODO: implement a full walk to make sure memory was set up + //const size_t pte_per_page = RISCV_PGSIZE/sizeof(void*); + pte_t* t = root_page_table; + printk(BIOS_DEBUG, "root_page_table: %p\n", t); +} + +void enter_supervisor(void) { + // enter supervisor mode + asm volatile("la t0, 1f; csrw mepc, t0; eret; 1:" ::: "t0"); +} + +void flush_tlb(void) +{ + asm volatile("sfence.vm"); +} + +size_t pte_ppn(pte_t pte) +{ + return pte >> PTE_PPN_SHIFT; +} + +pte_t ptd_create(uintptr_t ppn) +{ + return (ppn << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_TABLE; +} + +pte_t pte_create(uintptr_t ppn, int prot, int user) +{ + pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_V; + if (prot & PROT_WRITE) pte |= PTE_TYPE_URW_SRW; + if (prot & PROT_EXEC) pte |= PTE_TYPE_URX_SRX; + if (!user) pte |= PTE_TYPE_SR; + return pte; +} + +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) { + pte_t* sbi_pt = (pte_t*) pageTableStart; + memset(sbi_pt, 0, RISCV_PGSIZE); + // need to leave room for sbi page + uintptr_t memorySize = 0x7F000000; // 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE + + // middle page table + pte_t* middle_pt = (void*)sbi_pt + RISCV_PGSIZE; + size_t num_middle_pts = 2; // 3 level page table, 39 bit virtual address space for now + + // root page table + pte_t* root_pt = (void*)middle_pt + num_middle_pts * RISCV_PGSIZE; + memset(middle_pt, 0, (num_middle_pts + 1) * RISCV_PGSIZE); // 0's out middle_pt and root_pt + for (size_t i = 0; i < num_middle_pts; i++) + root_pt[(1<<RISCV_PGLEVEL_BITS)-num_middle_pts+i] = ptd_create(((uintptr_t)middle_pt >> RISCV_PGSHIFT) + i); + + // fill the middle page table + for (uintptr_t vaddr = virtMemStart, paddr = physMemStart; paddr < memorySize; vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) { + int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; + size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); + l2_idx += ((vaddr - virtMemStart) >> l2_shift); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + } + + // map SBI at top of vaddr space + uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + uintptr_t sbiStartAddress = 0x2000; // the start of the sbi mapping + uintptr_t sbiAddr = sbiStartAddress; + for (uintptr_t i = 0; i < num_sbi_pages; i++) { + uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbiAddr += RISCV_PGSIZE; + } + pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); + *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + + mb(); + root_page_table = root_pt; + write_csr(sptbr, root_pt); +} + +void initVirtualMemory(void) { + printk(BIOS_DEBUG, "Initializing virtual memory...\n"); + uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs + uintptr_t virtualStart = 0xffffffff81000000; + uintptr_t pageTableStart = 0x1f0000; + init_vm(virtualStart, physicalStart, pageTableStart); + mb(); + printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); + walk_page_table(); +} + +void mstatus_init(void) +{ + // supervisor support is required + + uintptr_t ms = 0; + ms = INSERT_FIELD(ms, MSTATUS_PRV, PRV_M); + ms = INSERT_FIELD(ms, MSTATUS_PRV1, PRV_S); + ms = INSERT_FIELD(ms, MSTATUS_PRV2, PRV_U); + ms = INSERT_FIELD(ms, MSTATUS_IE2, 1); + ms = INSERT_FIELD(ms, MSTATUS_VM, VM_CHOICE); + ms = INSERT_FIELD(ms, MSTATUS_FS, 3); + ms = INSERT_FIELD(ms, MSTATUS_XS, 3); + write_csr(mstatus, ms); + ms = read_csr(mstatus); + + if (EXTRACT_FIELD(ms, MSTATUS_VM) != VM_CHOICE) { + printk(BIOS_DEBUG, "we don't have virtual memory...\n"); + } else { + printk(BIOS_DEBUG, "-----------------------------\n"); + printk(BIOS_DEBUG, "virtual memory status enabled\n"); + printk(BIOS_DEBUG, "-----------------------------\n"); + } + + clear_csr(mip, MIP_MSIP); + set_csr(mie, MIP_MSIP); +}

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Patch set updated for coreboot: riscv-trap-handling: Add implementation for trap calls in riscv
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11368 -gerrit commit 50902db49107367d84f2e54b4cdb2e8d76d7c23f Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 14:54:31 2015 -0700 riscv-trap-handling: Add implementation for trap calls in riscv RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/Makefile.inc | 2 + src/arch/riscv/include/arch/errno.h | 66 ++++++++ src/arch/riscv/include/arch/exception.h | 22 +++ src/arch/riscv/include/spike_util.h | 17 ++ src/arch/riscv/trap_handler.c | 193 +++++++++++++++++++++++ src/arch/riscv/trap_util.S | 22 ++- src/mainboard/emulation/spike-riscv/spike_util.c | 139 ++++++++++++++++ 7 files changed, 460 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0f3eb0f..c7a2c16 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -29,6 +29,8 @@ riscv_asm_flags = ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S stages.c +bootblock-y += trap_util.S +bootblock-y += trap_handler.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ diff --git a/src/arch/riscv/include/arch/errno.h b/src/arch/riscv/include/arch/errno.h new file mode 100644 index 0000000..6f80ee5 --- /dev/null +++ b/src/arch/riscv/include/arch/errno.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _RISCV_ERRNO_BASE_H +#define _RISCV_ERRNO_BASE_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#endif diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index befab1f..8ed295d 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -32,8 +32,30 @@ #include <stdint.h> +typedef struct +{ + long gpr[32]; + long status; + long epc; + long badvaddr; + long cause; + long insn; +} trapframe; + +typedef uint32_t insn_t; + +typedef struct { + uintptr_t error; + insn_t insn; +} insn_fetch_t; + static inline void exception_init(void) { } +void trap_handler(trapframe* tf); +void handleSupervisorCall(trapframe* tf); +//void handleMisalignedLoad(trapframe *tf); +void handleMisalignedStore(trapframe *tf); + #endif diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/spike_util.h index a9d14cc..e9c0300 100644 --- a/src/arch/riscv/include/spike_util.h +++ b/src/arch/riscv/include/spike_util.h @@ -40,6 +40,12 @@ #define FROMHOST_DATA(fromhost_value) ((uint64_t)(fromhost_value) << 16 >> 16) typedef struct { + unsigned long base; + unsigned long size; + unsigned long node_id; +} memory_block_info; + +typedef struct { unsigned long dev; unsigned long cmd; unsigned long data; @@ -63,11 +69,22 @@ typedef struct { // hart-local storage, at top of stack #define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) +#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) #define MACHINE_STACK_SIZE RISCV_PGSIZE +uintptr_t translate_address(uintptr_t vAddr); +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p); +uintptr_t mcall_hart_id(void); uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs); uintptr_t mcall_console_putchar(uint8_t ch); void testPrint(void); +uintptr_t mcall_dev_req(sbi_device_message *m); +uintptr_t mcall_dev_resp(void); +uintptr_t mcall_set_timer(unsigned long long when); +uintptr_t mcall_clear_ipi(void); +uintptr_t mcall_send_ipi(uintptr_t recipient); +uintptr_t mcall_shutdown(void); +void hls_init(uint32_t hart_id); // need to call this before launching linux #endif diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c new file mode 100644 index 0000000..1f20c7f --- /dev/null +++ b/src/arch/riscv/trap_handler.c @@ -0,0 +1,193 @@ +/* + * Early initialization code for riscv + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <arch/exception.h> +#include <spike_util.h> +#include <string.h> + +#define HART_ID 0 +#define CONSOLE_PUT 1 +#define SEND_DEVICE_REQUEST 2 +#define RECEIVE_DEVICE_RESPONSE 3 +#define SEND_IPI 4 +#define CLEAR_IPI 5 +#define SHUTDOWN 6 +#define SET_TIMER 7 +#define QUERY_MEMORY 8 + +int loopBreak2 = 1; + +void handleSupervisorCall(trapframe *tf) { + uintptr_t call = tf->gpr[17]; + uintptr_t arg0 = tf->gpr[10]; + uintptr_t arg1 = tf->gpr[11]; + uintptr_t returnValue; + switch(call) { + case HART_ID: + printk(BIOS_DEBUG, "Getting hart id...\n"); + returnValue = mcall_hart_id(); + break; + case CONSOLE_PUT: + returnValue = mcall_console_putchar(arg0); + break; + case SEND_DEVICE_REQUEST: + printk(BIOS_DEBUG, "Sending device request...\n"); + returnValue = mcall_dev_req((sbi_device_message*) arg0); + break; + case RECEIVE_DEVICE_RESPONSE: + printk(BIOS_DEBUG, "Getting device response...\n"); + returnValue = mcall_dev_resp(); + break; + case SEND_IPI: + printk(BIOS_DEBUG, "Sending IPI...\n"); + returnValue = mcall_send_ipi(arg0); + break; + case CLEAR_IPI: + printk(BIOS_DEBUG, "Clearing IPI...\n"); + returnValue = mcall_clear_ipi(); + break; + case SHUTDOWN: + printk(BIOS_DEBUG, "Shutting down...\n"); + returnValue = mcall_shutdown(); + break; + case SET_TIMER: + printk(BIOS_DEBUG, "Setting timer...\n"); + returnValue = mcall_set_timer(arg0); + break; + case QUERY_MEMORY: + printk(BIOS_DEBUG, "Querying memory, CPU #%lld...\n", arg0); + returnValue = mcall_query_memory(arg0, (memory_block_info*) arg1); + break; + default: + printk(BIOS_DEBUG, "ERROR! Unrecognized system call\n"); + returnValue = 0; + break; // note: system call we do not know how to handle + } + tf->gpr[10] = returnValue; + write_csr(mepc, read_csr(mepc) + 4); + asm volatile("j supervisor_call_return"); +} + +void trap_handler(trapframe *tf) { + write_csr(mscratch, tf); + int cause = 0; + void* epc = 0; + void* badAddr = 0; + + // extract cause + asm("csrr t0, mcause"); + asm("move %0, t0" : "=r"(cause)); + + // extract faulting Instruction pc + epc = (void*) tf->epc; + + // extract bad address + asm("csrr t0, mbadaddr"); + asm("move %0, t0" : "=r"(badAddr)); + + switch(cause) { + case 0: + printk(BIOS_DEBUG, "Trap: Instruction address misaligned\n"); + break; + case 1: + printk(BIOS_DEBUG, "Trap: Instruction access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Address: %p\n", badAddr); + break; + case 2: + printk(BIOS_DEBUG, "Trap: Illegal instruction\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Address: %p\n", badAddr); + break; + case 3: + printk(BIOS_DEBUG, "Trap: Breakpoint\n"); + break; + case 4: + printk(BIOS_DEBUG, "Trap: Load address misaligned\n"); + //handleMisalignedLoad(tf); + break; + case 5: + printk(BIOS_DEBUG, "Trap: Load access fault\n"); + break; + case 6: + printk(BIOS_DEBUG, "Trap: Store address misaligned\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); + handleMisalignedStore(tf); + break; + case 7: + printk(BIOS_DEBUG, "Trap: Store access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); + break; + case 8: + printk(BIOS_DEBUG, "Trap: Environment call from U-mode\n"); + break; + case 9: + // Don't print so we make console putchar calls look the way they should + // printk(BIOS_DEBUG, "Trap: Environment call from S-mode\n"); + handleSupervisorCall(tf); + break; + case 10: + printk(BIOS_DEBUG, "Trap: Environment call from H-mode\n"); + break; + case 11: + printk(BIOS_DEBUG, "Trap: Environment call from M-mode\n"); + break; + default: + printk(BIOS_DEBUG, "Trap: Unknown cause\n"); + break; + } + printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + printk(BIOS_DEBUG, "looping...\n"); + while(1); +} + +void handleMisalignedStore(trapframe *tf) { + printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + insn_t faultingInstruction = 0; + uintptr_t faultingInstructionAddr = tf->epc; + asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr)); + asm("lw t0, 0(t0)"); + asm("move %0, t0" : "=r"(faultingInstruction)); + printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); + insn_t widthMask = 0x7000; + insn_t memWidth = (faultingInstruction & widthMask) >> 12; + insn_t srcMask = 0x1F00000; + insn_t srcRegister = (faultingInstruction & srcMask) >> 20; + printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth); + if (memWidth == 3) { + // store double, handle the issue + void* badAddress = (void*) tf->badvaddr; + long valueToStore = tf->gpr[srcRegister]; + memcpy(badAddress, &valueToStore, 8); + } else { + // panic, this should not have happened + printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n"); + while(1); + } + + // return to where we came from + write_csr(mepc, read_csr(mepc) + 4); + asm volatile("j machine_call_return"); +} diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 912bea8..9701aaf 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -1,3 +1,23 @@ +/* + * Early initialization code for riscv + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + #include <bits.h> .macro restore_regs # restore x registers @@ -101,7 +121,7 @@ supervisor_trap_entry: trap_entry: csrw mscratch, sp 1:addi sp,sp,-320 - save_tf_ + save_tf move a0,sp jal trap_handler .global supervisor_call_return diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index b34ff4a..1ee8b77 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -1,4 +1,143 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + #include <spike_util.h> +#include <arch/errno.h> +#include <atomic.h> +#include <string.h> +#include <console/console.h> + +uintptr_t translate_address(uintptr_t vAddr) { + // TODO: implement the page table translation algorithm + //uintptr_t pageTableRoot = read_csr(sptbr); + uintptr_t physAddrMask = 0xfffffff; + uintptr_t translationResult = vAddr & physAddrMask; + printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult); + return translationResult; +} + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) +{ + uintptr_t physicalAddr = translate_address((uintptr_t) p); + memory_block_info *info = (memory_block_info*) physicalAddr; + if (id == 0) { + info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later + info->size = 0x7F000000 - info->base; + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + //if (recipient >= num_harts) + //return -1; + + if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { + mb(); + write_csr(send_ipi, recipient); + } + + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + while (1) write_csr(mtohost, 1); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + write_csr(mtimecmp, when); + #ifndef __riscv64 + write_csr(mtimecmph, when >> 32); + #endif + clear_csr(mip, MIP_STIP); + set_csr(mie, MIP_MTIP); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; + + while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); + + m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; + HLS()->device_request_queue_head = m; + HLS()->device_request_queue_size++; + + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + htif_interrupt(0, 0); + + sbi_device_message* m = HLS()->device_response_queue_head; + if (m) { + //printm("resp %p\n", m); + sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); + HLS()->device_response_queue_head = next; + if (!next) { + HLS()->device_response_queue_tail = 0; + + // only clear SSIP if no other events are pending + clear_csr(mip, MIP_SSIP); + mb(); + if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); + } + } + return (uintptr_t)m; +} + +uintptr_t mcall_hart_id(void) +{ + return HLS()->hart_id; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { uintptr_t fromhost = swap_csr(mfromhost, 0);

1 0

New patch to review for coreboot: riscv-memlayout: fix existing memlayout issues, add sbi interface
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11370 -gerrit commit cb7e76a260bf12dccd1b75cab74b06493a1e4081 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:39:16 2015 -0700 riscv-memlayout: fix existing memlayout issues, add sbi interface Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Update Makefile to include all the files necessary for sbi interface. Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/Makefile.inc | 4 + src/arch/riscv/bootblock.S | 108 ++++++++++++++++++++--- src/mainboard/emulation/spike-riscv/memlayout.ld | 10 +-- 3 files changed, 103 insertions(+), 19 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0f3eb0f..60be871 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -29,6 +29,8 @@ riscv_asm_flags = ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S stages.c +bootblock-y += trap_util.S +bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ @@ -83,6 +85,8 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = +ramstage-y += trap_handler.c +ramstage-y += virtual_memory.c ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index a26b144..4caeea6 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -1,7 +1,7 @@ /* * Early initialization code for aarch64 (a.k.a. armv8) * - * Copyright 2013Google Inc. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,34 +22,112 @@ .section ".text._start", "ax", %progbits // Maybe there's a better way. -.space 0x200 +# machine mode handler when in supervisor mode +.space 0x140 +supervisor_machine_handler: + j supervisor_trap_entry + +# handler for when +.space 0x7c +.globl machine_handler +machine_handler: +# call trap_handler + j trap_entry + +.space 0x3c .globl _start _start: // pending figuring out this f-ing toolchain. Hardcode what we know works. -// la sp, 0x4ef0 // .stacktop -// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv - la sp, 0x7FF00 // stack start + stack size + la sp, 0x80FFF0 // stack start + stack size - // make room for HLS + # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - + csrr a0, mhartid + call hls_init //poison the stack - la t1, 0x40000 + la t1, 0x800000 li t0, 0xdeadbeef sd t0, 0(t1) -// la gp, _gp + la t0, exception_handler + csrw stvec, t0 # clear any pending interrupts -#if __GNUC__ < 5 - csrwi clear_ipi, 0 -#else csrwi sip, 0 -#endif + # set up the mstatus register for VM + call mstatus_init call main +.=0x2000 + .space 0x800 +# sbi interface lives here + +# hart_id +.align 5 +li a7, 0 +ecall +ret + +# num_harts +.align 4 +li a0, 1 +ret + +# query_memory +.align 4 +li a7, 8 +ecall +ret + +# console_putchar +.align 4 +li a7, 1 +ecall +ret + +# send_device_request +.align 4 +li a7, 2 +ecall +ret + +# receive_device_response +.align 4 +li a7, 3 +ecall +ret + +# send ipi +.align 4 +li a7, 4 +ecall +ret + +# clear ipi +.align 4 +li a7, 5 +ecall +ret + +# timebase +.align 4 +li a0, 10000000 # temporary, we should provide the correct answer +ret + +# shutdown +.align 4 +li a7, 6 +ecall + +# set_timer +.align 4 +li a7, 7 +ecall +ret + +# end of SBI trampolines .=0x4000 .stack: .align 8 @@ -59,7 +137,9 @@ _start: .align 3 .stack_size: .quad 0xf00 - +.globl test_trap +exception_handler: + call trap_handler reset: init_stack_loop: diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8801f35..8e2e7ee 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,10 +23,10 @@ SECTIONS { - DRAM_START(0x0) + DRAM_START(0x0) BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + STACK(8M, 64K) + ROMSTAGE(8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(8M + 192k, 8K) + RAMSTAGE(8M + 200K, 256K) }

1 0

New patch to review for coreboot: riscv-virtual-memory: Add virtual memory setup
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11369 -gerrit commit 0d2803badc445e19d1c4474db76d746d385fd979 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 15:28:04 2015 -0700 riscv-virtual-memory: Add virtual memory setup Execution in supervisor level code in RISCV requires early setup of virtual memory. Add initialization calls in src/arch/riscv/virtual_memory.c to implement the required page table setup, and helper functions to use when jumping to the payload correctly in riscv. Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/include/vm.h | 74 +++++++++++++++++++++ src/arch/riscv/virtual_memory.c | 142 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 216 insertions(+) diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h new file mode 100644 index 0000000..f9ffc40 --- /dev/null +++ b/src/arch/riscv/include/vm.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _VM_H +#define _VM_H + +#include <string.h> +#include <stdint.h> + +#define SUPERPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS)) +#define VM_CHOICE VM_SV39 +#define VA_BITS 39 +#define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) + +#define PROT_READ 1 +#define PROT_WRITE 2 +#define PROT_EXEC 4 + +#define MAP_PRIVATE 0x2 +#define MAP_FIXED 0x10 +#define MAP_ANONYMOUS 0x20 +#define MAP_POPULATE 0x8000 +#define MREMAP_FIXED 0x2 + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define supervisor_paddr_valid(start, length) \ + ((uintptr_t)(start) >= current.first_user_vaddr + current.bias \ + && (uintptr_t)(start) + (length) < mem_size \ + && (uintptr_t)(start) + (length) >= (uintptr_t)(start)) + +typedef uintptr_t pte_t; +extern pte_t* root_page_table; + +void enter_supervisor(void); +void initVirtualMemory(void); + +size_t pte_ppn(pte_t pte); +pte_t ptd_create(uintptr_t ppn); +pte_t pte_create(uintptr_t ppn, int prot, int user); + +void walk_page_table(void); + +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); +void mstatus_init(void); // need to setup mstatus so we know we have virtual memory + +void flush_tlb(void); + +#endif diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c new file mode 100644 index 0000000..78405dd --- /dev/null +++ b/src/arch/riscv/virtual_memory.c @@ -0,0 +1,142 @@ +/* + * Early initialization code for riscv virtual memory + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <vm.h> +#include <arch/encoding.h> +#include <atomic.h> +#include <stdint.h> +#include <console/console.h> + +pte_t* root_page_table; + +void walk_page_table(void) { + // TODO: implement a full walk to make sure memory was set up + //const size_t pte_per_page = RISCV_PGSIZE/sizeof(void*); + pte_t* t = root_page_table; + printk(BIOS_DEBUG, "root_page_table: %p\n", t); +} + +void enter_supervisor(void) { + // enter supervisor mode + asm volatile("la t0, 1f; csrw mepc, t0; eret; 1:" ::: "t0"); +} + +void flush_tlb(void) +{ + asm volatile("sfence.vm"); +} + +size_t pte_ppn(pte_t pte) +{ + return pte >> PTE_PPN_SHIFT; +} + +pte_t ptd_create(uintptr_t ppn) +{ + return (ppn << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_TABLE; +} + +pte_t pte_create(uintptr_t ppn, int prot, int user) +{ + pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_V; + if (prot & PROT_WRITE) pte |= PTE_TYPE_URW_SRW; + if (prot & PROT_EXEC) pte |= PTE_TYPE_URX_SRX; + if (!user) pte |= PTE_TYPE_SR; + return pte; +} + +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) { + pte_t* sbi_pt = (pte_t*) pageTableStart; + memset(sbi_pt, 0, RISCV_PGSIZE); + // need to leave room for sbi page + uintptr_t memorySize = 0x7F000000; // 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE + + // middle page table + pte_t* middle_pt = (void*)sbi_pt + RISCV_PGSIZE; + size_t num_middle_pts = 2; // 3 level page table, 39 bit virtual address space for now + + // root page table + pte_t* root_pt = (void*)middle_pt + num_middle_pts * RISCV_PGSIZE; + memset(middle_pt, 0, (num_middle_pts + 1) * RISCV_PGSIZE); // 0's out middle_pt and root_pt + for (size_t i = 0; i < num_middle_pts; i++) + root_pt[(1<<RISCV_PGLEVEL_BITS)-num_middle_pts+i] = ptd_create(((uintptr_t)middle_pt >> RISCV_PGSHIFT) + i); + + // fill the middle page table + for (uintptr_t vaddr = virtMemStart, paddr = physMemStart; paddr < memorySize; vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) { + int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; + size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); + l2_idx += ((vaddr - virtMemStart) >> l2_shift); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + } + + // map SBI at top of vaddr space + uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + uintptr_t sbiStartAddress = 0x2000; // the start of the sbi mapping + uintptr_t sbiAddr = sbiStartAddress; + for (uintptr_t i = 0; i < num_sbi_pages; i++) { + uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbiAddr += RISCV_PGSIZE; + } + pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); + *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + + mb(); + root_page_table = root_pt; + write_csr(sptbr, root_pt); +} + +void initVirtualMemory(void) { + printk(BIOS_DEBUG, "Initializing virtual memory...\n"); + uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs + uintptr_t virtualStart = 0xffffffff81000000; + uintptr_t pageTableStart = 0x1f0000; + init_vm(virtualStart, physicalStart, pageTableStart); + mb(); + printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); + walk_page_table(); +} + +void mstatus_init(void) +{ + // supervisor support is required + + uintptr_t ms = 0; + ms = INSERT_FIELD(ms, MSTATUS_PRV, PRV_M); + ms = INSERT_FIELD(ms, MSTATUS_PRV1, PRV_S); + ms = INSERT_FIELD(ms, MSTATUS_PRV2, PRV_U); + ms = INSERT_FIELD(ms, MSTATUS_IE2, 1); + ms = INSERT_FIELD(ms, MSTATUS_VM, VM_CHOICE); + ms = INSERT_FIELD(ms, MSTATUS_FS, 3); + ms = INSERT_FIELD(ms, MSTATUS_XS, 3); + write_csr(mstatus, ms); + ms = read_csr(mstatus); + + if (EXTRACT_FIELD(ms, MSTATUS_VM) != VM_CHOICE) { + printk(BIOS_DEBUG, "we don't have virtual memory...\n"); + } else { + printk(BIOS_DEBUG, "-----------------------------\n"); + printk(BIOS_DEBUG, "virtual memory status enabled\n"); + printk(BIOS_DEBUG, "-----------------------------\n"); + } + + clear_csr(mip, MIP_MSIP); + set_csr(mie, MIP_MSIP); +}

1 0

New patch to review for coreboot: riscv-trap-handling: Add implementation for trap calls in riscv
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11368 -gerrit commit 914be6a4e1a0092808fc42c9bed0c482fec6abcb Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 14:54:31 2015 -0700 riscv-trap-handling: Add implementation for trap calls in riscv RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/include/arch/errno.h | 66 ++++++++ src/arch/riscv/include/arch/exception.h | 22 +++ src/arch/riscv/include/spike_util.h | 13 +- src/arch/riscv/trap_handler.c | 195 +++++++++++++++++++++++ src/arch/riscv/trap_util.S | 22 ++- src/mainboard/emulation/spike-riscv/spike_util.c | 139 ++++++++++++++++ 6 files changed, 450 insertions(+), 7 deletions(-) diff --git a/src/arch/riscv/include/arch/errno.h b/src/arch/riscv/include/arch/errno.h new file mode 100644 index 0000000..6f80ee5 --- /dev/null +++ b/src/arch/riscv/include/arch/errno.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _RISCV_ERRNO_BASE_H +#define _RISCV_ERRNO_BASE_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#endif diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index befab1f..8ed295d 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -32,8 +32,30 @@ #include <stdint.h> +typedef struct +{ + long gpr[32]; + long status; + long epc; + long badvaddr; + long cause; + long insn; +} trapframe; + +typedef uint32_t insn_t; + +typedef struct { + uintptr_t error; + insn_t insn; +} insn_fetch_t; + static inline void exception_init(void) { } +void trap_handler(trapframe* tf); +void handleSupervisorCall(trapframe* tf); +//void handleMisalignedLoad(trapframe *tf); +void handleMisalignedStore(trapframe *tf); + #endif diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/spike_util.h index a9d14cc..2d6355b 100644 --- a/src/arch/riscv/include/spike_util.h +++ b/src/arch/riscv/include/spike_util.h @@ -1,15 +1,16 @@ /* - * This file is part of the coreboot project. + * Early initialization code for riscv * - * Copyright (C) 2013 The ChromiumOS Authors + * Copyright 2015 Google Inc. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c new file mode 100644 index 0000000..ce19d7a --- /dev/null +++ b/src/arch/riscv/trap_handler.c @@ -0,0 +1,195 @@ +/* + * Early initialization code for riscv + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <arch/exception.h> +#include <spike_util.h> +#include <string.h> + +#define HART_ID 0 +#define CONSOLE_PUT 1 +#define SEND_DEVICE_REQUEST 2 +#define RECEIVE_DEVICE_RESPONSE 3 +#define SEND_IPI 4 +#define CLEAR_IPI 5 +#define SHUTDOWN 6 +#define SET_TIMER 7 +#define QUERY_MEMORY 8 + +int loopBreak2 = 1; + +void handleSupervisorCall(trapframe *tf) { + uintptr_t call = tf->gpr[17]; + uintptr_t arg0 = tf->gpr[10]; + uintptr_t arg1 = tf->gpr[11]; + uintptr_t returnValue; + switch(call) { + case HART_ID: + printk(BIOS_DEBUG, "Getting hart id...\n"); + returnValue = mcall_hart_id(); + break; + case CONSOLE_PUT: + returnValue = mcall_console_putchar(arg0); + break; + case SEND_DEVICE_REQUEST: + printk(BIOS_DEBUG, "Sending device request...\n"); + returnValue = mcall_dev_req((sbi_device_message*) arg0); + break; + case RECEIVE_DEVICE_RESPONSE: + printk(BIOS_DEBUG, "Getting device response...\n"); + returnValue = mcall_dev_resp(); + break; + case SEND_IPI: + printk(BIOS_DEBUG, "Sending IPI...\n"); + returnValue = mcall_send_ipi(arg0); + break; + case CLEAR_IPI: + printk(BIOS_DEBUG, "Clearing IPI...\n"); + returnValue = mcall_clear_ipi(); + break; + case SHUTDOWN: + printk(BIOS_DEBUG, "Shutting down...\n"); + returnValue = mcall_shutdown(); + break; + case SET_TIMER: + printk(BIOS_DEBUG, "Setting timer...\n"); + returnValue = mcall_set_timer(arg0); + break; + case QUERY_MEMORY: + printk(BIOS_DEBUG, "Querying memory, CPU #%lld...\n", arg0); + returnValue = mcall_query_memory(arg0, (memory_block_info*) arg1); + break; + default: + printk(BIOS_DEBUG, "ERROR! Unrecognized system call\n"); + returnValue = 0; + break; // note: system call we do not know how to handle + } + tf->gpr[10] = returnValue; + write_csr(mepc, read_csr(mepc) + 4); + asm volatile("j supervisor_call_return"); +} + +void trap_handler(trapframe *tf) { + write_csr(mscratch, tf); + int cause = 0; + void* epc = 0; + void* badAddr = 0; + + // extract cause + asm("csrr t0, mcause"); + asm("move %0, t0" : "=r"(cause)); + + // extract faulting Instruction pc + epc = (void*) tf->epc; + + // extract bad address + asm("csrr t0, mbadaddr"); + asm("move %0, t0" : "=r"(badAddr)); + + switch(cause) { + case 0: + printk(BIOS_DEBUG, "Trap: Instruction address misaligned\n"); + break; + case 1: + printk(BIOS_DEBUG, "Trap: Instruction access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Address: %p\n", badAddr); + break; + case 2: + printk(BIOS_DEBUG, "Trap: Illegal instruction\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Address: %p\n", badAddr); + break; + case 3: + printk(BIOS_DEBUG, "Trap: Breakpoint\n"); + break; + case 4: + printk(BIOS_DEBUG, "Trap: Load address misaligned\n"); + //handleMisalignedLoad(tf); + break; + case 5: + printk(BIOS_DEBUG, "Trap: Load access fault\n"); + break; + case 6: + printk(BIOS_DEBUG, "Trap: Store address misaligned\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); + handleMisalignedStore(tf); + break; + case 7: + printk(BIOS_DEBUG, "Trap: Store access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); + break; + case 8: + printk(BIOS_DEBUG, "Trap: Environment call from U-mode\n"); + break; + case 9: + // Don't print so we make console putchar calls look the way they should + // printk(BIOS_DEBUG, "Trap: Environment call from S-mode\n"); + handleSupervisorCall(tf); + break; + case 10: + printk(BIOS_DEBUG, "Trap: Environment call from H-mode\n"); + break; + case 11: + printk(BIOS_DEBUG, "Trap: Environment call from M-mode\n"); + break; + default: + printk(BIOS_DEBUG, "Trap: Unknown cause\n"); + break; + } + printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + printk(BIOS_DEBUG, "looping...\n"); + while(1); +} + +void handleMisalignedStore(trapframe *tf) { + printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + insn_t faultingInstruction = 0; + uintptr_t faultingInstructionAddr = tf->epc; + uintptr_t misalignedMask = 0x4; + uintptr_t misalignedInstruction = faultingInstructionAddr & misalignedMask; + asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr)); + asm("lw t0, 0(t0)"); + asm("move %0, t0" : "=r"(faultingInstruction)); + printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); + insn_t widthMask = 0x7000; + insn_t memWidth = (faultingInstruction & widthMask) >> 12; + insn_t srcMask = 0x1F00000; + insn_t srcRegister = (faultingInstruction & srcMask) >> 20; + printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth); + if (memWidth == 3) { + // store double, handle the issue + void* badAddress = (void*) tf->badvaddr; + long valueToStore = tf->gpr[srcRegister]; + memcpy(badAddress, &valueToStore, 8); + } else { + // panic, this should not have happened + printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n"); + while(1); + } + + // return to where we came from + write_csr(mepc, read_csr(mepc) + 4); + asm volatile("j machine_call_return"); +} diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 912bea8..9701aaf 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -1,3 +1,23 @@ +/* + * Early initialization code for riscv + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + #include <bits.h> .macro restore_regs # restore x registers @@ -101,7 +121,7 @@ supervisor_trap_entry: trap_entry: csrw mscratch, sp 1:addi sp,sp,-320 - save_tf_ + save_tf move a0,sp jal trap_handler .global supervisor_call_return diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index b34ff4a..1ee8b77 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -1,4 +1,143 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + #include <spike_util.h> +#include <arch/errno.h> +#include <atomic.h> +#include <string.h> +#include <console/console.h> + +uintptr_t translate_address(uintptr_t vAddr) { + // TODO: implement the page table translation algorithm + //uintptr_t pageTableRoot = read_csr(sptbr); + uintptr_t physAddrMask = 0xfffffff; + uintptr_t translationResult = vAddr & physAddrMask; + printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult); + return translationResult; +} + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) +{ + uintptr_t physicalAddr = translate_address((uintptr_t) p); + memory_block_info *info = (memory_block_info*) physicalAddr; + if (id == 0) { + info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later + info->size = 0x7F000000 - info->base; + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + //if (recipient >= num_harts) + //return -1; + + if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { + mb(); + write_csr(send_ipi, recipient); + } + + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + while (1) write_csr(mtohost, 1); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + write_csr(mtimecmp, when); + #ifndef __riscv64 + write_csr(mtimecmph, when >> 32); + #endif + clear_csr(mip, MIP_STIP); + set_csr(mie, MIP_MTIP); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; + + while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); + + m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; + HLS()->device_request_queue_head = m; + HLS()->device_request_queue_size++; + + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + htif_interrupt(0, 0); + + sbi_device_message* m = HLS()->device_response_queue_head; + if (m) { + //printm("resp %p\n", m); + sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); + HLS()->device_response_queue_head = next; + if (!next) { + HLS()->device_response_queue_tail = 0; + + // only clear SSIP if no other events are pending + clear_csr(mip, MIP_SSIP); + mb(); + if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); + } + } + return (uintptr_t)m; +} + +uintptr_t mcall_hart_id(void) +{ + return HLS()->hart_id; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { uintptr_t fromhost = swap_csr(mfromhost, 0);

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Patch set updated for coreboot: riscv-trap-handling: Add preliminary trap handling for riscv
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11367 -gerrit commit 9bc713090ee3ac2779a1018316b1a3d3d8678f02 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 12:22:29 2015 -0700 riscv-trap-handling: Add preliminary trap handling for riscv RISCV requires a trap handler at the machine stage to deal with misaligned loads/stores, as well as to deal with calls that a linux payload will make in its setup. Put required assembly for jumping into and out of a trap here to be set up by the bootblock in a later commit. Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/include/bits.h | 57 +++++++++++++++++++++ src/arch/riscv/trap_util.S | 116 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+) diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h new file mode 100644 index 0000000..f69c7ec --- /dev/null +++ b/src/arch/riscv/include/bits.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _BITS_H +#define _BITS_H + +#define CONST_POPCOUNT2(x) ((((x) >> 0) & 1) + (((x) >> 1) & 1)) +#define CONST_POPCOUNT4(x) (CONST_POPCOUNT2(x) + CONST_POPCOUNT2((x)>>2)) +#define CONST_POPCOUNT8(x) (CONST_POPCOUNT4(x) + CONST_POPCOUNT4((x)>>4)) +#define CONST_POPCOUNT16(x) (CONST_POPCOUNT8(x) + CONST_POPCOUNT8((x)>>8)) +#define CONST_POPCOUNT32(x) (CONST_POPCOUNT16(x) + CONST_POPCOUNT16((x)>>16)) +#define CONST_POPCOUNT64(x) (CONST_POPCOUNT32(x) + CONST_POPCOUNT32((x)>>32)) +#define CONST_POPCOUNT(x) CONST_POPCOUNT64(x) + +#define CONST_CTZ2(x) CONST_POPCOUNT2(((x) & -(x))-1) +#define CONST_CTZ4(x) CONST_POPCOUNT4(((x) & -(x))-1) +#define CONST_CTZ8(x) CONST_POPCOUNT8(((x) & -(x))-1) +#define CONST_CTZ16(x) CONST_POPCOUNT16(((x) & -(x))-1) +#define CONST_CTZ32(x) CONST_POPCOUNT32(((x) & -(x))-1) +#define CONST_CTZ64(x) CONST_POPCOUNT64(((x) & -(x))-1) +#define CONST_CTZ(x) CONST_CTZ64(x) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LOG_REGBYTES 3 + +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S new file mode 100644 index 0000000..912bea8 --- /dev/null +++ b/src/arch/riscv/trap_util.S @@ -0,0 +1,116 @@ +#include <bits.h> +.macro restore_regs + # restore x registers + LOAD x1,1*REGBYTES(a0) + LOAD x2,2*REGBYTES(a0) + LOAD x3,3*REGBYTES(a0) + LOAD x4,4*REGBYTES(a0) + LOAD x5,5*REGBYTES(a0) + LOAD x6,6*REGBYTES(a0) + LOAD x7,7*REGBYTES(a0) + LOAD x8,8*REGBYTES(a0) + LOAD x9,9*REGBYTES(a0) + LOAD x11,11*REGBYTES(a0) + LOAD x12,12*REGBYTES(a0) + LOAD x13,13*REGBYTES(a0) + LOAD x14,14*REGBYTES(a0) + LOAD x15,15*REGBYTES(a0) + LOAD x16,16*REGBYTES(a0) + LOAD x17,17*REGBYTES(a0) + LOAD x18,18*REGBYTES(a0) + LOAD x19,19*REGBYTES(a0) + LOAD x20,20*REGBYTES(a0) + LOAD x21,21*REGBYTES(a0) + LOAD x22,22*REGBYTES(a0) + LOAD x23,23*REGBYTES(a0) + LOAD x24,24*REGBYTES(a0) + LOAD x25,25*REGBYTES(a0) + LOAD x26,26*REGBYTES(a0) + LOAD x27,27*REGBYTES(a0) + LOAD x28,28*REGBYTES(a0) + LOAD x29,29*REGBYTES(a0) + LOAD x30,30*REGBYTES(a0) + LOAD x31,31*REGBYTES(a0) + # restore a0 last + LOAD x10,10*REGBYTES(a0) + + + .endm +.macro save_tf + # save gprs + STORE x1,1*REGBYTES(x2) + STORE x3,3*REGBYTES(x2) + STORE x4,4*REGBYTES(x2) + STORE x5,5*REGBYTES(x2) + STORE x6,6*REGBYTES(x2) + STORE x7,7*REGBYTES(x2) + STORE x8,8*REGBYTES(x2) + STORE x9,9*REGBYTES(x2) + STORE x10,10*REGBYTES(x2) + STORE x11,11*REGBYTES(x2) + STORE x12,12*REGBYTES(x2) + STORE x13,13*REGBYTES(x2) + STORE x14,14*REGBYTES(x2) + STORE x15,15*REGBYTES(x2) + STORE x16,16*REGBYTES(x2) + STORE x17,17*REGBYTES(x2) + STORE x18,18*REGBYTES(x2) + STORE x19,19*REGBYTES(x2) + STORE x20,20*REGBYTES(x2) + STORE x21,21*REGBYTES(x2) + STORE x22,22*REGBYTES(x2) + STORE x23,23*REGBYTES(x2) + STORE x24,24*REGBYTES(x2) + STORE x25,25*REGBYTES(x2) + STORE x26,26*REGBYTES(x2) + STORE x27,27*REGBYTES(x2) + STORE x28,28*REGBYTES(x2) + STORE x29,29*REGBYTES(x2) + STORE x30,30*REGBYTES(x2) + STORE x31,31*REGBYTES(x2) + + # get sr, epc, badvaddr, cause + csrrw t0,mscratch,x0 + csrr s0,mstatus + csrr t1,mepc + csrr t2,mbadaddr + csrr t3,mcause + STORE t0,2*REGBYTES(x2) + STORE s0,32*REGBYTES(x2) + STORE t1,33*REGBYTES(x2) + STORE t2,34*REGBYTES(x2) + STORE t3,35*REGBYTES(x2) + + # get faulting insn, if it wasn't a fetch-related trap + li x5,-1 + STORE x5,36*REGBYTES(x2) +1: + .endm + + .text + .global supervisor_trap_entry +supervisor_trap_entry: + csrw mscratch, sp + # load in the top of the machine stack + la sp, 0x80FFF0 + 1:addi sp,sp,-320 + save_tf + move a0,sp + jal trap_handler + .global trap_entry +trap_entry: + csrw mscratch, sp + 1:addi sp,sp,-320 + save_tf_ + move a0,sp + jal trap_handler + .global supervisor_call_return +supervisor_call_return: + csrr a0, mscratch + restore_regs + eret # go back into supervisor call + .global machine_call_return +machine_call_return: + csrr a0, mscratch + restore_regs + eret # go back into machine call

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Patch set updated for coreboot: riscv-trap-handling: Add preliminary trap handling for riscv
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11367 -gerrit commit a1e71d40106dc9d482667965e24bce64522ed684 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 12:22:29 2015 -0700 riscv-trap-handling: Add preliminary trap handling for riscv RISCV requires a trap handler at the machine stage to deal with misaligned loads/stores, as well as to deal with calls that a linux payload will make in its setup. Put required assembly for jumping into and out of a trap here to be set up by the bootblock in a later commit. Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/include/bits.h | 57 ++++++++++++++++++ src/arch/riscv/trap_util.S | 136 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 193 insertions(+) diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h new file mode 100644 index 0000000..f69c7ec --- /dev/null +++ b/src/arch/riscv/include/bits.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _BITS_H +#define _BITS_H + +#define CONST_POPCOUNT2(x) ((((x) >> 0) & 1) + (((x) >> 1) & 1)) +#define CONST_POPCOUNT4(x) (CONST_POPCOUNT2(x) + CONST_POPCOUNT2((x)>>2)) +#define CONST_POPCOUNT8(x) (CONST_POPCOUNT4(x) + CONST_POPCOUNT4((x)>>4)) +#define CONST_POPCOUNT16(x) (CONST_POPCOUNT8(x) + CONST_POPCOUNT8((x)>>8)) +#define CONST_POPCOUNT32(x) (CONST_POPCOUNT16(x) + CONST_POPCOUNT16((x)>>16)) +#define CONST_POPCOUNT64(x) (CONST_POPCOUNT32(x) + CONST_POPCOUNT32((x)>>32)) +#define CONST_POPCOUNT(x) CONST_POPCOUNT64(x) + +#define CONST_CTZ2(x) CONST_POPCOUNT2(((x) & -(x))-1) +#define CONST_CTZ4(x) CONST_POPCOUNT4(((x) & -(x))-1) +#define CONST_CTZ8(x) CONST_POPCOUNT8(((x) & -(x))-1) +#define CONST_CTZ16(x) CONST_POPCOUNT16(((x) & -(x))-1) +#define CONST_CTZ32(x) CONST_POPCOUNT32(((x) & -(x))-1) +#define CONST_CTZ64(x) CONST_POPCOUNT64(((x) & -(x))-1) +#define CONST_CTZ(x) CONST_CTZ64(x) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LOG_REGBYTES 3 + +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S new file mode 100644 index 0000000..9f1d66d --- /dev/null +++ b/src/arch/riscv/trap_util.S @@ -0,0 +1,136 @@ +/* + * Early initialization code for aarch64 (a.k.a. armv8) + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <bits.h> +.macro restore_regs + # restore x registers + LOAD x1,1*REGBYTES(a0) + LOAD x2,2*REGBYTES(a0) + LOAD x3,3*REGBYTES(a0) + LOAD x4,4*REGBYTES(a0) + LOAD x5,5*REGBYTES(a0) + LOAD x6,6*REGBYTES(a0) + LOAD x7,7*REGBYTES(a0) + LOAD x8,8*REGBYTES(a0) + LOAD x9,9*REGBYTES(a0) + LOAD x11,11*REGBYTES(a0) + LOAD x12,12*REGBYTES(a0) + LOAD x13,13*REGBYTES(a0) + LOAD x14,14*REGBYTES(a0) + LOAD x15,15*REGBYTES(a0) + LOAD x16,16*REGBYTES(a0) + LOAD x17,17*REGBYTES(a0) + LOAD x18,18*REGBYTES(a0) + LOAD x19,19*REGBYTES(a0) + LOAD x20,20*REGBYTES(a0) + LOAD x21,21*REGBYTES(a0) + LOAD x22,22*REGBYTES(a0) + LOAD x23,23*REGBYTES(a0) + LOAD x24,24*REGBYTES(a0) + LOAD x25,25*REGBYTES(a0) + LOAD x26,26*REGBYTES(a0) + LOAD x27,27*REGBYTES(a0) + LOAD x28,28*REGBYTES(a0) + LOAD x29,29*REGBYTES(a0) + LOAD x30,30*REGBYTES(a0) + LOAD x31,31*REGBYTES(a0) + # restore a0 last + LOAD x10,10*REGBYTES(a0) + + + .endm +.macro save_tf + # save gprs + STORE x1,1*REGBYTES(x2) + STORE x3,3*REGBYTES(x2) + STORE x4,4*REGBYTES(x2) + STORE x5,5*REGBYTES(x2) + STORE x6,6*REGBYTES(x2) + STORE x7,7*REGBYTES(x2) + STORE x8,8*REGBYTES(x2) + STORE x9,9*REGBYTES(x2) + STORE x10,10*REGBYTES(x2) + STORE x11,11*REGBYTES(x2) + STORE x12,12*REGBYTES(x2) + STORE x13,13*REGBYTES(x2) + STORE x14,14*REGBYTES(x2) + STORE x15,15*REGBYTES(x2) + STORE x16,16*REGBYTES(x2) + STORE x17,17*REGBYTES(x2) + STORE x18,18*REGBYTES(x2) + STORE x19,19*REGBYTES(x2) + STORE x20,20*REGBYTES(x2) + STORE x21,21*REGBYTES(x2) + STORE x22,22*REGBYTES(x2) + STORE x23,23*REGBYTES(x2) + STORE x24,24*REGBYTES(x2) + STORE x25,25*REGBYTES(x2) + STORE x26,26*REGBYTES(x2) + STORE x27,27*REGBYTES(x2) + STORE x28,28*REGBYTES(x2) + STORE x29,29*REGBYTES(x2) + STORE x30,30*REGBYTES(x2) + STORE x31,31*REGBYTES(x2) + + # get sr, epc, badvaddr, cause + csrrw t0,mscratch,x0 + csrr s0,mstatus + csrr t1,mepc + csrr t2,mbadaddr + csrr t3,mcause + STORE t0,2*REGBYTES(x2) + STORE s0,32*REGBYTES(x2) + STORE t1,33*REGBYTES(x2) + STORE t2,34*REGBYTES(x2) + STORE t3,35*REGBYTES(x2) + + # get faulting insn, if it wasn't a fetch-related trap + li x5,-1 + STORE x5,36*REGBYTES(x2) +1: + .endm + + .text + .global supervisor_trap_entry +supervisor_trap_entry: + csrw mscratch, sp + # load in the top of the machine stack + la sp, 0x80FFF0 + 1:addi sp,sp,-320 + save_tf + move a0,sp + jal trap_handler + .global trap_entry +trap_entry: + csrw mscratch, sp + 1:addi sp,sp,-320 + save_tf + move a0,sp + jal trap_handler + .global supervisor_call_return +supervisor_call_return: + csrr a0, mscratch + restore_regs + eret # go back into supervisor call + .global machine_call_return +machine_call_return: + csrr a0, mscratch + restore_regs + eret # go back into machine call

1 0

New patch to review for coreboot: riscv-trap-handling: preliminary trap handling for riscv
by Thaminda Edirisooriya 26 Aug '15

26 Aug '15

Thaminda Edirisooriya (thaminda(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11367 -gerrit commit 80a9f3d693d8c3b98d9464372d9ac66322845825 Author: Thaminda Edirisooriya <thaminda(a)google.com> Date: Wed Aug 26 12:22:29 2015 -0700 riscv-trap-handling: preliminary trap handling for riscv RISCV requires a trap handler at the machine stage to deal with misaligned loads/stores, as well as to deal with calls that a linux payload will make in its setup. Putting required assembly for jumping into and out of a trap here to be set up by the bootblock in a later commit. Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e Signed-off-by: Thaminda Edirisooriya <thaminda(a)google.com> --- src/arch/riscv/include/bits.h | 57 +++++++++++++++++++++ src/arch/riscv/trap_util.S | 116 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+) diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h new file mode 100644 index 0000000..f69c7ec --- /dev/null +++ b/src/arch/riscv/include/bits.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _BITS_H +#define _BITS_H + +#define CONST_POPCOUNT2(x) ((((x) >> 0) & 1) + (((x) >> 1) & 1)) +#define CONST_POPCOUNT4(x) (CONST_POPCOUNT2(x) + CONST_POPCOUNT2((x)>>2)) +#define CONST_POPCOUNT8(x) (CONST_POPCOUNT4(x) + CONST_POPCOUNT4((x)>>4)) +#define CONST_POPCOUNT16(x) (CONST_POPCOUNT8(x) + CONST_POPCOUNT8((x)>>8)) +#define CONST_POPCOUNT32(x) (CONST_POPCOUNT16(x) + CONST_POPCOUNT16((x)>>16)) +#define CONST_POPCOUNT64(x) (CONST_POPCOUNT32(x) + CONST_POPCOUNT32((x)>>32)) +#define CONST_POPCOUNT(x) CONST_POPCOUNT64(x) + +#define CONST_CTZ2(x) CONST_POPCOUNT2(((x) & -(x))-1) +#define CONST_CTZ4(x) CONST_POPCOUNT4(((x) & -(x))-1) +#define CONST_CTZ8(x) CONST_POPCOUNT8(((x) & -(x))-1) +#define CONST_CTZ16(x) CONST_POPCOUNT16(((x) & -(x))-1) +#define CONST_CTZ32(x) CONST_POPCOUNT32(((x) & -(x))-1) +#define CONST_CTZ64(x) CONST_POPCOUNT64(((x) & -(x))-1) +#define CONST_CTZ(x) CONST_CTZ64(x) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LOG_REGBYTES 3 + +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S new file mode 100644 index 0000000..912bea8 --- /dev/null +++ b/src/arch/riscv/trap_util.S @@ -0,0 +1,116 @@ +#include <bits.h> +.macro restore_regs + # restore x registers + LOAD x1,1*REGBYTES(a0) + LOAD x2,2*REGBYTES(a0) + LOAD x3,3*REGBYTES(a0) + LOAD x4,4*REGBYTES(a0) + LOAD x5,5*REGBYTES(a0) + LOAD x6,6*REGBYTES(a0) + LOAD x7,7*REGBYTES(a0) + LOAD x8,8*REGBYTES(a0) + LOAD x9,9*REGBYTES(a0) + LOAD x11,11*REGBYTES(a0) + LOAD x12,12*REGBYTES(a0) + LOAD x13,13*REGBYTES(a0) + LOAD x14,14*REGBYTES(a0) + LOAD x15,15*REGBYTES(a0) + LOAD x16,16*REGBYTES(a0) + LOAD x17,17*REGBYTES(a0) + LOAD x18,18*REGBYTES(a0) + LOAD x19,19*REGBYTES(a0) + LOAD x20,20*REGBYTES(a0) + LOAD x21,21*REGBYTES(a0) + LOAD x22,22*REGBYTES(a0) + LOAD x23,23*REGBYTES(a0) + LOAD x24,24*REGBYTES(a0) + LOAD x25,25*REGBYTES(a0) + LOAD x26,26*REGBYTES(a0) + LOAD x27,27*REGBYTES(a0) + LOAD x28,28*REGBYTES(a0) + LOAD x29,29*REGBYTES(a0) + LOAD x30,30*REGBYTES(a0) + LOAD x31,31*REGBYTES(a0) + # restore a0 last + LOAD x10,10*REGBYTES(a0) + + + .endm +.macro save_tf + # save gprs + STORE x1,1*REGBYTES(x2) + STORE x3,3*REGBYTES(x2) + STORE x4,4*REGBYTES(x2) + STORE x5,5*REGBYTES(x2) + STORE x6,6*REGBYTES(x2) + STORE x7,7*REGBYTES(x2) + STORE x8,8*REGBYTES(x2) + STORE x9,9*REGBYTES(x2) + STORE x10,10*REGBYTES(x2) + STORE x11,11*REGBYTES(x2) + STORE x12,12*REGBYTES(x2) + STORE x13,13*REGBYTES(x2) + STORE x14,14*REGBYTES(x2) + STORE x15,15*REGBYTES(x2) + STORE x16,16*REGBYTES(x2) + STORE x17,17*REGBYTES(x2) + STORE x18,18*REGBYTES(x2) + STORE x19,19*REGBYTES(x2) + STORE x20,20*REGBYTES(x2) + STORE x21,21*REGBYTES(x2) + STORE x22,22*REGBYTES(x2) + STORE x23,23*REGBYTES(x2) + STORE x24,24*REGBYTES(x2) + STORE x25,25*REGBYTES(x2) + STORE x26,26*REGBYTES(x2) + STORE x27,27*REGBYTES(x2) + STORE x28,28*REGBYTES(x2) + STORE x29,29*REGBYTES(x2) + STORE x30,30*REGBYTES(x2) + STORE x31,31*REGBYTES(x2) + + # get sr, epc, badvaddr, cause + csrrw t0,mscratch,x0 + csrr s0,mstatus + csrr t1,mepc + csrr t2,mbadaddr + csrr t3,mcause + STORE t0,2*REGBYTES(x2) + STORE s0,32*REGBYTES(x2) + STORE t1,33*REGBYTES(x2) + STORE t2,34*REGBYTES(x2) + STORE t3,35*REGBYTES(x2) + + # get faulting insn, if it wasn't a fetch-related trap + li x5,-1 + STORE x5,36*REGBYTES(x2) +1: + .endm + + .text + .global supervisor_trap_entry +supervisor_trap_entry: + csrw mscratch, sp + # load in the top of the machine stack + la sp, 0x80FFF0 + 1:addi sp,sp,-320 + save_tf + move a0,sp + jal trap_handler + .global trap_entry +trap_entry: + csrw mscratch, sp + 1:addi sp,sp,-320 + save_tf_ + move a0,sp + jal trap_handler + .global supervisor_call_return +supervisor_call_return: + csrr a0, mscratch + restore_regs + eret # go back into supervisor call + .global machine_call_return +machine_call_return: + csrr a0, mscratch + restore_regs + eret # go back into machine call

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coreboot-gerrit August 2015