coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: edid: fix know_modes timing error
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11397 -gerrit commit 5b2d003896e528acf15a48d6f411e4584add9a33 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Tue Aug 18 04:18:09 2015 -0500 edid: fix know_modes timing error BRANCH=None BUG=chrome-os-partner:43789 TEST=Mickey board, 640x480@60Hz display normally Change-Id: Iea298302fe1124edbef157d1d81c12610402e9c7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 0209422efe52c45cab3c0d787b27352f63578e76 Original-Change-Id: Idf4c8cd9f2da3c5daa589973d831a506ff549b8b Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293994 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index be3d906..68cc38a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -987,22 +987,22 @@ static void dump_breakdown(unsigned char *edid) static struct edid_mode known_modes[NUM_KNOWN_MODES] = { [EDID_MODE_640x480_60Hz] = { .name = "640x480@60Hz", .pixel_clock = 25175, .refresh = 60, - .ha = 640, .hbl = 160, .hso = 16, .hborder = 96, + .ha = 640, .hbl = 160, .hso = 16, .hspw = 96, .va = 480, .vbl = 45, .vso = 10, .vspw = 2, .phsync = '-', .pvsync = '-' }, [EDID_MODE_720x480_60Hz] = { .name = "720x480@60Hz", .pixel_clock = 27000, .refresh = 60, - .ha = 720, .hbl = 78, .hso = 16, .hborder = 62, + .ha = 720, .hbl = 138, .hso = 16, .hspw = 62, .va = 480, .vbl = 45, .vso = 9, .vspw = 6, .phsync = '-', .pvsync = '-' }, [EDID_MODE_1280x720_60Hz] = { .name = "1280x720@60Hz", .pixel_clock = 74250, .refresh = 60, - .ha = 1280, .hbl = 370, .hso = 110, .hborder = 40, + .ha = 1280, .hbl = 370, .hso = 110, .hspw = 40, .va = 720, .vbl = 30, .vso = 5, .vspw = 20, .phsync = '+', .pvsync = '+' }, [EDID_MODE_1920x1080_60Hz] = { .name = "1920x1080@60Hz", .pixel_clock = 148500, .refresh = 60, - .ha = 1920, .hbl = 280, .hso = 88, .hborder = 44, + .ha = 1920, .hbl = 280, .hso = 88, .hspw = 44, .va = 1080, .vbl = 45, .vso = 4, .vspw = 5, .phsync = '+', .pvsync = '+' }, };

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New patch to review for coreboot: veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odt
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11396 -gerrit commit 1b16c3123659a647bf3493b38f35873e9c343297 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Aug 13 10:52:52 2015 +0800 veyron: mickey sdram-lpddr3-samsung-2GB.inc enable odt only modify the MR3 value, there will always be some mickey not working properly. After enable ODT, we use many mickey do tests, now functioning properly. BRANCH=None BUG=chrome-os-partner:43626 TEST=My mickey now boots up Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 681c169d59f5638d35b777eb2b7543e3b0dd90c8 Original-Change-Id: Ieb2b8a56054f91b6be81260e4c574425fb72fed3 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293324 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org> Original-Trybot-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-(cherry picked from commit 5397c2f32f5851b9f514b0bd2ae68999a77cabbf) Original-Reviewed-on: https://chromium-review.googlesource.com/294126 Change-Id: Icb3c839bebebfcae54fc6e96e9958c7020d49eff --- .../google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc index 666b12f..89dfd69 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -75,5 +75,5 @@ .dramtype = LPDDR3, .num_channels = 2, .stride = 9, - .odt = 0, + .odt = 1, },

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New patch to review for coreboot: arm64: declare do_dcsw_op as function
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11395 -gerrit commit a829c2059a63f84ba5e977e81d937c9f4605f93a Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Thu Aug 13 10:48:49 2015 +0800 arm64: declare do_dcsw_op as function do_dcsw_op is coded as a label, it's possible that linker will place do_dcsw_op on unaligned address. To avoid this situation, we declare do_dcsw_op as a function. Also explicitly set the 2nd argument of ENTRY_WITH_ALIGN(name, bits) to 2. do_dcsw_op: cbz x3, exit c103d: b40003e3 cbz x3, c10b9 <exit> mov x10, xzr c1041: aa1f03ea mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address BRANCH=none BUG=none TEST=build and check do_dcsw_op in elf file Change-Id: Ieb5f4188d6126ac9f6ddb0bfcc67452f79de94ad Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 4ee26b76089fab82cf4fb9b21c9f15b29e57b453 Original-Change-Id: Id331e8ecab7ea8782e97c10b13e8810955747a51 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> --- src/arch/arm64/armv8/cache_helpers.S | 3 ++- src/arch/arm64/include/arch/asm.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/armv8/cache_helpers.S b/src/arch/arm64/armv8/cache_helpers.S index dc74dad..b94bc30 100644 --- a/src/arch/arm64/armv8/cache_helpers.S +++ b/src/arch/arm64/armv8/cache_helpers.S @@ -54,7 +54,7 @@ b do_dcsw_op .endm -do_dcsw_op: +ENTRY(do_dcsw_op) cbz x3, exit mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address @@ -92,6 +92,7 @@ level_done: isb exit: ret +ENDPROC(do_dcsw_op) .macro dcsw_loop _op loop2_\_op: diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index 851f3f9..878509e 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -30,7 +30,7 @@ .align bits; \ name: -#define ENTRY(name) ENTRY_WITH_ALIGN(name, 0) +#define ENTRY(name) ENTRY_WITH_ALIGN(name, 2) #define END(name) \ .size name, .-name

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New patch to review for coreboot: t210: lp0_resume: apply mbist WAR for audio on resume
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11394 -gerrit commit 9142ae593e276ebbd43838885aedf1bd7946e2f7 Author: Christopher Freeman <cfreeman(a)nvidia.com> Date: Fri Aug 14 15:11:26 2015 -0700 t210: lp0_resume: apply mbist WAR for audio on resume When power is cut/restored to audio block, mbist workaround must be reapplied or I2S will not function. Handle this in lp0 resume firmware with the rest of the mbist WAR. This sequence for audio is also present in boot block code for T210. BUG=chrome-os-partner:41249 BRANCH=None TEST=lp0 suspend/resume with audio playback Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 84933da8188f8263c19f38ba37e88e32ca46cb3d Original-Change-Id: Ia6432e8556ee64f528d94f2dc3279b152294e132 Original-Signed-off-by: Christopher Freeman <cfreeman(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293618 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Anatol Pomazau <anatol(a)google.com> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Anatol Pomazau <anatol(a)google.com> Original-Tested-by: Anatol Pomazau <anatol(a)google.com> Original-(cherry picked from commit 1e529c3e2ff929975fd654ef75396bc98d3b785c) Original-Reviewed-on: https://chromium-review.googlesource.com/293886 Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I3e72bc10f7e2bea2fa5f946e25803a7928ce9276 --- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 69 ++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 5ef03d0..956e8c5 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -31,7 +31,8 @@ enum { MC_CTLR_BASE = 0x70019000, FUSE_BASE = 0x7000F800, EMC_BASE = 0x7001B000, - I2C5_BASE = 0x7000D000 + I2C5_BASE = 0x7000D000, + I2S_BASE = 0x702d1000 }; /* UP tag registers. */ @@ -704,15 +705,77 @@ static void set_pmacro_training_wrptr(void) write32(pmacro_cfg_pm_global, ENABLE_CFG_BYTES); } +static uint32_t *i2s_0_master = (void *)(I2S_BASE + 0x0a0); +static uint32_t *i2s_1_master = (void *)(I2S_BASE + 0x1a0); +static uint32_t *i2s_2_master = (void *)(I2S_BASE + 0x2a0); +static uint32_t *i2s_3_master = (void *)(I2S_BASE + 0x3a0); +static uint32_t *i2s_4_master = (void *)(I2S_BASE + 0x4a0); + +static uint32_t *i2s_0_slcg = (void *)(I2S_BASE + 0x088); +static uint32_t *i2s_1_slcg = (void *)(I2S_BASE + 0x188); +static uint32_t *i2s_2_slcg = (void *)(I2S_BASE + 0x288); +static uint32_t *i2s_3_slcg = (void *)(I2S_BASE + 0x388); +static uint32_t *i2s_4_slcg = (void *)(I2S_BASE + 0x488); + +static uint32_t *clk_rst_ape_clear = (void *)(CLK_RST_BASE + 0x2ac); +static uint32_t *clk_rst_ape_set = (void *)(CLK_RST_BASE + 0x2a8); + static void mbist_workaround(void) { uint32_t clks_to_be_cleared; + uint32_t i2s_read; + + write32(clk_rst_ape_clear, 0x40); + udelay(2); + + i2s_read = read32(i2s_0_master); + i2s_read |= 0x400; + write32(i2s_0_master, i2s_read); + + i2s_read = read32(i2s_0_slcg); + i2s_read &= ~1; + write32(i2s_0_slcg, i2s_read); + + i2s_read = read32(i2s_1_master); + i2s_read |= 0x400; + write32(i2s_1_master, i2s_read); + + i2s_read = read32(i2s_1_slcg); + i2s_read &= ~1; + write32(i2s_1_slcg, i2s_read); + + i2s_read = read32(i2s_2_master); + i2s_read |= 0x400; + write32(i2s_2_master, i2s_read); + + i2s_read = read32(i2s_2_slcg); + i2s_read &= ~1; + write32(i2s_2_slcg, i2s_read); + + i2s_read = read32(i2s_3_master); + i2s_read |= 0x400; + write32(i2s_3_master, i2s_read); + + i2s_read = read32(i2s_3_slcg); + i2s_read &= ~1; + write32(i2s_3_slcg, i2s_read); + + i2s_read = read32(i2s_4_master); + i2s_read |= 0x400; + write32(i2s_4_master, i2s_read); + + i2s_read = read32(i2s_4_slcg); + i2s_read &= ~1; + write32(i2s_4_slcg, i2s_read); + + udelay(2); write32(clk_rst_lvl2_clk_gate_ovra_ptr, 0); write32(clk_rst_lvl2_clk_gate_ovrb_ptr, 0); - write32(clk_rst_lvl2_clk_gate_ovrc_ptr, 0); + write32(clk_rst_lvl2_clk_gate_ovrc_ptr, 0x00000002); write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */ - write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0); + write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0x00000c00); + clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr); clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0;

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New patch to review for coreboot: rockchip: rk3288: multiple NPLL rate in pll_para_config
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11393 -gerrit commit 6064ce9bedfa40049ca08b0d3eaafb6147ec69b8 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Mon Jul 27 08:50:36 2015 -0500 rockchip: rk3288: multiple NPLL rate in pll_para_config Due to HDMI need to set dclk_rate to 27Mhz, and we can't caclu a suitable config paramters for this rate, so we need to multiple rate unless the vco larger then VCO_MAX. When NPLL rate multiple to 54MHz, pll_para_config could caclu a right paramters, and I have verify the clock jitter is okay to HDMI output. Jitter Reports: Dclk Rate NPLL Rate nr/no/nf jitter Margin 27MHz 54MHz 2/10/45 449.0ps +51.0% BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, show right recovery picture on TV, and 480p clock jitter test passed Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c Original-Reviewed-on: https://chromium-review.googlesource.com/288416 Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290331 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 878c194..e4d2e3e 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -498,7 +498,7 @@ void rkclk_configure_tsadc(unsigned int hz) RK_CLRSETBITS(0x3f << 0, (div - 1) << 0)); } -static int pll_para_config(u32 freq_hz, struct pll_div *div) +static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div) { u32 ref_khz = OSC_HZ / KHz, nr, nf = 0; u32 fref_khz; @@ -512,17 +512,27 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) printk(BIOS_ERR, "%s: the frequency can not be 0 Hz\n", __func__); return -1; } + no = div_round_up(VCO_MIN_KHZ, freq_khz); + if (ext_div) { + *ext_div = div_round_up(no, max_no); + no = div_round_up(no, *ext_div); + } /* only even divisors (and 1) are supported */ if (no > 1) no = div_round_up(no, 2) * 2; + vco_khz = freq_khz * no; + if (ext_div) + vco_khz *= *ext_div; + if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { printk(BIOS_ERR, "%s: Cannot find out a supported VCO" " for Frequency (%uHz).\n", __func__, freq_hz); return -1; } + div->no = no; best_diff_khz = vco_khz; @@ -608,8 +618,9 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) { struct pll_div npll_config = {0}; + u32 lcdc_div; - if (pll_para_config(dclk_hz, &npll_config)) + if (pll_para_config(dclk_hz, &npll_config, &lcdc_div)) return -1; /* npll enter slow-mode */ @@ -633,12 +644,14 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) switch (vop_id) { case 0: write32(&cru_ptr->cru_clksel_con[27], - RK_CLRSETBITS(0xff << 8 | 3 << 0, 0 << 8 | 2 << 0)); + RK_CLRSETBITS(0xff << 8 | 3 << 0, + (lcdc_div - 1) << 8 | 2 << 0)); break; case 1: write32(&cru_ptr->cru_clksel_con[29], - RK_CLRSETBITS(0xff << 8 | 3 << 6, 0 << 8 | 2 << 6)); + RK_CLRSETBITS(0xff << 8 | 3 << 6, + (lcdc_div - 1) << 8 | 2 << 6)); break; } return 0;

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New patch to review for coreboot: rk3288: Set HDMI display mode to 480p
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11392 -gerrit commit 7de41aaac35b625a97db8b0dc2d67442acfa6eb1 Author: Yakir Yang <ykk(a)rock-chips.com> Date: Wed Jul 29 08:54:14 2015 -0500 rk3288: Set HDMI display mode to 480p If an HDMI display is detected (EDID can be read), set the display mode to 480p. If for some reason 480p is not supported then we'll fall back to the automatically detected display mode. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=dev mode screen shows up on Mickey at 480p resolution Change-Id: I2c431eff6673392d3c09e1b66c66ba12ecc6eeb0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 76203a683c4501f368c50fe24101f68746ddb7f0 Original-Change-Id: I90dea37daa2d78628230d7d47f7ef0e917cbd7bb Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290554 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/hdmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index e5bebe3..a520399 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -793,6 +793,10 @@ int rk_hdmi_get_edid(struct edid *edid) if (decode_edid(edid_buf, edid_size, edid)) hdmi_debug("failed to decode edid.\n"); + /* Try 480p for best compatibility. */ + if (set_display_mode(edid, EDID_MODE_640x480_60Hz)) + hdmi_debug("failed to set mode to 640x480@60Hz\n"); + return 0; }

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New patch to review for coreboot: rk3288: Ignore EDID errors for HDMI
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11391 -gerrit commit 74928b5fbe7e5ea8eb117ad6f7d9826c83466f0f Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 13 15:43:55 2015 -0700 rk3288: Ignore EDID errors for HDMI Assume that HDMI implies usage of an external display, and that we want to try bringing up display if we can read an EDID. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=none; need a display with corrupt EDID to test with Change-Id: I11cc61140d905d70798a7b46db7847f3a1b3c886 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: ace7773623eac57f068ecd50baa9108ce028cf1b Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I9e22984a98b1a5f8cd9645b92dc9b87e8d968f01 Original-Reviewed-on: https://chromium-review.googlesource.com/293548 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/hdmi.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index a7a9c40..e5bebe3 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -788,11 +788,10 @@ int rk_hdmi_get_edid(struct edid *edid) edid_size += HDMI_EDID_BLOCK_SIZE; } - ret = decode_edid(edid_buf, edid_size, edid); - if (ret) { + /* Assume usage of HDMI implies an external display in which case + * we should be lenient about errors that the EDID decoder finds. */ + if (decode_edid(edid_buf, edid_size, edid)) hdmi_debug("failed to decode edid.\n"); - return -1; - } return 0; }

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New patch to review for coreboot: edid: add function to manually specify mode
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11390 -gerrit commit 378d042ee8d89d5606d495c5bd11e9263f4ab566 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 7 18:41:37 2015 -0700 edid: add function to manually specify mode This patch will let you to choose a favourite mode to display, while not just taking the edid detail timing. But not all modes are able to set, only modes that are in established or standard timing, and we only support a few common common resolutions for now. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=tested dev mode on Mickey at 640x480@60Hz Change-Id: I8a9dedfe08057d42d85b8ca129935a258cb26762 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 090583f90ff720d88e5cfe69fcb2d541c716f0e6 Original-Change-Id: Iaa8c9a6fad106ee792f7cd1a0ac77e3dcbadf481 Original-Signed-off-by: Yakir Yang <ykk(a)rock-chips.com> Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289671 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/include/edid.h | 9 +++++++- src/lib/edid.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 2 deletions(-) diff --git a/src/include/edid.h b/src/include/edid.h index 3de4dbc..72ae7f3 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -21,8 +21,13 @@ #define EDID_H enum edid_modes { - EDID_MODE_AUTO = 0, EDID_MODE_640x480_60Hz, + EDID_MODE_720x480_60Hz, + EDID_MODE_1280x720_60Hz, + EDID_MODE_1920x1080_60Hz, + NUM_KNOWN_MODES, + + EDID_MODE_AUTO }; struct edid_mode { @@ -75,6 +80,7 @@ struct edid { unsigned int panel_bits_per_pixel; /* used to compute timing for graphics chips. */ struct edid_mode mode; + u8 mode_is_supported[NUM_KNOWN_MODES]; unsigned int link_clock; /* 3 variables needed for coreboot framebuffer. * In most cases, they are the same as the ha @@ -89,5 +95,6 @@ struct edid { /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr); +int set_display_mode(struct edid *edid, enum edid_modes mode); #endif /* EDID_H */ diff --git a/src/lib/edid.c b/src/lib/edid.c index ed3565c..be3d906 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -977,6 +977,52 @@ static void dump_breakdown(unsigned char *edid) } /* + * Lookup table of some well-known modes that can be useful in case the + * auto-detected mode is unsuitable. + * ha = hdisplay; va = vdisplay; + * hbl = htotal - hdisplay; vbl = vtotal - vdisplay; + * hso = hsync_start - hdsiplay; vso = vsync_start - vdisplay; + * hspw = hsync_end - hsync_start; vspw = vsync_end - vsync_start; + */ +static struct edid_mode known_modes[NUM_KNOWN_MODES] = { + [EDID_MODE_640x480_60Hz] = { + .name = "640x480@60Hz", .pixel_clock = 25175, .refresh = 60, + .ha = 640, .hbl = 160, .hso = 16, .hborder = 96, + .va = 480, .vbl = 45, .vso = 10, .vspw = 2, + .phsync = '-', .pvsync = '-' }, + [EDID_MODE_720x480_60Hz] = { + .name = "720x480@60Hz", .pixel_clock = 27000, .refresh = 60, + .ha = 720, .hbl = 78, .hso = 16, .hborder = 62, + .va = 480, .vbl = 45, .vso = 9, .vspw = 6, + .phsync = '-', .pvsync = '-' }, + [EDID_MODE_1280x720_60Hz] = { + .name = "1280x720@60Hz", .pixel_clock = 74250, .refresh = 60, + .ha = 1280, .hbl = 370, .hso = 110, .hborder = 40, + .va = 720, .vbl = 30, .vso = 5, .vspw = 20, + .phsync = '+', .pvsync = '+' }, + [EDID_MODE_1920x1080_60Hz] = { + .name = "1920x1080@60Hz", .pixel_clock = 148500, .refresh = 60, + .ha = 1920, .hbl = 280, .hso = 88, .hborder = 44, + .va = 1080, .vbl = 45, .vso = 4, .vspw = 5, + .phsync = '+', .pvsync = '+' }, +}; + +int set_display_mode(struct edid *edid, enum edid_modes mode) +{ + if (mode == EDID_MODE_AUTO) + return 0; + + if (edid->mode_is_supported[mode]) { + printk(BIOS_DEBUG, "Forcing mode %s\n", known_modes[mode].name); + edid->mode = known_modes[mode]; + return 0; + } + + printk(BIOS_ERR, "Requested display mode not supported.\n"); + return -1; +} + +/* * Given a raw edid bloc, decode it into a form * that other parts of coreboot can use -- mainly * graphics bringup functions. The raw block is @@ -986,7 +1032,7 @@ static void dump_breakdown(unsigned char *edid) */ int decode_edid(unsigned char *edid, int size, struct edid *out) { - int analog, i; + int analog, i, j; struct edid_context c = { .has_valid_cvt = 1, .has_valid_dummy_block = 1, @@ -1210,6 +1256,14 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) printk(BIOS_SPEW, " %dx%d@%dHz\n", established_timings[i].x, established_timings[i].y, established_timings[i].refresh); } + + for (j = 0; j < NUM_KNOWN_MODES; j++) { + if (known_modes[j].ha == established_timings[i].x && + known_modes[j].va == established_timings[i].y && + known_modes[j].refresh == established_timings[i].refresh) + out->mode_is_supported[j] = 1; + } + } printk(BIOS_SPEW, "Standard timings supported:\n"); @@ -1245,6 +1299,11 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) refresh = 60 + (b2 & 0x3f); printk(BIOS_SPEW, " %dx%d@%dHz\n", x, y, refresh); + for (j = 0; j < NUM_KNOWN_MODES; j++) { + if (known_modes[j].ha == x && known_modes[j].va == y && + known_modes[j].refresh == refresh) + out->mode_is_supported[j] = 1; + } } /* detailed timings */

1 0

New patch to review for coreboot: edid: Memset output earlier in decode_edid()
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11389 -gerrit commit 208d840e531e88cb52b30b8db5fca77951537488 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 13 15:51:00 2015 -0700 edid: Memset output earlier in decode_edid() This ensures the output buffer is initialized before exiting decode_edid() so that if the return value is ignored in higher-level logic (like when dealing with external displays) we don't leave the struct filled with garbage. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=none Change-Id: I557e2495157458342db6d8b0b1ecb39f7267f61f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: bb12dca133576543efa4d3bcc9aadf85d37c8b71 Original-Change-Id: I697436fffadc7dd3af239436061975165a97ec8c Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293547 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/edid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 22f3f0e..ed3565c 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1001,12 +1001,13 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) dump_breakdown(edid); + memset(out, 0, sizeof(*out)); + if (!edid || memcmp(edid, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8)) { printk(BIOS_SPEW, "No header found\n"); return 1; } - memset(out, 0, sizeof(*out)); if (manufacturer_name(edid + 0x08)) c.manufacturer_name_well_formed = 1;

1 0

New patch to review for coreboot: edid: Use edid_mode struct to reduce redundancy
by Patrick Georgi 27 Aug '15

27 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11388 -gerrit commit 0e994e564a9a6c344298ba98caf361f2bb51854e Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jul 30 18:49:48 2015 -0700 edid: Use edid_mode struct to reduce redundancy This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/intel/gma/display.c | 27 ++++++++++----------- src/include/edid.h | 39 ++++++++++++++++++++----------- src/lib/edid.c | 49 ++++++++++++++++++++------------------- src/mainboard/google/falco/gma.c | 4 ++-- src/mainboard/google/peppy/gma.c | 12 +++++----- src/soc/nvidia/tegra124/dp.c | 18 +++++++------- src/soc/nvidia/tegra132/dp.c | 18 +++++++------- src/soc/nvidia/tegra210/dp.c | 18 +++++++------- src/soc/rockchip/rk3288/display.c | 8 +++---- src/soc/rockchip/rk3288/hdmi.c | 36 ++++++++++++++-------------- src/soc/rockchip/rk3288/vop.c | 32 ++++++++++++------------- 11 files changed, 138 insertions(+), 123 deletions(-) diff --git a/src/drivers/intel/gma/display.c b/src/drivers/intel/gma/display.c index 5c8e886..afcec91 100644 --- a/src/drivers/intel/gma/display.c +++ b/src/drivers/intel/gma/display.c @@ -38,6 +38,7 @@ void compute_display_params(struct intel_dp *dp) { struct edid *edid = &(dp->edid); + struct edid_mode *mode = &edid->mode; /* step 1: get the constants in the dp struct set up. */ dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK; @@ -51,22 +52,22 @@ void compute_display_params(struct intel_dp *dp) dp->stride = edid->bytes_per_line; - dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); + dp->htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); + dp->hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - dp->hsync = (edid->ha + edid->hso - 1) | - ((edid->ha + edid->hso + edid->hspw - 1) << 16); + dp->hsync = (mode->ha + mode->hso - 1) | + ((mode->ha + mode->hso + mode->hspw - 1) << 16); - dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); + dp->vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); + dp->vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - dp->vsync = (edid->va + edid->vso - 1) | - ((edid->va + edid->vso + edid->vspw - 1) << 16); + dp->vsync = (mode->va + mode->vso - 1) | + ((mode->va + mode->vso + mode->vspw - 1) << 16); /* PIPEASRC is wid-1 x ht-1 */ - dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1); + dp->pipesrc = (mode->ha-1)<<16 | (mode->va-1); dp->pfa_pos = 0; @@ -75,7 +76,7 @@ void compute_display_params(struct intel_dp *dp) if (dp->gen == 6) dp->pfa_ctl |= PF_PIPE_SEL_IVB(dp->pipe); - dp->pfa_sz = (edid->ha << 16) | (edid->va); + dp->pfa_sz = (mode->ha << 16) | (mode->va); /* step 3. Call the linux code we pulled in. */ dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel, @@ -84,15 +85,15 @@ void compute_display_params(struct intel_dp *dp) dp->type, dp->lane_count, dp->pfa_sz, - dp->edid.phsync == '+'?1:0, - dp->edid.pvsync == '+'?1:0); + mode->phsync == '+'?1:0, + mode->pvsync == '+'?1:0); dp->transcoder = intel_ddi_get_transcoder(dp->port, dp->pipe); intel_dp_compute_m_n(edid->panel_bits_per_pixel, dp->lane_count, - dp->edid.pixel_clock, + dp->edid.mode.pixel_clock, dp->edid.link_clock, &dp->m_n); diff --git a/src/include/edid.h b/src/include/edid.h index 1422c1e..3de4dbc 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -20,6 +20,31 @@ #ifndef EDID_H #define EDID_H +enum edid_modes { + EDID_MODE_AUTO = 0, + EDID_MODE_640x480_60Hz, +}; + +struct edid_mode { + const char *name; + unsigned int pixel_clock; + unsigned int refresh; + unsigned int ha; + unsigned int hbl; + unsigned int hso; + unsigned int hspw; + unsigned int hborder; + unsigned int va; + unsigned int vbl; + unsigned int vso; + unsigned int vspw; + unsigned int vborder; + unsigned char phsync; + unsigned char pvsync; + unsigned int x_mm; + unsigned int y_mm; +}; + /* structure for communicating EDID information from a raw EDID block to * higher level functions. * The size of the data types is not critical, so we leave them as @@ -49,20 +74,8 @@ struct edid { */ unsigned int panel_bits_per_pixel; /* used to compute timing for graphics chips. */ - unsigned char phsync; - unsigned char pvsync; - unsigned int pixel_clock; + struct edid_mode mode; unsigned int link_clock; - unsigned int ha; - unsigned int hbl; - unsigned int hso; - unsigned int hspw; - unsigned int hborder; - unsigned int va; - unsigned int vbl; - unsigned int vso; - unsigned int vspw; - unsigned int vborder; /* 3 variables needed for coreboot framebuffer. * In most cases, they are the same as the ha * and va variables, but not always, as in the diff --git a/src/lib/edid.c b/src/lib/edid.c index e08535d..22f3f0e 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -445,19 +445,19 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, if (! c->did_detailed_timing){ /* Edid contains pixel clock in terms of 10KHz */ - out->pixel_clock = (x[0] + (x[1] << 8)) * 10; + out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10; extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8)); - out->ha = (x[2] + ((x[4] & 0xF0) << 4)); - out->hbl = (x[3] + ((x[4] & 0x0F) << 8)); - out->hso = (x[8] + ((x[11] & 0xC0) << 2)); - out->hspw = (x[9] + ((x[11] & 0x30) << 4)); - out->hborder = x[15]; - out->va = (x[5] + ((x[7] & 0xF0) << 4)); - out->vbl = (x[6] + ((x[7] & 0x0F) << 8)); - out->vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); - out->vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); - out->vborder = x[16]; + out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4)); + out->mode.hbl = (x[3] + ((x[4] & 0x0F) << 8)); + out->mode.hso = (x[8] + ((x[11] & 0xC0) << 2)); + out->mode.hspw = (x[9] + ((x[11] & 0x30) << 4)); + out->mode.hborder = x[15]; + out->mode.va = (x[5] + ((x[7] & 0xF0) << 4)); + out->mode.vbl = (x[6] + ((x[7] & 0x0F) << 8)); + out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2)); + out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4)); + out->mode.vborder = x[16]; /* set up some reasonable defaults for payloads. * We observe that most modern chipsets we work with * tend to support rgb888 without regard to the @@ -475,11 +475,11 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, */ out->framebuffer_bits_per_pixel = 32; - out->x_resolution = ALIGN(out->ha * + out->x_resolution = ALIGN(out->mode.ha * ((out->framebuffer_bits_per_pixel + 7) / 8), 64) / (out->framebuffer_bits_per_pixel/8); - out->y_resolution = out->va; - out->bytes_per_line = ALIGN(out->ha * + out->y_resolution = out->mode.va; + out->bytes_per_line = ALIGN(out->mode.ha * ((out->framebuffer_bits_per_pixel + 7)/8), 64); printk(BIOS_SPEW, "Did detailed timing\n"); @@ -499,8 +499,8 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, extra_info.syncmethod = ""; break; } - out->pvsync = (x[17] & (1 << 2)) ? '+' : '-'; - out->phsync = (x[17] & (1 << 1)) ? '+' : '-'; + out->mode.pvsync = (x[17] & (1 << 2)) ? '+' : '-'; + out->mode.phsync = (x[17] & (1 << 1)) ? '+' : '-'; switch (x[17] & 0x61) { case 0x20: extra_info.stereo = "field sequential L/R"; @@ -529,17 +529,18 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, " %04x %04x %04x %04x hborder %x\n" " %04x %04x %04x %04x vborder %x\n" " %chsync %cvsync%s%s %s\n", - out->pixel_clock, + out->mode.pixel_clock, extra_info.x_mm, extra_info.y_mm, - out->ha, out->ha + out->hso, out->ha + out->hso + out->hspw, - out->ha + out->hbl, out->hborder, - out->va, out->va + out->vso, out->va + out->vso + out->vspw, - out->va + out->vbl, out->vborder, - out->phsync, out->pvsync, + out->mode.ha, out->mode.ha + out->mode.hso, + out->mode.ha + out->mode.hso + out->mode.hspw, + out->mode.ha + out->mode.hbl, out->mode.hborder, + out->mode.va, out->mode.va + out->mode.vso, + out->mode.va + out->mode.vso + out->mode.vspw, + out->mode.va + out->mode.vbl, out->mode.vborder, + out->mode.phsync, out->mode.pvsync, extra_info.syncmethod, x[17] & 0x80 ?" interlaced" : "", - extra_info.stereo - ); + extra_info.stereo); return 1; } diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c index 68f1e45..6c936d7 100644 --- a/src/mainboard/google/falco/gma.c +++ b/src/mainboard/google/falco/gma.c @@ -234,8 +234,8 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb) palette(); - pixels = dp->edid.ha * (dp->edid.va-4) * 4; - printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va); + pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4; + printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va); test_gfx(dp); diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c index 735ad65..4e2fc5f 100644 --- a/src/mainboard/google/peppy/gma.c +++ b/src/mainboard/google/peppy/gma.c @@ -151,12 +151,12 @@ static void test_gfx(struct intel_dp *dp) are made right. Thus, to be used only for testing, not otherwise */ - for (i = 0; i < (dp->edid.va - 4); i++) { + for (i = 0; i < (dp->edid.mode.va - 4); i++) { u32 *l; int j; u32 tcolor = 0x0ff; - for (j = 0; j < (dp->edid.ha-4); j++) { - if (j == (dp->edid.ha/2)) { + for (j = 0; j < (dp->edid.mode.ha-4); j++) { + if (j == (dp->edid.mode.ha/2)) { tcolor = 0xff00; } l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor)); @@ -246,7 +246,7 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb) compute_display_params(dp); printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n", - dp->edid.pixel_clock, dp->edid.link_clock); + dp->edid.mode.pixel_clock, dp->edid.link_clock); intel_ddi_set_pipe_settings(dp); @@ -254,8 +254,8 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb) palette(); - pixels = dp->edid.ha * (dp->edid.va-4) * 4; - printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va); + pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4; + printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va); test_gfx(dp); set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics); diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index b3dab75..3a3bce8 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -1328,17 +1328,17 @@ static void tegra_dp_update_config(struct tegra_dc_dp_data *dp, return; } - config->xres = edid.ha; - config->yres = edid.va; - config->pixel_clock = edid.pixel_clock * 1000; + config->xres = edid.mode.ha; + config->yres = edid.mode.va; + config->pixel_clock = edid.mode.pixel_clock * 1000; - config->hfront_porch = edid.hso; - config->hsync_width = edid.hspw; - config->hback_porch = edid.hbl - edid.hso - edid.hspw; + config->hfront_porch = edid.mode.hso; + config->hsync_width = edid.mode.hspw; + config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw; - config->vfront_porch = edid.vso; - config->vsync_width = edid.vspw; - config->vback_porch = edid.vbl - edid.vso - edid.vspw; + config->vfront_porch = edid.mode.vso; + config->vsync_width = edid.mode.vspw; + config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw; /** * Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32, diff --git a/src/soc/nvidia/tegra132/dp.c b/src/soc/nvidia/tegra132/dp.c index 9714d44..17118e3 100644 --- a/src/soc/nvidia/tegra132/dp.c +++ b/src/soc/nvidia/tegra132/dp.c @@ -1367,18 +1367,18 @@ static void tegra_dp_update_config(struct tegra_dc_dp_data *dp, return; } - config->xres = config->display_xres = edid.ha; - config->yres = config->display_yres = edid.va; + config->xres = config->display_xres = edid.mode.ha; + config->yres = config->display_yres = edid.mode.va; - config->pixel_clock = edid.pixel_clock * 1000; + config->pixel_clock = edid.mode.pixel_clock * 1000; - config->hfront_porch = edid.hso; - config->hsync_width = edid.hspw; - config->hback_porch = edid.hbl - edid.hso - edid.hspw; + config->hfront_porch = edid.mode.hso; + config->hsync_width = edid.mode.hspw; + config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw; - config->vfront_porch = edid.vso; - config->vsync_width = edid.vspw; - config->vback_porch = edid.vbl - edid.vso - edid.vspw; + config->vfront_porch = edid.mode.vso; + config->vsync_width = edid.mode.vspw; + config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw; /** * Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32, diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index ea6dbca..e047584 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -1367,18 +1367,18 @@ static void tegra_dp_update_config(struct tegra_dc_dp_data *dp, return; } - config->xres = config->display_xres = edid.ha; - config->yres = config->display_yres = edid.va; + config->xres = config->display_xres = edid.mode.ha; + config->yres = config->display_yres = edid.mode.va; - config->pixel_clock = edid.pixel_clock * 1000; + config->pixel_clock = edid.mode.pixel_clock * 1000; - config->hfront_porch = edid.hso; - config->hsync_width = edid.hspw; - config->hback_porch = edid.hbl - edid.hso - edid.hspw; + config->hfront_porch = edid.mode.hso; + config->hsync_width = edid.mode.hspw; + config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw; - config->vfront_porch = edid.vso; - config->vsync_width = edid.vspw; - config->vback_porch = edid.vbl - edid.vso - edid.vspw; + config->vfront_porch = edid.mode.vso; + config->vsync_width = edid.mode.vspw; + config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw; /** * Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32, diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index d241e3e..02526a4 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -93,15 +93,15 @@ void rk_display_init(device_t dev, u32 lcdbase, return; } - if (rkclk_configure_vop_dclk(conf->vop_id, edid.pixel_clock * KHz)) { + if (rkclk_configure_vop_dclk(conf->vop_id, edid.mode.pixel_clock * KHz)) { printk(BIOS_WARNING, "config vop err\n"); return; } edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel; - edid.bytes_per_line = edid.ha * conf->framebuffer_bits_per_pixel / 8; - edid.x_resolution = edid.ha; - edid.y_resolution = edid.va; + edid.bytes_per_line = edid.mode.ha * conf->framebuffer_bits_per_pixel / 8; + edid.x_resolution = edid.mode.ha; + edid.y_resolution = edid.mode.va; rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid); diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 582c834..a7a9c40 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -494,11 +494,11 @@ static void hdmi_av_composer(const struct edid *edid) /* set up hdmi_fc_invidconf */ inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE; - inv_val |= ((edid->pvsync == '+') ? + inv_val |= ((edid->mode.pvsync == '+') ? HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); - inv_val |= ((edid->phsync == '+') ? + inv_val |= ((edid->mode.phsync == '+') ? HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); @@ -517,33 +517,33 @@ static void hdmi_av_composer(const struct edid *edid) write32(&hdmi_regs->fc_invidconf, inv_val); /* set up horizontal active pixel width */ - write32(&hdmi_regs->fc_inhactv1, edid->ha >> 8); - write32(&hdmi_regs->fc_inhactv0, edid->ha); + write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8); + write32(&hdmi_regs->fc_inhactv0, edid->mode.ha); /* set up vertical active lines */ - write32(&hdmi_regs->fc_invactv1, edid->va >> 8); - write32(&hdmi_regs->fc_invactv0, edid->va); + write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8); + write32(&hdmi_regs->fc_invactv0, edid->mode.va); /* set up horizontal blanking pixel region width */ - write32(&hdmi_regs->fc_inhblank1, edid->hbl >> 8); - write32(&hdmi_regs->fc_inhblank0, edid->hbl); + write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8); + write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl); /* set up vertical blanking pixel region width */ - write32(&hdmi_regs->fc_invblank, edid->vbl); + write32(&hdmi_regs->fc_invblank, edid->mode.vbl); /* set up hsync active edge delay width (in pixel clks) */ - write32(&hdmi_regs->fc_hsyncindelay1, edid->hso >> 8); - write32(&hdmi_regs->fc_hsyncindelay0, edid->hso); + write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8); + write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso); /* set up vsync active edge delay (in lines) */ - write32(&hdmi_regs->fc_vsyncindelay, edid->vso); + write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso); /* set up hsync active pulse width (in pixel clks) */ - write32(&hdmi_regs->fc_hsyncinwidth1, edid->hspw >> 8); - write32(&hdmi_regs->fc_hsyncinwidth0, edid->hspw); + write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8); + write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw); /* set up vsync active edge delay (in lines) */ - write32(&hdmi_regs->fc_vsyncinwidth, edid->vspw); + write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw); } /* hdmi initialization step b.4 */ @@ -613,11 +613,11 @@ static int hdmi_setup(const struct edid *edid) int ret; hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n", - edid->pixel_clock, edid->ha, edid->va); + edid->mode.pixel_clock, edid->mode.ha, edid->mode.va); hdmi_av_composer(edid); - ret = hdmi_phy_init(edid->pixel_clock); + ret = hdmi_phy_init(edid->mode.pixel_clock); if (ret) return ret; @@ -625,7 +625,7 @@ static int hdmi_setup(const struct edid *edid) hdmi_audio_fifo_reset(); hdmi_audio_set_format(); - hdmi_audio_set_samplerate(edid->pixel_clock); + hdmi_audio_set_samplerate(edid->mode.pixel_clock); hdmi_video_packetize(); hdmi_video_csc(); diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c index 30b73c2..784c6c7 100644 --- a/src/soc/rockchip/rk3288/vop.c +++ b/src/soc/rockchip/rk3288/vop.c @@ -39,12 +39,12 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) { u32 lb_mode; u32 rgb_mode; - u32 hactive = edid->ha; - u32 vactive = edid->va; - u32 hsync_len = edid->hspw; - u32 hback_porch = edid->hbl - edid->hso - edid->hspw; - u32 vsync_len = edid->vspw; - u32 vback_porch = edid->vbl - edid->vso - edid->vspw; + u32 hactive = edid->mode.ha; + u32 vactive = edid->mode.va; + u32 hsync_len = edid->mode.hspw; + u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw; + u32 vsync_len = edid->mode.vspw; + u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw; u32 xpos = 0, ypos = 0; struct rk3288_vop_regs *preg = vop_regs[vop_id]; @@ -98,14 +98,14 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) { - u32 hactive = edid->ha; - u32 vactive = edid->va; - u32 hfront_porch = edid->hso; - u32 hsync_len = edid->hspw; - u32 hback_porch = edid->hbl - edid->hso - edid->hspw; - u32 vfront_porch = edid->vso; - u32 vsync_len = edid->vspw; - u32 vback_porch = edid->vbl - edid->vso - edid->vspw; + u32 hactive = edid->mode.ha; + u32 vactive = edid->mode.va; + u32 hfront_porch = edid->mode.hso; + u32 hsync_len = edid->mode.hspw; + u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw; + u32 vfront_porch = edid->mode.vso; + u32 vsync_len = edid->mode.vspw; + u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw; struct rk3288_vop_regs *preg = vop_regs[vop_id]; switch (mode) { @@ -125,8 +125,8 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, V_DSP_OUT_MODE(15) | - V_DSP_HSYNC_POL(edid->phsync == '+') | - V_DSP_VSYNC_POL(edid->pvsync == '+')); + V_DSP_HSYNC_POL(edid->mode.phsync == '+') | + V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));

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coreboot-gerrit August 2015