coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: skylake: only generate ACPI cpu entries once
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 5a96b3743edb99ced733cf37cbeea305b58768c7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 18 10:11:35 2015 -0500 skylake: only generate ACPI cpu entries once The acpi_fill_ssdt_generator function pointer is evaluated for each device. As there are multiple cpus in the system the acpi_fill_ssdt_generator was being called more than once creating duplicate ACPI entries because there was more than 1 cpu device. Fix this by only generating them once by removing the acpi_fill_ssdt_generator for the cpu devices, but add the generator to the cpu cluster device. BUG=chrome-os-partner:44084 BRANCH=None TEST=Built and booted on glados. Noted ACPI entries only generated once. Original-Change-Id: I695c30e6150f6d3a79d13744c532f1b658b10402 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294240 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com> Change-Id: I7c85f44ba65398bda668e13db8be531535a983c5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11285 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11285 for details. -gerrit

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Patch merged into coreboot/master: skylake: FAB3 Adding Support for various SPD.
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 415022a86c1033e7b233fc2ca16e1d6367425ab5 Author: pchandri <preetham.chandrian(a)intel.com> Date: Fri Aug 14 12:18:31 2015 -0700 skylake: FAB3 Adding Support for various SPD. This pach enables memory configuration based on PCH_MEM_CFG and EC_BRD_ID. BRANCH=None BUG=chrome-os-partner:44087 CQ-DEPEND=CL:293832 TEST=Build and Boot FAB3 (Kunimitsu) Original-Change-Id: I7999e609c4b0b3c89a9689ee6bb6b98c88703809 Original-Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293787 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I52a1af1683b74e5cad71b9e4861942a23869f255 Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Reviewed-on: http://review.coreboot.org/11284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11284 for details. -gerrit

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Patch merged into coreboot/master: skylake: make PAD_CFG_GPI default to GPIO ownership
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 028bcaae32e8ca779d216dc61a9b3dd468ff4be2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Aug 17 16:27:09 2015 -0500 skylake: make PAD_CFG_GPI default to GPIO ownership The prior implementation of PAD_CFG_GPI kept the pad ownership as ACPI. The gpio driver in the kernel then wouldn't allow one to export those GPIOs through sysfs in /sys/class/gpio. Fix this by setting the ownership to GPIO. BUG=chrome-os-partner:44147 BRANCH=None TEST=Built and boot glados. PCH_WP gpio is properly exported by crossystem. Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294081 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11283 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11283 for details. -gerrit

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Patch merged into coreboot/master: glados: Abstract board GPIO configuration in gpio.h
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 56260850e8274d6088cbddca2e06a8735aa22995 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Aug 17 09:53:22 2015 -0700 glados: Abstract board GPIO configuration in gpio.h Move all the various places that look at board specific GPIOs into the mainboard gpio.h so it can be easily ported to new boards. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293942 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11282 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11282 for details. -gerrit

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Patch merged into coreboot/master: glados: Implement Chrome OS specific handlers
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit c3281917289bbc2cb39f62c46418053b57fa33e3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:54:27 2015 -0700 glados: Implement Chrome OS specific handlers Implement the required Chrome OS specific handlers to read the recovery mode, clear the recovery mode, read the lid switch state, and read the write protect state using the appropriate methods. Also update the Chrome OS ACPI device to use the GPIO definitions that are exposed now by the SOC. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados and successfully enter recovery mode Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293515 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11281 for details. -gerrit

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Patch merged into coreboot/master: chromeec: Add helper function to read EC switch state
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 699c788837cd7cbfe1627abbbb909f63e390690a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:52:08 2015 -0700 chromeec: Add helper function to read EC switch state Add a helper function to read the EC switch state on LPC based ECs instead of having each board need to understand and use the specific EC LPC IO method that is required. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293514 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11280 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11280 for details. -gerrit

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Patch merged into coreboot/master: glados: Fix SPD part number for Hynix H9CCNNN8JTBLAR
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 7f3f285bf181cce7a708d1957845a7e2b413f098 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Aug 1 00:25:02 2015 -0700 glados: Fix SPD part number for Hynix H9CCNNN8JTBLAR The part number was the same as the H9CCNNNBLTLAR which means it is not possible to distinguish the two based on part number alone. This breaks mosys and thus the factory tests. BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 SKU3 and verify memory reported by mosys Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293513 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11279 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11279 for details. -gerrit

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Patch merged into coreboot/master: glados: Add touchscreen device in ACPI
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit a40b7f3e1d637c01a29f7e7fe05201c5d61f428f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:27:56 2015 -0700 glados: Add touchscreen device in ACPI Add the ELAN touchscreen device in ACPI to bind it to the I2C device at bus I2C0, address 0x10, interrupt 31 (GPP_E7). BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 and see touchscreen initialized by kernel Original-Change-Id: I23b071b2767547baed239c94216cda6162d045dd Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293512 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I8a9492e6fa1f650cef0871329ae8944caffdaf5a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11278 for details. -gerrit

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Patch merged into coreboot/master: glados: Clean up mainboard ACPI devices
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 35a32064f124c3cd87c54f8173c064dc4e73de9c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:18:52 2015 -0700 glados: Clean up mainboard ACPI devices Clean up the device code for the glados mainboard, using the defined values for interrupts by the SOC and moving the various codec i2c addresses to the top of the file. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Original-Change-Id: Iead1aeb54363b15a6176d4f4a9511674195c0505 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293511 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I083c9ef6140e20a433cb2017e4c3cbc7a41e8fed Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11277 for details. -gerrit

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Patch merged into coreboot/master: kunimitsu: Enable SMBus device in devicetree
by gerrit＠coreboot.org 27 Aug '15

27 Aug '15

the following patch was just integrated into master: commit 5eed3a551892ee97f845b37e174f96727672f2fb Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Mon Aug 10 11:49:07 2015 +0530 kunimitsu: Enable SMBus device in devicetree this patch enables SMBus in device tree for kunimitsu board. BRANCH=none BUG=none TEST=built for kunimitsu; booted on kunimitsu fab3 and verified with lspci Original-Change-Id: I3b2b8c202b71c2a0c602169841978ed0c4d8bf8d Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292971 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Id20e6cafda8664bd0ae3a5acecdd66c58c220694 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Reviewed-on: http://review.coreboot.org/11276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11276 for details. -gerrit

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coreboot-gerrit August 2015