the following patch was just integrated into master:
commit 066980cd32796ae5a5ff97dd024416ce5f9829fc
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Fri May 8 17:17:44 2015 -0500
cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator
The prior ACPI _PSD generator committed in ef33db01 incorrectly assumed the active
link count of each processor was identical. Detect the link count on each node
when generating the _PSD objects.
Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf9b
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10158
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/10158 for details.
-gerrit
the following patch was just integrated into master:
commit fb39f82116f0411ee85e3d91bfd97237c34debbb
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Jun 2 20:25:03 2015 -0500
cpu/amd/car: Move AP stacks below the BSP stack to free up space
Caching SPD data during startup requires additional CAR space.
There was a large chunk of free space between the AP stack top and
the BSP stack bottom; moving the AP stacks below the BSP stack
allows this space to be utilized.
TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores)
and 120k of CAR.
Change-Id: I370ff368affde7061d6547527bda058b9016e977
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10404
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See http://review.coreboot.org/10404 for details.
-gerrit
the following patch was just integrated into master:
commit a97e0075a22af82ede8ab70a7e26d2a9e88490ea
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Jun 2 13:53:25 2015 -0500
cpu/amd/car: Increase Family 10h CAR size limit to 128k
This resolves issues with 4-node (32-core) systems not having
sufficient CAR memory available to boot.
TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores)
and 120k of CAR.
Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10402
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/10402 for details.
-gerrit
the following patch was just integrated into master:
commit b5e465522ed9efdc3e3f22db6391adb3fbca6bb1
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Jun 2 13:47:36 2015 -0500
cpu/amd: Detect any conflicts between sysinfo and the stack region
When increasing the number of supported CPUs on AMD Family 10h/15h
systems there is a relatively high chance of causing a collision
between the CAR global variable region and the AP stack space.
Such collision was noted when increasing the number of supported
CPUs to 32 on the ASUS KGPE-D16.
Detect collision at runtime and print a warning if collision is
present.
Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10401
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See http://review.coreboot.org/10401 for details.
-gerrit
the following patch was just integrated into master:
commit 46b2271ea49d43607cbed273b367f48cf04d844d
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Sun Apr 12 14:11:27 2015 -0500
northbridge/amd/amdfam10: Remove array to null comparison
The address of array 'sysinfo->DCTstatA' will always evaluate to 'true'.
Remove checking the base pointer of an array for validity.
Found-by: Coverity (CID 1293135: Incorrect expression)
Found-by: Clang (Wpointer-bool-conversion)
Change-Id: I99c9c9f1564dfb997c60b2a895d664e3b06c117b
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9596
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/9596 for details.
-gerrit
Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10527
-gerrit
commit 076d47d1c300d881e8e5f6e7f0790d877ab67ee9
Author: Naman Govil <namangov(a)gmail.com>
Date: Wed Jun 10 16:18:52 2015 -0400
armv8 : coreboot for qemu aarch64 #Work in progress#
This patchset aims to add a new mainboard
(emulation) for arm64. By the
end of this work, we will have coreboot running
on a qemu-system-aarch64.
Change-Id: I5550dcaae9981908e0c3bf6961206a70bebac5d1
Signed-off-by: Naman Govil <namangov(a)gmail.com>
---
src/arch/arm64/c_entry.c | 2 +-
src/arch/arm64/include/armv8/arch/secmon.h | 4 +-
src/cpu/armltd/armv8/Kconfig | 11 +++++
src/mainboard/emulation/qemu-armv8/Kconfig | 55 +++++++++++++++++++++++
src/mainboard/emulation/qemu-armv8/Kconfig.name | 2 +
src/mainboard/emulation/qemu-armv8/Makefile.inc | 40 +++++++++++++++++
src/mainboard/emulation/qemu-armv8/board_info.txt | 3 ++
src/mainboard/emulation/qemu-armv8/cbmem.c | 25 +++++++++++
src/mainboard/emulation/qemu-armv8/cpu_lib.S | 29 ++++++++++++
src/mainboard/emulation/qemu-armv8/devicetree.cb | 20 +++++++++
src/mainboard/emulation/qemu-armv8/mainboard.c | 27 +++++++++++
src/mainboard/emulation/qemu-armv8/media.c | 25 +++++++++++
src/mainboard/emulation/qemu-armv8/memlayout.ld | 48 ++++++++++++++++++++
src/mainboard/emulation/qemu-armv8/romstage.c | 40 +++++++++++++++++
src/mainboard/emulation/qemu-armv8/timer.c | 27 +++++++++++
src/mainboard/emulation/qemu-armv8/uart.c | 24 ++++++++++
util/crossgcc/buildgcc | 2 +-
util/genbuild_h/genbuild_h.sh | 6 +--
18 files changed, 383 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c
index a4d4773..b570a2b 100644
--- a/src/arch/arm64/c_entry.c
+++ b/src/arch/arm64/c_entry.c
@@ -60,7 +60,7 @@ static void arm64_init(void)
/*
* This variable holds entry point for CPUs starting up. The first
* element is the BSP path, and the second is the non-BSP path.
- */
+*/
void (*c_entry[2])(void) = { &arm64_init, &arch_secondary_cpu_init };
void *prepare_secondary_cpu_startup(void)
diff --git a/src/arch/arm64/include/armv8/arch/secmon.h b/src/arch/arm64/include/armv8/arch/secmon.h
index f8351b5..6458893 100644
--- a/src/arch/arm64/include/armv8/arch/secmon.h
+++ b/src/arch/arm64/include/armv8/arch/secmon.h
@@ -24,8 +24,8 @@
struct secmon_params {
size_t online_cpus;
- struct cpu_action bsp;
- struct cpu_action secondary;
+ struct cpu_action *bsp;
+ struct cpu_action *secondary;
};
void secmon_run(void (*entry)(void *), void *arg);
diff --git a/src/cpu/armltd/armv8/Kconfig b/src/cpu/armltd/armv8/Kconfig
new file mode 100644
index 0000000..e73980c
--- /dev/null
+++ b/src/cpu/armltd/armv8/Kconfig
@@ -0,0 +1,11 @@
+config CPU_ARMLTD_ARMV8
+ bool
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_VERSTAGE_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+ default n
+
+if CPU_ARMLTD_ARMV8
+
+endif
diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig b/src/mainboard/emulation/qemu-armv8/Kconfig
new file mode 100644
index 0000000..d152813
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/Kconfig
@@ -0,0 +1,55 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com>
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# WRITE THE INSTRUCTIONS TO EXECUTE
+# To execute, do:
+# export QEMU_AUDIO_DRV=none
+# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
+
+if BOARD_EMULATION_QEMU_ARMV8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select DRIVERS_UART_PL011
+ select BOOTBLOCK_CONSOLE
+ select EARLY_CONSOLE
+ select CONSOLE_SERIAL
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_VERSTAGE_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+ select BOARD_ROMSIZE_KB_4096
+
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-armv8
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU ARMv8"
+
+config MAX_CPUS
+ int
+ default 2
+
+config MAINBOARD_VENDOR
+ string
+ default "ARM Ltd."
+
+config DRAM_SIZE_MB
+ int
+ default 1024
+
+endif # BOARD_EMULATION_QEMU_ARMV8
diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig.name b/src/mainboard/emulation/qemu-armv8/Kconfig.name
new file mode 100644
index 0000000..bb3a0e4
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_QEMU_ARMV8
+ bool "QEMU armv8"
diff --git a/src/mainboard/emulation/qemu-armv8/Makefile.inc b/src/mainboard/emulation/qemu-armv8/Makefile.inc
new file mode 100644
index 0000000..7fa8880
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/Makefile.inc
@@ -0,0 +1,40 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com>
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+romstage-y += romstage.c
+
+romstage-y += cbmem.c
+ramstage-y += cbmem.c
+
+bootblock-y += media.c
+romstage-y += media.c
+ramstage-y += media.c
+
+bootblock-y += timer.c
+romstage-y += timer.c
+ramstage-y += timer.c
+
+bootblock-y += uart.c
+romstage-y += uart.c
+ramstage-y += uart.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
+
+bootblock-y += cpu_lib.S
+romstage-y += cpu_lib.S
+ramstage-y += cpu_lib.S
+
diff --git a/src/mainboard/emulation/qemu-armv8/board_info.txt b/src/mainboard/emulation/qemu-armv8/board_info.txt
new file mode 100644
index 0000000..69c5eb6
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/board_info.txt
@@ -0,0 +1,3 @@
+Board name: QEMU armv8
+Category: emulation
+Board URL: http://fabrice.bellard.free.fr/qemu/
diff --git a/src/mainboard/emulation/qemu-armv8/cbmem.c b/src/mainboard/emulation/qemu-armv8/cbmem.c
new file mode 100644
index 0000000..d3a2d6f
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/cbmem.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stddef.h>
+#include <cbmem.h>
+#include <symbols.h>
+
+void *cbmem_top(void)
+{
+ return _dram + (CONFIG_DRAM_SIZE_MB << 20);
+}
diff --git a/src/mainboard/emulation/qemu-armv8/cpu_lib.S b/src/mainboard/emulation/qemu-armv8/cpu_lib.S
new file mode 100644
index 0000000..13eed4b
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/cpu_lib.S
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright 2015, Naman Govil <namangov(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+
+.text
+.global smp_processor_id
+smp_processor_id:
+ /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */
+ /* Multiprocessor Afinity Register (MPIDR) contains CPU ID for a57 */
+ mrs x0, mpidr_el1
+ uxtb w0, w0
+ ret
diff --git a/src/mainboard/emulation/qemu-armv8/devicetree.cb b/src/mainboard/emulation/qemu-armv8/devicetree.cb
new file mode 100644
index 0000000..fa3c03a
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# TODO fill with Versatile Express board data in QEMU.
+chip cpu/armltd/armv8
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # Fake component for testing
+ end
+end
diff --git a/src/mainboard/emulation/qemu-armv8/mainboard.c b/src/mainboard/emulation/qemu-armv8/mainboard.c
new file mode 100644
index 0000000..b73ab9d
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/mainboard.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Enable qemu/armv8 device...\n");
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-armv8/media.c b/src/mainboard/emulation/qemu-armv8/media.c
new file mode 100644
index 0000000..4d4edd8
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/media.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot_device.h>
+
+/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */
+static const struct mem_region_device boot_dev =
+ MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+ return &boot_dev.rdev;
+}
diff --git a/src/mainboard/emulation/qemu-armv8/memlayout.ld b/src/mainboard/emulation/qemu-armv8/memlayout.ld
new file mode 100644
index 0000000..ee8132d
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/memlayout.ld
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C )2015, Naman Govil <namangov(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Memory map for qemu armv8:
+ *
+ * 0x0000_0000: jump instruction (required by qemu)
+ * 0x0001_0000: bootblock (entry of kernel / firmware)
+ * 0x0002_0000: romstage, assume up to 128KB in size.
+ * 0x0007_ff00: stack pointer
+ * 0x0010_0000: CBFS header
+ * 0x0011_0000: CBFS data
+ * 0x0100_0000: reserved for ramstage
+ * 0x1000_0000: I/O map address
+ */
+
+SECTIONS
+{
+ /* TODO: does this thing emulate SRAM? */
+
+ BOOTBLOCK(0x10000, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x000FC000, 16K)
+
+ DRAM_START(0x01000000)
+ RAMSTAGE(0x01000000, 16M)
+}
diff --git a/src/mainboard/emulation/qemu-armv8/romstage.c b/src/mainboard/emulation/qemu-armv8/romstage.c
new file mode 100644
index 0000000..6f6ed5b
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/romstage.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+#include <cbfs.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <arch/stages.h>
+
+void main(void)
+{
+ void *entry;
+ console_init();
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
+ stage_exit(entry);
+ //run_ramstage();
+}
+
+*/
+#include <console/console.h>
+#include <program_loading.h>
+
+void main(void)
+{
+ console_init();
+ run_ramstage();
+}
diff --git a/src/mainboard/emulation/qemu-armv8/timer.c b/src/mainboard/emulation/qemu-armv8/timer.c
new file mode 100644
index 0000000..b6d048b
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/timer.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+void udelay(unsigned int n);
+void udelay(unsigned int n)
+{
+ /* TODO provide delay here. */
+}
+
+int init_timer(void);
+int init_timer(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/emulation/qemu-armv8/uart.c b/src/mainboard/emulation/qemu-armv8/uart.c
new file mode 100644
index 0000000..0fc2390
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv8/uart.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <console/uart.h>
+
+#define UART0_IO_ADDRESS (0x1C090000)
+
+uintptr_t uart_platform_base(int idx)
+{
+ return UART0_IO_ADDRESS;
+}
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b78b141..f7a8023 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -387,7 +387,7 @@ build_BINUTILS() {
fi
CC="$CC" ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR \
--target=${TARGETARCH} --enable-targets=${TARGETARCH}${ADDITIONALTARGET} \
- --disable-werror --disable-nls --enable-lto --enable-gold \
+ --disable-werror --disable-nls --enable-lto \
--enable-plugins --enable-multilibs CFLAGS="$HOSTCFLAGS" || touch .failed
$MAKE $JOBS || touch .failed
$MAKE install DESTDIR=$DESTDIR || touch .failed
diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh
index be72f81..8e38d1b 100755
--- a/util/genbuild_h/genbuild_h.sh
+++ b/util/genbuild_h/genbuild_h.sh
@@ -33,16 +33,16 @@ if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then
else
GITREV=Unknown
TIMESOURCE="LANG=C LC_ALL=C TZ=UTC date"
- DATE=$(date +%s)
+ DATE=$(gdate +%s)
fi
our_date() {
case $(uname) in
NetBSD|OpenBSD|DragonFly|FreeBSD)
- date -r $1 $2
+ gdate -r $1 $2
;;
*)
- date -d @$1 $2
+ gdate -d @$1 $2
esac
}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10817
-gerrit
commit a27604512915c12a8c15c173ee86ffa0e7e5509a
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue Jul 7 00:32:47 2015 +0200
Unconditionally compile romstage with -Wa,--divide
The option --divide is required by our assembler to ensure that
'/' is not parsed as a comment sign but as a division, because
some of the cache as ram code is using divisions.
The --divide parameter has been part of the GNU as since binutils 2.17.
Hence, compile romstage (which contains cache as ram init) with
-Wa,--divide unconditionally instead of probing for it and adding it to
all compiler invocations (because that is causing random trouble with
clang when compiling the SMM code and calling gcc with --divide instead of
-Wa,--divide)
Change-Id: Ideefb2a243dc1d657ba415a99c1f8ab1d93800e0
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/arch/x86/Makefile.inc | 3 +++
util/xcompile/xcompile | 8 --------
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f502bbe..20740a4 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -247,6 +247,9 @@ $(objgenerated)/crt0.S: $$(crt0s)
# Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
romstage-S-ccopts += -I. -g0
+# Some cache as ram code is doing divisions
+romstage-S-ccopts +=-Wa,--divide
+
endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64
###############################################################################
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 7ae1e39..884d7b8 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -143,10 +143,6 @@ detect_special_flags() {
case "$architecture" in
x86)
- testcc "$GCC" "$CFLAGS_GCC -Wa,--divide" &&
- CFLAGS_GCC="$CFLAGS_GCC -Wa,--divide"
- testcc "$CLANG" "$CFLAGS_CLANG -Wa,--divide" &&
- CFLAGS_CLANG="$CFLAGS_CLANG -Wa,--divide"
# Always build for i686 -- no sse/mmx instructions since SMM
# modules are compiled using these flags. Note that this
# doesn't prevent a project using xcompile to explicitly
@@ -154,10 +150,6 @@ detect_special_flags() {
CFLAGS_GCC="$CFLAGS_GCC -march=i686"
;;
x64)
- testcc "$GCC" "$CFLAGS_GCC -Wa,--divide" &&
- CFLAGS_GCC="$CFLAGS_GCC -Wa,--divide"
- testcc "$CLANG" "$CFLAGS_CLANG -Wa,--divide" &&
- CFLAGS_CLANG="$CFLAGS_CLANG -Wa,--divide"
;;
mipsel)
testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \