coreboot-gerrit July 2015

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Patch merged into coreboot/master: cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 066980cd32796ae5a5ff97dd024416ce5f9829fc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri May 8 17:17:44 2015 -0500 cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator The prior ACPI _PSD generator committed in ef33db01 incorrectly assumed the active link count of each processor was identical. Detect the link count on each node when generating the _PSD objects. Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf9b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10158 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10158 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd/car: Move AP stacks below the BSP stack to free up space
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit fb39f82116f0411ee85e3d91bfd97237c34debbb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 20:25:03 2015 -0500 cpu/amd/car: Move AP stacks below the BSP stack to free up space Caching SPD data during startup requires additional CAR space. There was a large chunk of free space between the AP stack top and the BSP stack bottom; moving the AP stacks below the BSP stack allows this space to be utilized. TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores) and 120k of CAR. Change-Id: I370ff368affde7061d6547527bda058b9016e977 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10404 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See http://review.coreboot.org/10404 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd/car: Increase Family 10h CAR size limit to 128k
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit a97e0075a22af82ede8ab70a7e26d2a9e88490ea Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 13:53:25 2015 -0500 cpu/amd/car: Increase Family 10h CAR size limit to 128k This resolves issues with 4-node (32-core) systems not having sufficient CAR memory available to boot. TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores) and 120k of CAR. Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10402 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10402 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd: Detect any conflicts between sysinfo and the stack region
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit b5e465522ed9efdc3e3f22db6391adb3fbca6bb1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 13:47:36 2015 -0500 cpu/amd: Detect any conflicts between sysinfo and the stack region When increasing the number of supported CPUs on AMD Family 10h/15h systems there is a relatively high chance of causing a collision between the CAR global variable region and the AP stack space. Such collision was noted when increasing the number of supported CPUs to 32 on the ASUS KGPE-D16. Detect collision at runtime and print a warning if collision is present. Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10401 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See http://review.coreboot.org/10401 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdfam10: Remove array to null comparison
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 46b2271ea49d43607cbed273b367f48cf04d844d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 12 14:11:27 2015 -0500 northbridge/amd/amdfam10: Remove array to null comparison The address of array 'sysinfo->DCTstatA' will always evaluate to 'true'. Remove checking the base pointer of an array for validity. Found-by: Coverity (CID 1293135: Incorrect expression) Found-by: Clang (Wpointer-bool-conversion) Change-Id: I99c9c9f1564dfb997c60b2a895d664e3b06c117b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9596 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/9596 for details. -gerrit

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Patch set updated for coreboot: x86: Drop -Wa, --divide
by Stefan Reinauer 06 Jul '15

06 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10819 -gerrit commit bec2ed5bc1e4945bc7e9502cf78ebdf7529d61b9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 00:54:05 2015 +0200 x86: Drop -Wa,--divide Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Makefile.inc | 3 --- src/cpu/amd/car/cache_as_ram.inc | 10 +++++----- src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +- src/cpu/intel/car/cache_as_ram.inc | 8 ++++---- src/cpu/intel/haswell/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_2065x/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_206ax/cache_as_ram.inc | 6 +++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++-- src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 2 +- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 4 ++-- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 4 ++-- src/vendorcode/amd/agesa/f10/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f12/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f14/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f15/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 6 +++--- 18 files changed, 43 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 20740a4..f502bbe 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -247,9 +247,6 @@ $(objgenerated)/crt0.S: $$(crt0s) # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 -# Some cache as ram code is doing divisions -romstage-S-ccopts +=-Wa,--divide - endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ############################################################################### diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cf..fb7c05c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -237,15 +237,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm @@ -389,7 +389,7 @@ roll_cfg: /* Calculate stack pointer. */ movl $CacheSizeAPStack, %eax mull %ebx - movl $(CacheBase + CacheSize / 2), %esp + movl $(CacheBase + CacheSize >> 1), %esp subl %eax, %esp /* Retrive init detected. */ diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 7ddd3af..837352f 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -166,7 +166,7 @@ done_cache_as_ram_main: /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index df6f942..bcb0d4b 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -192,7 +192,7 @@ done_cache_as_ram_main: * copying it back to itself to invalidate the cache */ push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1d8ea8d..f9be6e8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -195,15 +195,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 595b4df..0a070b2 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -60,7 +60,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -116,7 +116,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 62f816a..cfa3b6b 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -57,7 +57,7 @@ wait_for_sipi: post_code(0x22) /* Zero out all fixed range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -121,7 +121,7 @@ clear_var_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index f54c691..2d469ff 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -55,7 +55,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -111,7 +111,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl @@ -298,7 +298,7 @@ before_romstage: cld movl $CONFIG_RAMBASE, %esi movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE / 4, %ecx + movl $HIGH_MEMORY_SAVE >> 2, %ecx rep movsl __acpi_resume_backup_done: diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d7d932e..271b756 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -40,7 +40,7 @@ cache_as_ram: /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -90,7 +90,7 @@ clear_mtrrs: /* Clear the cache memory reagion. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 2e560d9..86c10ce 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -36,7 +36,7 @@ cache_as_ram: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 7c6a67f..583ec58 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -82,7 +82,7 @@ wait_for_sipi: /* Zero out all fixed range and variable range MTRRs. */ movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi + movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx 1: @@ -152,7 +152,7 @@ wait_for_sipi: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index ba90c25..05d4889 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -63,7 +63,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -119,7 +119,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 11f50db..b0f4ee6 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -1380,7 +1380,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1389,7 +1389,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1411,7 +1411,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index f6b0899..147d16e 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1374,7 +1374,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1383,7 +1383,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1405,7 +1405,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index f0a1901..2104c27 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1388,7 +1388,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1397,7 +1397,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1419,7 +1419,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index c88709c..1ccefcf 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -1395,7 +1395,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1404,7 +1404,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1426,7 +1426,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index d6c6278..5118a4c 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1704,7 +1704,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1713,7 +1713,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1735,7 +1735,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 90c8cc6..862c8cb 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1069,7 +1069,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1078,7 +1078,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1100,7 +1100,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax #

1 0

Patch set updated for coreboot: armv8 : coreboot for qemu aarch64 #Work in progress#
by Naman Govil 06 Jul '15

06 Jul '15

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10527 -gerrit commit 076d47d1c300d881e8e5f6e7f0790d877ab67ee9 Author: Naman Govil <namangov(a)gmail.com> Date: Wed Jun 10 16:18:52 2015 -0400 armv8 : coreboot for qemu aarch64 #Work in progress# This patchset aims to add a new mainboard (emulation) for arm64. By the end of this work, we will have coreboot running on a qemu-system-aarch64. Change-Id: I5550dcaae9981908e0c3bf6961206a70bebac5d1 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/arch/arm64/c_entry.c | 2 +- src/arch/arm64/include/armv8/arch/secmon.h | 4 +- src/cpu/armltd/armv8/Kconfig | 11 +++++ src/mainboard/emulation/qemu-armv8/Kconfig | 55 +++++++++++++++++++++++ src/mainboard/emulation/qemu-armv8/Kconfig.name | 2 + src/mainboard/emulation/qemu-armv8/Makefile.inc | 40 +++++++++++++++++ src/mainboard/emulation/qemu-armv8/board_info.txt | 3 ++ src/mainboard/emulation/qemu-armv8/cbmem.c | 25 +++++++++++ src/mainboard/emulation/qemu-armv8/cpu_lib.S | 29 ++++++++++++ src/mainboard/emulation/qemu-armv8/devicetree.cb | 20 +++++++++ src/mainboard/emulation/qemu-armv8/mainboard.c | 27 +++++++++++ src/mainboard/emulation/qemu-armv8/media.c | 25 +++++++++++ src/mainboard/emulation/qemu-armv8/memlayout.ld | 48 ++++++++++++++++++++ src/mainboard/emulation/qemu-armv8/romstage.c | 40 +++++++++++++++++ src/mainboard/emulation/qemu-armv8/timer.c | 27 +++++++++++ src/mainboard/emulation/qemu-armv8/uart.c | 24 ++++++++++ util/crossgcc/buildgcc | 2 +- util/genbuild_h/genbuild_h.sh | 6 +-- 18 files changed, 383 insertions(+), 7 deletions(-) diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index a4d4773..b570a2b 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -60,7 +60,7 @@ static void arm64_init(void) /* * This variable holds entry point for CPUs starting up. The first * element is the BSP path, and the second is the non-BSP path. - */ +*/ void (*c_entry[2])(void) = { &arm64_init, &arch_secondary_cpu_init }; void *prepare_secondary_cpu_startup(void) diff --git a/src/arch/arm64/include/armv8/arch/secmon.h b/src/arch/arm64/include/armv8/arch/secmon.h index f8351b5..6458893 100644 --- a/src/arch/arm64/include/armv8/arch/secmon.h +++ b/src/arch/arm64/include/armv8/arch/secmon.h @@ -24,8 +24,8 @@ struct secmon_params { size_t online_cpus; - struct cpu_action bsp; - struct cpu_action secondary; + struct cpu_action *bsp; + struct cpu_action *secondary; }; void secmon_run(void (*entry)(void *), void *arg); diff --git a/src/cpu/armltd/armv8/Kconfig b/src/cpu/armltd/armv8/Kconfig new file mode 100644 index 0000000..e73980c --- /dev/null +++ b/src/cpu/armltd/armv8/Kconfig @@ -0,0 +1,11 @@ +config CPU_ARMLTD_ARMV8 + bool + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + default n + +if CPU_ARMLTD_ARMV8 + +endif diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig b/src/mainboard/emulation/qemu-armv8/Kconfig new file mode 100644 index 0000000..d152813 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Kconfig @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# WRITE THE INSTRUCTIONS TO EXECUTE +# To execute, do: +# export QEMU_AUDIO_DRV=none +# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom + +if BOARD_EMULATION_QEMU_ARMV8 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select DRIVERS_UART_PL011 + select BOOTBLOCK_CONSOLE + select EARLY_CONSOLE + select CONSOLE_SERIAL + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select BOARD_ROMSIZE_KB_4096 + + +config MAINBOARD_DIR + string + default emulation/qemu-armv8 + +config MAINBOARD_PART_NUMBER + string + default "QEMU ARMv8" + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "ARM Ltd." + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_EMULATION_QEMU_ARMV8 diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig.name b/src/mainboard/emulation/qemu-armv8/Kconfig.name new file mode 100644 index 0000000..bb3a0e4 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_EMULATION_QEMU_ARMV8 + bool "QEMU armv8" diff --git a/src/mainboard/emulation/qemu-armv8/Makefile.inc b/src/mainboard/emulation/qemu-armv8/Makefile.inc new file mode 100644 index 0000000..7fa8880 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Makefile.inc @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +romstage-y += romstage.c + +romstage-y += cbmem.c +ramstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += timer.c +romstage-y += timer.c +ramstage-y += timer.c + +bootblock-y += uart.c +romstage-y += uart.c +ramstage-y += uart.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld + +bootblock-y += cpu_lib.S +romstage-y += cpu_lib.S +ramstage-y += cpu_lib.S + diff --git a/src/mainboard/emulation/qemu-armv8/board_info.txt b/src/mainboard/emulation/qemu-armv8/board_info.txt new file mode 100644 index 0000000..69c5eb6 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU armv8 +Category: emulation +Board URL: http://fabrice.bellard.free.fr/qemu/ diff --git a/src/mainboard/emulation/qemu-armv8/cbmem.c b/src/mainboard/emulation/qemu-armv8/cbmem.c new file mode 100644 index 0000000..d3a2d6f --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stddef.h> +#include <cbmem.h> +#include <symbols.h> + +void *cbmem_top(void) +{ + return _dram + (CONFIG_DRAM_SIZE_MB << 20); +} diff --git a/src/mainboard/emulation/qemu-armv8/cpu_lib.S b/src/mainboard/emulation/qemu-armv8/cpu_lib.S new file mode 100644 index 0000000..13eed4b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/cpu_lib.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright 2015, Naman Govil <namangov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + +.text +.global smp_processor_id +smp_processor_id: + /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */ + /* Multiprocessor Afinity Register (MPIDR) contains CPU ID for a57 */ + mrs x0, mpidr_el1 + uxtb w0, w0 + ret diff --git a/src/mainboard/emulation/qemu-armv8/devicetree.cb b/src/mainboard/emulation/qemu-armv8/devicetree.cb new file mode 100644 index 0000000..fa3c03a --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# TODO fill with Versatile Express board data in QEMU. +chip cpu/armltd/armv8 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/qemu-armv8/mainboard.c b/src/mainboard/emulation/qemu-armv8/mainboard.c new file mode 100644 index 0000000..b73ab9d --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Enable qemu/armv8 device...\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-armv8/media.c b/src/mainboard/emulation/qemu-armv8/media.c new file mode 100644 index 0000000..4d4edd8 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/media.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> + +/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-armv8/memlayout.ld b/src/mainboard/emulation/qemu-armv8/memlayout.ld new file mode 100644 index 0000000..ee8132d --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/memlayout.ld @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C )2015, Naman Govil <namangov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Memory map for qemu armv8: + * + * 0x0000_0000: jump instruction (required by qemu) + * 0x0001_0000: bootblock (entry of kernel / firmware) + * 0x0002_0000: romstage, assume up to 128KB in size. + * 0x0007_ff00: stack pointer + * 0x0010_0000: CBFS header + * 0x0011_0000: CBFS data + * 0x0100_0000: reserved for ramstage + * 0x1000_0000: I/O map address + */ + +SECTIONS +{ + /* TODO: does this thing emulate SRAM? */ + + BOOTBLOCK(0x10000, 64K) + ROMSTAGE(0x20000, 128K) + STACK(0x000FC000, 16K) + + DRAM_START(0x01000000) + RAMSTAGE(0x01000000, 16M) +} diff --git a/src/mainboard/emulation/qemu-armv8/romstage.c b/src/mainboard/emulation/qemu-armv8/romstage.c new file mode 100644 index 0000000..6f6ed5b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/romstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +#include <cbfs.h> +#include <console/console.h> +#include <program_loading.h> +#include <arch/stages.h> + +void main(void) +{ + void *entry; + console_init(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); + //run_ramstage(); +} + +*/ +#include <console/console.h> +#include <program_loading.h> + +void main(void) +{ + console_init(); + run_ramstage(); +} diff --git a/src/mainboard/emulation/qemu-armv8/timer.c b/src/mainboard/emulation/qemu-armv8/timer.c new file mode 100644 index 0000000..b6d048b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void udelay(unsigned int n); +void udelay(unsigned int n) +{ + /* TODO provide delay here. */ +} + +int init_timer(void); +int init_timer(void) +{ + return 0; +} diff --git a/src/mainboard/emulation/qemu-armv8/uart.c b/src/mainboard/emulation/qemu-armv8/uart.c new file mode 100644 index 0000000..0fc2390 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/uart.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/uart.h> + +#define UART0_IO_ADDRESS (0x1C090000) + +uintptr_t uart_platform_base(int idx) +{ + return UART0_IO_ADDRESS; +} diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b78b141..f7a8023 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -387,7 +387,7 @@ build_BINUTILS() { fi CC="$CC" ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR \ --target=${TARGETARCH} --enable-targets=${TARGETARCH}${ADDITIONALTARGET} \ - --disable-werror --disable-nls --enable-lto --enable-gold \ + --disable-werror --disable-nls --enable-lto \ --enable-plugins --enable-multilibs CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index be72f81..8e38d1b 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -33,16 +33,16 @@ if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then else GITREV=Unknown TIMESOURCE="LANG=C LC_ALL=C TZ=UTC date" - DATE=$(date +%s) + DATE=$(gdate +%s) fi our_date() { case $(uname) in NetBSD|OpenBSD|DragonFly|FreeBSD) - date -r $1 $2 + gdate -r $1 $2 ;; *) - date -d @$1 $2 + gdate -d @$1 $2 esac }

1 0

New patch to review for coreboot: x86: Drop -Wa, --divide
by Stefan Reinauer 06 Jul '15

06 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10819 -gerrit commit 2b4fa86345e6263e158cc600d95c84bbca9093d1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 00:54:05 2015 +0200 x86: Drop -Wa,--divide Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Makefile.inc | 3 --- src/cpu/amd/car/cache_as_ram.inc | 10 +++++----- src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +- src/cpu/intel/car/cache_as_ram.inc | 8 ++++---- src/cpu/intel/haswell/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_2065x/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_206ax/cache_as_ram.inc | 6 +++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++-- src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 2 +- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 4 ++-- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 4 ++-- 12 files changed, 25 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 20740a4..f502bbe 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -247,9 +247,6 @@ $(objgenerated)/crt0.S: $$(crt0s) # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 -# Some cache as ram code is doing divisions -romstage-S-ccopts +=-Wa,--divide - endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ############################################################################### diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cf..fb7c05c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -237,15 +237,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm @@ -389,7 +389,7 @@ roll_cfg: /* Calculate stack pointer. */ movl $CacheSizeAPStack, %eax mull %ebx - movl $(CacheBase + CacheSize / 2), %esp + movl $(CacheBase + CacheSize >> 1), %esp subl %eax, %esp /* Retrive init detected. */ diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 7ddd3af..837352f 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -166,7 +166,7 @@ done_cache_as_ram_main: /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index df6f942..bcb0d4b 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -192,7 +192,7 @@ done_cache_as_ram_main: * copying it back to itself to invalidate the cache */ push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1d8ea8d..f9be6e8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -195,15 +195,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 595b4df..0a070b2 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -60,7 +60,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -116,7 +116,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 62f816a..cfa3b6b 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -57,7 +57,7 @@ wait_for_sipi: post_code(0x22) /* Zero out all fixed range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -121,7 +121,7 @@ clear_var_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index f54c691..2d469ff 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -55,7 +55,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -111,7 +111,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl @@ -298,7 +298,7 @@ before_romstage: cld movl $CONFIG_RAMBASE, %esi movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE / 4, %ecx + movl $HIGH_MEMORY_SAVE >> 2, %ecx rep movsl __acpi_resume_backup_done: diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d7d932e..271b756 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -40,7 +40,7 @@ cache_as_ram: /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -90,7 +90,7 @@ clear_mtrrs: /* Clear the cache memory reagion. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 2e560d9..86c10ce 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -36,7 +36,7 @@ cache_as_ram: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 7c6a67f..583ec58 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -82,7 +82,7 @@ wait_for_sipi: /* Zero out all fixed range and variable range MTRRs. */ movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi + movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx 1: @@ -152,7 +152,7 @@ wait_for_sipi: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index ba90c25..05d4889 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -63,7 +63,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -119,7 +119,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl

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New patch to review for coreboot: buildgcc: update IASL to version 20150619
by Stefan Reinauer 06 Jul '15

06 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10818 -gerrit commit d39e08cb11e6ed4eb9181badd0c874859df57fc7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 00:41:42 2015 +0200 buildgcc: update IASL to version 20150619 Change-Id: Ic0cb6826bb624e905b9c715f17a7629bc7b751c5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/acpica-unix-20150204.tar.gz.cksum | 1 - util/crossgcc/sum/acpica-unix-20150619.tar.gz.cksum | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 367f4d1..272820f 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -42,7 +42,7 @@ GCC_VERSION=4.9.2 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.25 GDB_VERSION=7.9.1 -IASL_VERSION=20150204 +IASL_VERSION=20150619 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number diff --git a/util/crossgcc/sum/acpica-unix-20150204.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20150204.tar.gz.cksum deleted file mode 100644 index c2f201f..0000000 --- a/util/crossgcc/sum/acpica-unix-20150204.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -e8ab49a9cd47ec1f3542b4185852bb49814c7694 tarballs/acpica-unix-20150204.tar.gz diff --git a/util/crossgcc/sum/acpica-unix-20150619.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20150619.tar.gz.cksum new file mode 100644 index 0000000..4047300 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix-20150619.tar.gz.cksum @@ -0,0 +1 @@ +ccc86513f10c47762bf46bf4d348c8cbda4336f5 tarballs/acpica-unix-20150619.tar.gz

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New patch to review for coreboot: Unconditionally compile romstage with -Wa, --divide
by Stefan Reinauer 06 Jul '15

06 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10817 -gerrit commit a27604512915c12a8c15c173ee86ffa0e7e5509a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 00:32:47 2015 +0200 Unconditionally compile romstage with -Wa,--divide The option --divide is required by our assembler to ensure that '/' is not parsed as a comment sign but as a division, because some of the cache as ram code is using divisions. The --divide parameter has been part of the GNU as since binutils 2.17. Hence, compile romstage (which contains cache as ram init) with -Wa,--divide unconditionally instead of probing for it and adding it to all compiler invocations (because that is causing random trouble with clang when compiling the SMM code and calling gcc with --divide instead of -Wa,--divide) Change-Id: Ideefb2a243dc1d657ba415a99c1f8ab1d93800e0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Makefile.inc | 3 +++ util/xcompile/xcompile | 8 -------- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f502bbe..20740a4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -247,6 +247,9 @@ $(objgenerated)/crt0.S: $$(crt0s) # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 +# Some cache as ram code is doing divisions +romstage-S-ccopts +=-Wa,--divide + endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ############################################################################### diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 7ae1e39..884d7b8 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -143,10 +143,6 @@ detect_special_flags() { case "$architecture" in x86) - testcc "$GCC" "$CFLAGS_GCC -Wa,--divide" && - CFLAGS_GCC="$CFLAGS_GCC -Wa,--divide" - testcc "$CLANG" "$CFLAGS_CLANG -Wa,--divide" && - CFLAGS_CLANG="$CFLAGS_CLANG -Wa,--divide" # Always build for i686 -- no sse/mmx instructions since SMM # modules are compiled using these flags. Note that this # doesn't prevent a project using xcompile to explicitly @@ -154,10 +150,6 @@ detect_special_flags() { CFLAGS_GCC="$CFLAGS_GCC -march=i686" ;; x64) - testcc "$GCC" "$CFLAGS_GCC -Wa,--divide" && - CFLAGS_GCC="$CFLAGS_GCC -Wa,--divide" - testcc "$CLANG" "$CFLAGS_CLANG -Wa,--divide" && - CFLAGS_CLANG="$CFLAGS_CLANG -Wa,--divide" ;; mipsel) testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \

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coreboot-gerrit July 2015