coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

Patch set updated for coreboot: northbridge/amd/pi: Add support for memory settings
by Dave Frodin 01 Jul '15

01 Jul '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10672 -gerrit commit 9fd76040e904ef39a3130f83f5ac349f84fe56e8 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed May 20 10:33:51 2015 -0600 northbridge/amd/pi: Add support for memory settings This adds support for binarypi based boards that have to make adjustments to the memory configuration settings. A PlatformMemoryConfiguration[] table that describes the memory configuration must be defined in the mainboard folder. Change-Id: I5e4b476a4adf3dd1f3b7843274a81ecb243d10ab Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/northbridge/amd/pi/agesawrapper.c | 15 +++++++++++++++ src/northbridge/amd/pi/def_callouts.c | 3 +++ 2 files changed, 18 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 255b31d..e716f9b 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -26,6 +26,9 @@ #include <heapManager.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> +#include <PlatformMemoryConfiguration.h> + +extern const PSO_ENTRY PlatformMemoryConfiguration[]; VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -136,6 +139,18 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + /* + * A PlatformMemoryConfiguration[] table must be added in the + * mainboard folder to any boards that need the memory configuation + * settings altered from the standard settings. Examples of boards + * requiring this change might be boards with soldered down memory, + * or boards that use a non-standard memory clock routing scheme + * There are PlatformMemoryConfiguration[] tables in many existing + * mainboards that can be used as an example. + */ + if (PlatformMemoryConfiguration[0] != PSO_END) + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration; + // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 8a4472c..389742c 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -27,6 +27,9 @@ #include "agesawrapper.h" #include "BiosCallOuts.h" #include "dimmSpd.h" +#include <PlatformMemoryConfiguration.h> + +const PSO_ENTRY __attribute__((weak)) PlatformMemoryConfiguration[] = { PSO_END }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {

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Patch set updated for coreboot: AMD binary PI: add southbridge support for fan control
by WANG Siyuan 01 Jul '15

01 Jul '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10720 -gerrit commit f5bc45ed59001b80669da1dcb750627f662eb9fd Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 23 22:28:17 2015 +0800 AMD binary PI: add southbridge support for fan control 1. Add functions to support fan control. 2. When IMC firmware is added, the current firmwares' layout cause build error. There is not enough space to add some firmwares, so HUDSON_PSP_OFFSET is added to fix this problem. Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 11 +++- src/southbridge/amd/pi/hudson/acpi/fch.asl | 6 ++- src/southbridge/amd/pi/hudson/hudson.c | 9 ++++ src/southbridge/amd/pi/hudson/imc.c | 87 ++++++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/imc.h | 26 +++++++++ 5 files changed, 136 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 235ce1e..30b5868 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -45,6 +45,10 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +romstage-y += imc.c +ramstage-y += imc.c +endif smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c @@ -100,10 +104,15 @@ HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ 65536) HUDSON_PSP_DIRECTORY_SIZE=256 else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +HUDSON_PSP_OFFSET=131072 +else +HUDSON_PSP_OFFSET=0 +endif HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ $(call int-add,\ $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ + $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(HUDSON_PSP_OFFSET)),\ 65536) HUDSON_PSP_DIRECTORY_SIZE=256 else diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index b4d6899..cee721f 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -160,9 +160,11 @@ Method(_INI, 0) { /* Determine the OS we're running on */ OSFL() +#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) /* TODO: It is unstable. */ - //#include "acpi/AmdImc.asl" /* Hudson IMC function */ - //ITZE() /* enable IMC Fan Control*/ + #include "acpi/AmdImc.asl" /* Hudson IMC function */ + ITZE() /* enable IMC Fan Control*/ +#endif } /* End Method(_SB._INI) */ Method(OSFL, 0){ diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 9b6e6a3..4ef65e9 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -30,6 +30,9 @@ #include "hudson.h" #include "smbus.h" #include "smi.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "fchec.h" +#endif /* Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid @@ -130,6 +133,12 @@ static void hudson_init(void *chip_info) static void hudson_final(void *chip_info) { +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + agesawrapper_fchecfancontrolservice(); +#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) + enable_imc_thermal_zone(); +#endif +#endif } struct chip_operations southbridge_amd_pi_hudson_ops = { diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c new file mode 100644 index 0000000..c2c9138 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include "imc.h" +#include <arch/io.h> +#include <device/device.h> +#include <delay.h> +#include "Porting.h" +#include "AGESA.h" +#include <Lib/amdlib.h> +#include <Proc/Fch/Fch.h> +#include <Proc/Fch/Common/FchCommonCfg.h> +#include <Proc/Fch/FchPlatform.h> + +#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) + +void imc_reg_init(void) +{ + u8 reg8; + /* Init Power Management Block 2 (PM2) Registers. + * Check BKDG for AMD Family 16h for details. */ + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff); + + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff); + write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff); + + reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4); + reg8 &= (UINT8)0x8F; + reg8 |= 0x10; + pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8); +} + +#ifndef __PRE_RAM__ +void enable_imc_thermal_zone(void) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT8 FunNum; + UINT8 regs[9]; + int i; + + regs[0] = 0; + regs[1] = 0; + FunNum = Fun_80; + for (i=0; i<=1; i++) + WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number + WaitForEcLDN9MailboxCmdAck(&StdHeader); + + for (i=2; i<=9; i++) + ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + + /* enable thermal zone 0 */ + regs[2] |= 1; + regs[0] = 0; + regs[1] = 0; + FunNum = Fun_81; + for (i=0; i<=9; i++) + WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); + WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number + WaitForEcLDN9MailboxCmdAck(&StdHeader); +} +#endif diff --git a/src/southbridge/amd/pi/hudson/imc.h b/src/southbridge/amd/pi/hudson/imc.h new file mode 100644 index 0000000..d348319 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/imc.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef HUDSON_IMC_H +#define HUDSON_IMC_H + +void imc_reg_init(void); +void enable_imc_thermal_zone(void); + +#endif

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Patch set updated for coreboot: amd/bettong: Enable fan control
by WANG Siyuan 01 Jul '15

01 Jul '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10721 -gerrit commit bfeaa0d0c25f8469d54bd9bf3f39d6f10e891749 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 23 22:43:03 2015 +0800 amd/bettong: Enable fan control 1. Use enable_imc_thermal_zone to enable fan control. 2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7 but does not work on Windows 8, so I didn't use it. After this issue is fixed, I'll add ACPI_ENABLE_THERMAL_ZONE in bettong/Kconfig. 3. Fan control works on Bettong. I used "APU Validation Toolkit" to test on Windows 8. This tool can put load to APU. The fan's behaviour is just like bettong/fchec.c defined. When the temperature is 40 Celsius, the fan start to run. Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 33 ++++++++++++++++ src/mainboard/amd/bettong/Makefile.inc | 3 ++ src/mainboard/amd/bettong/fchec.c | 67 ++++++++++++++++++++++++++++++++ src/mainboard/amd/bettong/fchec.h | 31 +++++++++++++++ src/vendorcode/amd/Kconfig | 2 +- 5 files changed, 135 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 1add1f5..f7503ad 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -51,6 +51,36 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); +/* Bettong Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* Enable IMC fan control. the recommand way */ + imc_reg_init(); + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + +#else + /* HWM fan control, using the alternative method */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE; /* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + static const GPIO_CONTROL oem_bettong_gpio[] = { {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, @@ -76,6 +106,9 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + oem_fan_control(FchParams_env); +#endif /* XHCI configuration */ #if CONFIG_HUDSON_XHCI_ENABLE diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc index b9cd644..70722ee 100644 --- a/src/mainboard/amd/bettong/Makefile.inc +++ b/src/mainboard/amd/bettong/Makefile.inc @@ -22,3 +22,6 @@ romstage-y += PlatformGnbPcie.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +ramstage-y += fchec.c +endif diff --git a/src/mainboard/amd/bettong/fchec.c b/src/mainboard/amd/bettong/fchec.c new file mode 100644 index 0000000..3458f9b --- /dev/null +++ b/src/mainboard/amd/bettong/fchec.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "fchec.h" + +void agesawrapper_fchecfancontrolservice() +{ + FCH_DATA_BLOCK LateParams; + + /* Thermal Zone Parameter */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111; + + FchECfancontrolservice(&LateParams); +} diff --git a/src/mainboard/amd/bettong/fchec.h b/src/mainboard/amd/bettong/fchec.h new file mode 100644 index 0000000..13305d8 --- /dev/null +++ b/src/mainboard/amd/bettong/fchec.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef AMD_BETTONG_FCHEC +#define AMD_BETTONG_FCHEC + +#include "imc.h" +#include "Porting.h" +#include "AGESA.h" +#include "FchCommonCfg.h" + +extern VOID FchECfancontrolservice (IN VOID *FchDataPtr); +void agesawrapper_fchecfancontrolservice(void); + +#endif diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 9720c79..2591cf9 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -34,7 +34,7 @@ choice config CPU_AMD_AGESA_BINARY_PI bool "binary PI" - select HUDSON_DISABLE_IMC + select HUDSON_DISABLE_IMC if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00630F01 help Use a binary PI package. Generally, these will be stored in the "3rdparty/blobs" directory. For some processors, these must be obtained

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Patch set updated for coreboot: x86 makefile: Use preprocessed linker files
by Marc Jones 01 Jul '15

01 Jul '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10743 -gerrit commit a833bfa194825d8cb80ce920bf54c545c4a42cee Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Jun 30 15:46:49 2015 -0600 x86 makefile: Use preprocessed linker files The top level Makefile runs the $stage-src .led scripts through the preprocessor and puts them in $(obj). Use the preprocessed .ld files and cat them together into x86 romstage_null.ld. Change-Id: If71240fbf7231df2b1333a1f8e5160cb8694f6ce Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/x86/Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index dcb9ff0..303f4cb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -220,12 +220,12 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $(obj)/config.h $$(filter %.ld,$$(romstage-srcs)) +$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - printf '$(foreach ldscript,$(^),#include "$(ldscript)"\n)' >> $@.tmp - $(CC_romstage) $(PREPROCESS_ONLY) $(CPPFLAGS_common) $@.tmp > $@ + $(foreach ldscript,$(^), $(shell cat $(ldscript) >> $@.tmp) ) + mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt

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New patch to review for coreboot: Braswell: Add the GNVS pointer to the DSDT
by Leroy P Leahy 01 Jul '15

01 Jul '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10748 -gerrit commit b5e02fd19ff71f9fd7c52904d549380507c943fa Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jun 30 15:25:44 2015 -0700 Braswell: Add the GNVS pointer to the DSDT Build the GNVS pointer and add it to the DSDT. With this patch, coreboot is able to boot ChromeOS without graphics. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/braswell/southcluster.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 5a3ad9d..58237fa 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -21,10 +21,12 @@ #include <arch/io.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <bootstate.h> #include <cbmem.h> #include "chip.h" #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> @@ -34,6 +36,7 @@ #include <soc/iomap.h> #include <soc/irq.h> #include <soc/lpc.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> @@ -445,10 +448,35 @@ void southcluster_enable_dev(device_t dev) } } +static void southcluster_inject_dsdt(device_t device) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); + } +} + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus,

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New patch to review for filo: Fix Makefiles for mixed use Kconfig usage
by Stefan Reinauer 01 Jul '15

01 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10747 -gerrit commit 0324003adde76176a4201da1f8b9e2df168306f4 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jun 30 17:38:36 2015 -0700 Fix Makefiles for mixed use Kconfig usage Change-Id: Ibcf7051a6e0e4b17536a4f18bd3a632c7463aae1 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Makefile b/Makefile index 5afa63e..a814983 100644 --- a/Makefile +++ b/Makefile @@ -33,6 +33,11 @@ export LIBCONFIG_PATH export KERNELVERSION := $(PROGRAM_VERSION) export KCONFIG_AUTOHEADER := $(obj)/config.h export KCONFIG_AUTOCONFIG := $(obj)/auto.conf +export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd +export KCONFIG_SPLITCONFIG := $(obj)/config +export KCONFIG_TRISTATE := $(obj)/tristate.conf +export KCONFIG_NEGATIVES := 1 +export KCONFIG_CONFIG := .config CONFIG_SHELL := sh KBUILD_DEFCONFIG := configs/defconfig @@ -171,6 +176,10 @@ $(obj)/version.h: Makefile $(obj)/%/: mkdir -p $@ +ifndef NOMKDIR +$(shell mkdir -p $(KCONFIG_SPLITCONFIG) $(objk)/lxdialog) +endif + prepare: $(sort $(dir $(OBJS))) $(obj)/util/kconfig/lxdialog/ clean:

1 0

New patch to review for filo: Rename Config.in to Kconfig
by Stefan Reinauer 01 Jul '15

01 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10746 -gerrit commit a880e2313ce389c88cea01c15af37f0412c0965e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jun 30 17:05:02 2015 -0700 Rename Config.in to Kconfig This is the standard name for all other Kconfig based projects surrounding coreboot. Let's adopt this in FILO, too. Change-Id: I6366468bd127485cc6f5fdbba216b55a593e062a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Config.in | 382 -------------------------------------------------- Kconfig | 382 ++++++++++++++++++++++++++++++++++++++++++++++++++ util/kconfig/Makefile | 2 +- 3 files changed, 383 insertions(+), 383 deletions(-) diff --git a/Config.in b/Config.in deleted file mode 100644 index cc48bd3..0000000 --- a/Config.in +++ /dev/null @@ -1,382 +0,0 @@ -## -## Copyright (C) 2008-2009 coresystems GmbH -## - -mainmenu "FILO Configuration" - -# When (if) we support multiple architectures, this will become an option. -config TARGET_I386 - bool - default y - -config MULTIBOOT_IMAGE - bool "Include a MultiBoot header" - default y - help - Including a MultiBoot header makes FILO chainloadable by MultiBoot - compliant boot loaders like GRUB. - -menu "Interface Options" - -config USE_GRUB - bool "Use GRUB like interface" - default y - help - Use GRUB legacy like interface instead of autoboot? - -config NON_INTERACTIVE - bool "non-interactive interface" - default n - help - Build a non-interactive interface to disallow modifications of - the boot options, e.g. the kernel to load or the command line. - -config PROMPT - string "Command line prompt" - default "filo" - depends on USE_GRUB - help - Per default, the FILO shell comes up with the prompt - filo> - If you want better GRUB compatibility (ie to pass through - your automated test system, specify 'grub' here instead of - 'filo' to get a prompt of - grub> - -config MENULST_FILE - string "GRUB menu.lst filename" - default "hda3:/boot/filo/menu.lst" - depends on USE_GRUB - help - For VIA Epia-MII CF use: - hde1:/boot/filo/menu.lst - -config MENULST_TIMEOUT - int "Timeout for loading menu.lst" - default 0 - depends on USE_GRUB - help - Set to 0 to ignore - -config USE_MD5_PASSWORDS - bool "Use MD5 passwords in menu.lst?" - default y - depends on USE_GRUB - help - Enable this option if your menu.lst passwords are MD5 encrypted. - -config USE_AUTOBOOT - bool "Autoboot a command line after timeout?" - depends on !USE_GRUB - default y - -config AUTOBOOT_FILE - string "Kernel filename and parameters" - default "hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200" - depends on !USE_GRUB - depends on USE_AUTOBOOT - help - #AUTOBOOT_FILE = "mem@0xfff80000" - #AUTOBOOT_FILE = "hde1@0" - #AUTOBOOT_FILE = "uda1:/vmlinuz.elf" - #AUTOBOOT_FILE = "flashb@0x00400000,0x154a00 console=tty0 console=ttyS0,115200" - -config AUTOBOOT_DELAY - int "Time in seconds before booting" - default 2 - depends on !USE_GRUB - depends on USE_AUTOBOOT - help - Time in second before booting AUTOBOOT_FILE - -config ISOLINUX_PARSER - bool "Support for parsing isolinux.cfg config files" - default n - depends on USE_GRUB - help - If you enable this function, FILO will be able to parse isolinux.cfg - config files in addition to filo.lst/menu.lst files. - -endmenu - -menu "Drivers" - -config IDE_DISK - bool "IDE DISK support" - default y - help - Driver for hard disk, CompactFlash, and CD-ROM on IDE bus - -config IDE_DISK_POLL_DELAY - int "IDE disk poll delay" - default 0 - depends on IDE_DISK - help - Add a short delay when polling status registers - (required on some broken SATA controllers) - NOTE: Slows down access significantly, so disable - whenever possible. Set to 1 if you require this. - -config SLOW_SATA - bool "Extra delay for SATA" - default n - depends on IDE_DISK - help - SATA drives seem to have problems reporting their spinup. - This will delay FILO start by 5s so the disks have some time to settle. - (required on some broken SATA controllers) - NOTE: Slows down access significantly, so disable - whenever possible. - -config PCMCIA_CF - bool "PCMCIA CF (Epia) support" - default n - depends on IDE_DISK - help - Use PCMCIA compact flash on Via Epia MII10000 and MII6000E - This device is referred to as hde. - -config IDE_NEW_DISK - bool "New IDE driver" - default n - depends on !IDE_DISK - help - Jens Axboe's fine IDE driver - -config LIBPAYLOAD_STORAGE - bool "Use libpayload's storage drivers" - default n - help - If selected, libpayloads storage drivers will be used to access - hard disk and optical drives. - -config USB_DISK - bool "USB Stack" - default y - help - Driver for USB Storage - -config FLASH_DISK - bool "NAND Flash support" - default n - help - Driver for Geode NAND flash storage - -config SUPPORT_PCI - bool "PCI support" - default y - -config PCI_BRUTE_SCAN - bool "Scan all PCI busses" - default n - depends on SUPPORT_PCI - help - Enable this to scan PCI busses above bus 0 - AMD64 based boards do need this. - -config SUPPORT_SOUND - bool "Sound Support" - default n - depends on SUPPORT_PCI - -config VIA_SOUND - bool "VIA sound" - default n - depends on SUPPORT_SOUND - -config FLASHROM_LOCKDOWN - bool "Flash memory lockdown" - default n - help - Enable system flash memory write protections and lock them down prior - starting the kernel. Flash memory lockdown can be disabled per boot - entry with the new command 'flashrom_unlock'. - - NOTE: Only supported on selected hardware: - - o Intel ICH7 (FWH) - o Intel ICH9 (FWH + SPI) - o Intel Cougar Point / Panther Point PCH (FWH + SPI) - o AMD SB600 (SPI by locking the flash chip itself) - -endmenu - -menu "Filesystems" - -config FSYS_EXT2FS - bool "EXT2 filesystem" - default y - -config FSYS_FAT - bool "FAT (MSDOS) filesystem" - default y - -config FSYS_JFS - bool "JFS" - default n - -config FSYS_MINIX - bool "Minix filesystem" - default n - -config FSYS_REISERFS - bool "ReiserFS" - default y - -config FSYS_XFS - bool "XFS" - default n - -config FSYS_ISO9660 - bool "ISO9660 filesystem" - default y - -config ELTORITO - bool "El Torito bootable CDROMs" - default y - depends on FSYS_ISO9660 - help - Support for boot disk image in bootable CD-ROM (El Torito) - -config FSYS_CRAMFS - bool "Compressed RAM filesystem (CRAMFS)" - default n - -config FSYS_SQUASHFS - bool "Squash filesystem" - default n - -config FSYS_CBFS - bool "CBFS ROM Image filesystem" - default y - -endmenu - -menu "Loaders" - -config LINUX_LOADER - bool "Standard Linux Loader" - default y - depends on TARGET_I386 - help - Loader for standard Linux kernel image, a.k.a. /vmlinuz - -config WINCE_LOADER - bool "Windows CE Loader" - default n - depends on TARGET_I386 - help - Loader for Windows CE image - -config ARTEC_BOOT - bool "Artec Loader" - default n - depends on TARGET_I386 - help - Artecboot Loader Support - -endmenu - -menu "Debugging & Experimental" - -config EXPERIMENTAL - bool "Enable experimental features" - default n - help - Select this option to enable experimental code. This may - cause FILO to stop compiling. Enable if you wish to develop - for FILO. - -config DEBUG_ALL - bool "DEBUG_ALL" - select DEBUG_ELFBOOT - select DEBUG_SEGMENT - select DEBUG_SYS_INFO - select DEBUG_BLOCKDEV - select DEBUG_VFS - select DEBUG_FSYS_EXT2FS - select DEBUG_PCI - select DEBUG_VIA_SOUND - select DEBUG_LINUXLOAD - select DEBUG_IDE - select DEBUG_USB - select DEBUG_ELTORITO - select DEBUG_FLASH - select DEBUG_ARTECBOOT - default n - -config DEBUG_ELFBOOT - bool "DEBUG_ELFBOOT" - default n - -config DEBUG_SEGMENT - bool "DEBUG_SEGMENT" - default n - -config DEBUG_SYS_INFO - bool "DEBUG_SYS_INFO" - default n - -config DEBUG_BLOCKDEV - bool "DEBUG_BLOCKDEV" - default n - -config DEBUG_VFS - bool "DEBUG_VFS" - default n - -config DEBUG_FSYS_EXT2FS - bool "DEBUG_FSYS_EXT2FS" - depends on FSYS_EXT2FS - default n - -config DEBUG_PCI - bool "DEBUG_PCI" - depends on SUPPORT_PCI - default n - -config DEBUG_VIA_SOUND - bool "DEBUG_VIA_SOUND" - depends on VIA_SOUND - default n - -config DEBUG_LINUXLOAD - bool "DEBUG_LINUXLOAD" - depends on LINUX_LOADER - default n - -config DEBUG_IDE - bool "DEBUG_IDE" - depends on IDE_DISK||IDE_NEW_DISK - default n - -config DEBUG_USB - bool "DEBUG_USB" - depends on USB_DISK - default n - -config DEBUG_ELTORITO - bool "DEBUG_ELTORITO" - depends on ELTORITO - default n - -config DEBUG_FLASH - bool "DEBUG_FLASH" - depends on FLASH_DISK - default n - -config DEBUG_ARTECBOOT - bool "DEBUG_ARTECBOOT" - depends on ARTEC_BOOT - default n - -config DEVELOPER_TOOLS - bool "Developer Tools" - depends on USE_GRUB - default y - help - Add commands useful for hardware development to the GRUB - interface. These are lspci, setpci, io. - -endmenu - diff --git a/Kconfig b/Kconfig new file mode 100644 index 0000000..cc48bd3 --- /dev/null +++ b/Kconfig @@ -0,0 +1,382 @@ +## +## Copyright (C) 2008-2009 coresystems GmbH +## + +mainmenu "FILO Configuration" + +# When (if) we support multiple architectures, this will become an option. +config TARGET_I386 + bool + default y + +config MULTIBOOT_IMAGE + bool "Include a MultiBoot header" + default y + help + Including a MultiBoot header makes FILO chainloadable by MultiBoot + compliant boot loaders like GRUB. + +menu "Interface Options" + +config USE_GRUB + bool "Use GRUB like interface" + default y + help + Use GRUB legacy like interface instead of autoboot? + +config NON_INTERACTIVE + bool "non-interactive interface" + default n + help + Build a non-interactive interface to disallow modifications of + the boot options, e.g. the kernel to load or the command line. + +config PROMPT + string "Command line prompt" + default "filo" + depends on USE_GRUB + help + Per default, the FILO shell comes up with the prompt + filo> + If you want better GRUB compatibility (ie to pass through + your automated test system, specify 'grub' here instead of + 'filo' to get a prompt of + grub> + +config MENULST_FILE + string "GRUB menu.lst filename" + default "hda3:/boot/filo/menu.lst" + depends on USE_GRUB + help + For VIA Epia-MII CF use: + hde1:/boot/filo/menu.lst + +config MENULST_TIMEOUT + int "Timeout for loading menu.lst" + default 0 + depends on USE_GRUB + help + Set to 0 to ignore + +config USE_MD5_PASSWORDS + bool "Use MD5 passwords in menu.lst?" + default y + depends on USE_GRUB + help + Enable this option if your menu.lst passwords are MD5 encrypted. + +config USE_AUTOBOOT + bool "Autoboot a command line after timeout?" + depends on !USE_GRUB + default y + +config AUTOBOOT_FILE + string "Kernel filename and parameters" + default "hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200" + depends on !USE_GRUB + depends on USE_AUTOBOOT + help + #AUTOBOOT_FILE = "mem@0xfff80000" + #AUTOBOOT_FILE = "hde1@0" + #AUTOBOOT_FILE = "uda1:/vmlinuz.elf" + #AUTOBOOT_FILE = "flashb@0x00400000,0x154a00 console=tty0 console=ttyS0,115200" + +config AUTOBOOT_DELAY + int "Time in seconds before booting" + default 2 + depends on !USE_GRUB + depends on USE_AUTOBOOT + help + Time in second before booting AUTOBOOT_FILE + +config ISOLINUX_PARSER + bool "Support for parsing isolinux.cfg config files" + default n + depends on USE_GRUB + help + If you enable this function, FILO will be able to parse isolinux.cfg + config files in addition to filo.lst/menu.lst files. + +endmenu + +menu "Drivers" + +config IDE_DISK + bool "IDE DISK support" + default y + help + Driver for hard disk, CompactFlash, and CD-ROM on IDE bus + +config IDE_DISK_POLL_DELAY + int "IDE disk poll delay" + default 0 + depends on IDE_DISK + help + Add a short delay when polling status registers + (required on some broken SATA controllers) + NOTE: Slows down access significantly, so disable + whenever possible. Set to 1 if you require this. + +config SLOW_SATA + bool "Extra delay for SATA" + default n + depends on IDE_DISK + help + SATA drives seem to have problems reporting their spinup. + This will delay FILO start by 5s so the disks have some time to settle. + (required on some broken SATA controllers) + NOTE: Slows down access significantly, so disable + whenever possible. + +config PCMCIA_CF + bool "PCMCIA CF (Epia) support" + default n + depends on IDE_DISK + help + Use PCMCIA compact flash on Via Epia MII10000 and MII6000E + This device is referred to as hde. + +config IDE_NEW_DISK + bool "New IDE driver" + default n + depends on !IDE_DISK + help + Jens Axboe's fine IDE driver + +config LIBPAYLOAD_STORAGE + bool "Use libpayload's storage drivers" + default n + help + If selected, libpayloads storage drivers will be used to access + hard disk and optical drives. + +config USB_DISK + bool "USB Stack" + default y + help + Driver for USB Storage + +config FLASH_DISK + bool "NAND Flash support" + default n + help + Driver for Geode NAND flash storage + +config SUPPORT_PCI + bool "PCI support" + default y + +config PCI_BRUTE_SCAN + bool "Scan all PCI busses" + default n + depends on SUPPORT_PCI + help + Enable this to scan PCI busses above bus 0 + AMD64 based boards do need this. + +config SUPPORT_SOUND + bool "Sound Support" + default n + depends on SUPPORT_PCI + +config VIA_SOUND + bool "VIA sound" + default n + depends on SUPPORT_SOUND + +config FLASHROM_LOCKDOWN + bool "Flash memory lockdown" + default n + help + Enable system flash memory write protections and lock them down prior + starting the kernel. Flash memory lockdown can be disabled per boot + entry with the new command 'flashrom_unlock'. + + NOTE: Only supported on selected hardware: + + o Intel ICH7 (FWH) + o Intel ICH9 (FWH + SPI) + o Intel Cougar Point / Panther Point PCH (FWH + SPI) + o AMD SB600 (SPI by locking the flash chip itself) + +endmenu + +menu "Filesystems" + +config FSYS_EXT2FS + bool "EXT2 filesystem" + default y + +config FSYS_FAT + bool "FAT (MSDOS) filesystem" + default y + +config FSYS_JFS + bool "JFS" + default n + +config FSYS_MINIX + bool "Minix filesystem" + default n + +config FSYS_REISERFS + bool "ReiserFS" + default y + +config FSYS_XFS + bool "XFS" + default n + +config FSYS_ISO9660 + bool "ISO9660 filesystem" + default y + +config ELTORITO + bool "El Torito bootable CDROMs" + default y + depends on FSYS_ISO9660 + help + Support for boot disk image in bootable CD-ROM (El Torito) + +config FSYS_CRAMFS + bool "Compressed RAM filesystem (CRAMFS)" + default n + +config FSYS_SQUASHFS + bool "Squash filesystem" + default n + +config FSYS_CBFS + bool "CBFS ROM Image filesystem" + default y + +endmenu + +menu "Loaders" + +config LINUX_LOADER + bool "Standard Linux Loader" + default y + depends on TARGET_I386 + help + Loader for standard Linux kernel image, a.k.a. /vmlinuz + +config WINCE_LOADER + bool "Windows CE Loader" + default n + depends on TARGET_I386 + help + Loader for Windows CE image + +config ARTEC_BOOT + bool "Artec Loader" + default n + depends on TARGET_I386 + help + Artecboot Loader Support + +endmenu + +menu "Debugging & Experimental" + +config EXPERIMENTAL + bool "Enable experimental features" + default n + help + Select this option to enable experimental code. This may + cause FILO to stop compiling. Enable if you wish to develop + for FILO. + +config DEBUG_ALL + bool "DEBUG_ALL" + select DEBUG_ELFBOOT + select DEBUG_SEGMENT + select DEBUG_SYS_INFO + select DEBUG_BLOCKDEV + select DEBUG_VFS + select DEBUG_FSYS_EXT2FS + select DEBUG_PCI + select DEBUG_VIA_SOUND + select DEBUG_LINUXLOAD + select DEBUG_IDE + select DEBUG_USB + select DEBUG_ELTORITO + select DEBUG_FLASH + select DEBUG_ARTECBOOT + default n + +config DEBUG_ELFBOOT + bool "DEBUG_ELFBOOT" + default n + +config DEBUG_SEGMENT + bool "DEBUG_SEGMENT" + default n + +config DEBUG_SYS_INFO + bool "DEBUG_SYS_INFO" + default n + +config DEBUG_BLOCKDEV + bool "DEBUG_BLOCKDEV" + default n + +config DEBUG_VFS + bool "DEBUG_VFS" + default n + +config DEBUG_FSYS_EXT2FS + bool "DEBUG_FSYS_EXT2FS" + depends on FSYS_EXT2FS + default n + +config DEBUG_PCI + bool "DEBUG_PCI" + depends on SUPPORT_PCI + default n + +config DEBUG_VIA_SOUND + bool "DEBUG_VIA_SOUND" + depends on VIA_SOUND + default n + +config DEBUG_LINUXLOAD + bool "DEBUG_LINUXLOAD" + depends on LINUX_LOADER + default n + +config DEBUG_IDE + bool "DEBUG_IDE" + depends on IDE_DISK||IDE_NEW_DISK + default n + +config DEBUG_USB + bool "DEBUG_USB" + depends on USB_DISK + default n + +config DEBUG_ELTORITO + bool "DEBUG_ELTORITO" + depends on ELTORITO + default n + +config DEBUG_FLASH + bool "DEBUG_FLASH" + depends on FLASH_DISK + default n + +config DEBUG_ARTECBOOT + bool "DEBUG_ARTECBOOT" + depends on ARTEC_BOOT + default n + +config DEVELOPER_TOOLS + bool "Developer Tools" + depends on USE_GRUB + default y + help + Add commands useful for hardware development to the GRUB + interface. These are lspci, setpci, io. + +endmenu + diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index 1d519b2..1482afa 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -11,7 +11,7 @@ ifeq ($(_OS),MINGW32) regex-objs=regex.o endif -Kconfig := Config.in +Kconfig := Kconfig FILO_CONFIG := $(src)/.config LIB_CONFIG := $(src)/lib.config

1 0

New patch to review for filo: filo: Fix compilation with latest libpayload changes
by Stefan Reinauer 01 Jul '15

01 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10745 -gerrit commit 29a639fa607966d9398f9b0ce64c0085c5a50273 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jun 30 17:03:19 2015 -0700 filo: Fix compilation with latest libpayload changes The use of IS_ENABLED() requires that kconfig.h from libpayload is included by all files. Change-Id: I53b9ec8cac9c0a409b1e7290e9b81e06f2ce29e5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a860236..5afa63e 100644 --- a/Makefile +++ b/Makefile @@ -93,7 +93,7 @@ ARCHDIR-$(CONFIG_TARGET_I386) := x86 CPPFLAGS := -nostdinc -imacros $(obj)/config.h CPPFLAGS += -I$(INCPAYLOAD) -I$(INCPAYLOAD)/$(ARCHDIR-y) CPPFLAGS += -I$(ARCHDIR-y)/include -Iinclude -I$(obj) -CPPFLAGS += -I$(GCCINCDIR) +CPPFLAGS += -I$(GCCINCDIR) --include $(INCPAYLOAD)/kconfig.h CFLAGS := -Wall -Wshadow -Os -pipe CFLAGS += -fomit-frame-pointer -fno-common -ffreestanding -fno-strict-aliasing

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coreboot-gerrit July 2015