coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: ifdfake: Add prompts and help for the regions in Kconfig
by gerrit＠coreboot.org 02 Jul '15

02 Jul '15

the following patch was just integrated into master: commit 57eff2a1924d9f0684630b593afe56a104603f90 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 21:49:56 2015 -0600 ifdfake: Add prompts and help for the regions in Kconfig Update the ifdfake region questions in Kconfig with help descriptions and prompts to allow values to be entered and not just use pre-defined default values. Change-Id: Ifdffadc3d74ec49492c2ded66623a1be6945425f Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10649 for details. -gerrit

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Patch merged into coreboot/master: Intel Firmware Descriptor: Add Lock ME Kconfig question
by gerrit＠coreboot.org 02 Jul '15

02 Jul '15

the following patch was just integrated into master: commit 775d50828ef090339ae57d93da55f46676f4bf58 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 21:47:19 2015 -0600 Intel Firmware Descriptor: Add Lock ME Kconfig question Add the Kconfig question to allow the user to lock the ME section using ifdtool. Change-Id: I46018c3bc9df3e309aa3083d693cbebf00e18062 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10648 for details. -gerrit

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Patch merged into coreboot/master: Move baytrail & fsp_baytrail to the common IFD interface.
by gerrit＠coreboot.org 02 Jul '15

02 Jul '15

the following patch was just integrated into master: commit c407cb97bc121ef28770cdda1d7ee7e2f06157e8 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 19:59:30 2015 -0600 Move baytrail & fsp_baytrail to the common IFD interface. - Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults. Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10647 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10647 for details. -gerrit

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Patch merged into coreboot/master: Intel Firmware Descriptor Kconfig: remove USES_INTEL_ME
by gerrit＠coreboot.org 02 Jul '15

02 Jul '15

the following patch was just integrated into master: commit c528c2e3e9f9e87522ab5b1cd61e67e1dec606ce Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 27 08:59:10 2015 -0600 Intel Firmware Descriptor Kconfig: remove USES_INTEL_ME When I added the common IFD Kconfig and Makefile, My thinking was that I could use this symbol to differentiate between the ME and the TXE, and to exclude the ME questions from platforms that use the IFD, but don't use an ME, like Rangeley. In practice this made things a lot more complicated and isn't worth it. Change-Id: I4428744e53c6bb7fc00a4fa4f0aa782c25fc9013 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10678 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10678 for details. -gerrit

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New patch to review for coreboot: sandy/ivybridge: use LAPIC timer in SMM
by Stefan Reinauer 02 Jul '15

02 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10762 -gerrit commit bb55a5d116b55f024286889d0f1a86d3a83c7f23 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 16:58:36 2015 -0700 sandy/ivybridge: use LAPIC timer in SMM This fixes an issue with using the flash driver in SMM for writing the event log through an SMM call. Change-Id: If18c77634cca4563f770f09b0f0797ece24308ce Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/x86/lapic/Makefile.inc | 3 ++ src/northbridge/intel/sandybridge/Makefile.inc | 1 - src/northbridge/intel/sandybridge/udelay.c | 55 -------------------------- 3 files changed, 3 insertions(+), 56 deletions(-) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 3061024..baa8292 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -3,5 +3,8 @@ ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y) +smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +endif romstage-y += boot_cpu.c ramstage-y += boot_cpu.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index cf79459..60765f2 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -42,7 +42,6 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c deleted file mode 100644 index b150253..0000000 --- a/src/northbridge/intel/sandybridge/udelay.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> - -/** - * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 100, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(0xce); - divisor = (msr.lo >> 8) & 0xff; - - d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -}

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New patch to review for coreboot: tegra124: verified boot fixups
by Stefan Reinauer 02 Jul '15

02 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10761 -gerrit commit d34fc66c1b4afe27c79459399240b2877587261b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 16:34:07 2015 -0700 tegra124: verified boot fixups This patch fixes up verified boot (vboot2) configuration of all tegra 124 bases boards in the tree. Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/google/nyan/Makefile.inc | 5 +++++ src/mainboard/google/nyan_big/Makefile.inc | 5 +++++ src/soc/nvidia/tegra124/Kconfig | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 441e0f9..97c1a94 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -43,6 +43,11 @@ ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-y += reset.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-y += early_configs.c + bootblock-y += memlayout.ld +verstage-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index 76411d7..3c9699f 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -42,6 +42,11 @@ ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-y += reset.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-y += early_configs.c + bootblock-y += memlayout.ld +verstage-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 9c83865..c35e2c2 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -2,7 +2,7 @@ config SOC_NVIDIA_TEGRA124 bool default n select ARCH_BOOTBLOCK_ARMV4 - select ARCH_VERSTAGE_ARMV4 + select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL

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New patch to review for coreboot: purin: chromeos.c also needed in romstage
by Stefan Reinauer 01 Jul '15

01 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10760 -gerrit commit a4439a0d03f55b7ee5be43d803571595bde6e513 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 14:51:41 2015 -0700 purin: chromeos.c also needed in romstage Otherwise the Chrome OS build won't succeed. Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/google/purin/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/purin/Makefile.inc b/src/mainboard/google/purin/Makefile.inc index 00e4f0b..00e6af7 100644 --- a/src/mainboard/google/purin/Makefile.inc +++ b/src/mainboard/google/purin/Makefile.inc @@ -26,6 +26,7 @@ verstage-y += chromeos.c verstage-y += reset.c romstage-y += boardid.c +romstage-y += chromeos.c romstage-y += reset.c ramstage-y += boardid.c

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Patch merged into coreboot/master: coreinfo: use coreboot's kconfig
by gerrit＠coreboot.org 01 Jul '15

01 Jul '15

the following patch was just integrated into master: commit 0ab2b25f01f7e2cbfcd632f8d78b969b79a534d8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Jun 29 16:10:16 2015 -0700 coreinfo: use coreboot's kconfig Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I99e612dca3c2e5678d43b3e85eaf2f51d8f693e7 Reviewed-on: http://review.coreboot.org/10715 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10715 for details. -gerrit

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Patch merged into coreboot/master: tegra132: adjust vboot2 memlayout to make coreboot compile
by gerrit＠coreboot.org 01 Jul '15

01 Jul '15

the following patch was just integrated into master: commit ca7794854c9d04d1fcd95c2e1170265b8a36297b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 13:55:10 2015 -0700 tegra132: adjust vboot2 memlayout to make coreboot compile romstage didn't fit in it's region anymore. Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10759 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10759 for details. -gerrit

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Patch set updated for coreboot: tegra132: adjust vboot2 memlayout to make coreboot compile
by Stefan Reinauer 01 Jul '15

01 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10759 -gerrit commit 810c98bac41de4a1ac7a019e89d1e386607d97b7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 13:55:10 2015 -0700 tegra132: adjust vboot2 memlayout to make coreboot compile romstage didn't fit in it's region anymore. Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index a834f99..2fba8ef 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -36,9 +36,9 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) - BOOTBLOCK(0x40019000, 24K) - VERSTAGE(0x4001f000, 60K) - ROMSTAGE(0x4002e000, 72K) + BOOTBLOCK(0x40019000, 22K) + VERSTAGE(0x4001e800, 58K) + ROMSTAGE(0x4002d000, 76K) SRAM_END(0x40040000) DRAM_START(0x80000000)

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coreboot-gerrit July 2015