coreboot-gerrit July 2015

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Patch set updated for coreboot: timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
by Patrick Georgi 02 Jul '15

02 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10742 -gerrit commit d08302887a90ce0411ef822b47298f2440d7b48e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 6 09:58:07 2014 -0600 timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS so stop guarding the compilation. BUG=None BRANCH=None TEST=Built Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228190 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392 --- src/arch/x86/boot/acpi.c | 4 ---- src/mainboard/google/cosmos/romstage.c | 15 ++++----------- src/mainboard/google/veyron_brain/romstage.c | 11 +++-------- src/mainboard/google/veyron_danger/romstage.c | 11 +++-------- src/mainboard/google/veyron_jerry/romstage.c | 12 ++++-------- src/mainboard/google/veyron_mickey/romstage.c | 11 +++-------- src/mainboard/google/veyron_mighty/romstage.c | 11 +++-------- src/mainboard/google/veyron_minnie/romstage.c | 12 ++++-------- src/mainboard/google/veyron_pinky/romstage.c | 14 ++++++-------- src/mainboard/google/veyron_rialto/romstage.c | 11 +++-------- src/mainboard/google/veyron_romy/romstage.c | 11 +++-------- src/mainboard/google/veyron_speedy/romstage.c | 12 ++++-------- src/southbridge/intel/bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/i82801gx/bootblock.c | 3 +-- src/southbridge/intel/lynxpoint/bootblock.c | 3 +-- 16 files changed, 44 insertions(+), 103 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index cf33e40..134e437 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -34,9 +34,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> -#if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> -#endif #include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ @@ -1124,9 +1122,7 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_ACPI_WAKE_JUMP); -#endif acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index 0988bee..e5fa67e 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -37,37 +37,30 @@ void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); -#endif console_init(); -#if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); -#endif + sdram_init(); -#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); -#endif + mmu_init(); mmu_config_range(0, 4096, DCACHE_OFF); dcache_mmu_enable(); cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif - -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 0328e95..e9857b8 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -80,9 +80,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -93,13 +91,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,9 +106,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 06eabe0..fb6e631 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,8 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index 06eabe0..5ccbe3e 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 5031ad9d..492c0f0 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -93,9 +93,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -106,13 +104,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -122,9 +120,9 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif + run_ramstage(); } diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index ffdfdb0..9cdacc3 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 4df6bb5..18532df 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -86,9 +86,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 46aa58f..8f6ddbc 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 64c4410..dde1ae9 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -47,9 +47,8 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); /* Enable RCBA */ diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 6727173..8c2133b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc();

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Patch set updated for coreboot: memlayout: Add TIMESTAMP region
by Patrick Georgi 02 Jul '15

02 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10734 -gerrit commit 02b34e5683793d00405115e0325505d3e97cdc64 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:26:47 2014 -0700 memlayout: Add TIMESTAMP region This region is used to store the timestamps from bootblock and verstage when cbmem is not yet initialized. Once cbmem is setup, the timestamps from this region can be retrieved and filled up properly in cbmem. In order to achieve this a new Kconfig option is introduced HAS_TIMESTAMP_REGION. This is to maintain compatbility with older boards which do not use this region. BUG=chrome-os-partner:32973 BRANCH=None TEST=cbmem -t and verified timestamps on ryu Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/223348 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 3f77e81a369d032cbb0bc072872b373533b000e9) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/Kconfig | 8 ++++++++ src/include/memlayout.h | 3 +++ src/include/symbols.h | 4 ++++ 3 files changed, 15 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 269f7d2..3679685 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -200,6 +200,14 @@ config COLLECT_TIMESTAMPS Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. +config HAS_PRECBMEM_TIMESTAMP_REGION + bool "Timestamp region exists for pre-cbmem timestamps" + depends on COLLECT_TIMESTAMPS + help + A separate region is maintained to allow storing of timestamps before + cbmem comes up. This is useful for storing timestamps across different + stage boundaries. + config USE_BLOBS bool "Allow use of binary-only repository" default n diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 2771f2f..a529628 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -47,6 +47,9 @@ #define DRAM_START(addr) SYMBOL(dram, addr) +#define TIMESTAMP(addr, size) \ + REGION(timestamp, addr, size, 8) + #define PRERAM_CBMEM_CONSOLE(addr, size) \ REGION(preram_cbmem_console, addr, size, 4) diff --git a/src/include/symbols.h b/src/include/symbols.h index 9102e82..3fbf819 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -28,6 +28,10 @@ extern u8 _esram[]; extern u8 _dram[]; +extern u8 _timestamp[]; +extern u8 _etimestamp[]; +#define _timestamp_size (_etimestamp - _timestamp) + extern u8 _preram_cbmem_console[]; extern u8 _epreram_cbmem_console[]; #define _preram_cbmem_console_size \

1 0

Patch set updated for coreboot: timestamp: Make timestamp library more flexible and intelligent
by Patrick Georgi 02 Jul '15

02 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10735 -gerrit commit ab6ba3d10bf91482c7f1bfb294cb92b6748373a0 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Oct 15 15:17:49 2014 -0700 timestamp: Make timestamp library more flexible and intelligent Add support for: 1) Using timestamps in bootblock and verstage 2) Allowing the timestamps to be stashed into _timestamp region so that they can be used across multiple stages 3) Performing operations over the timestamps in _timestamp region Instead of having two separate APIs for stashing and adding timestamps, let the timestamp library decide on its own where to save depending on timestamp cache status. Now the sequence of operations would be something like: timestamp_init / timestamp_early_init : Set the base time timestamp_add / timestamp_add_now cbmem_initialize : It internally calls timestamp_sync timestamp_add / timestamp_add_now BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully for ryu and samus. cbmem -t on ryu works fine. Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224024 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 2f6b472984f4971ece172b789aab3bc82afa8a9d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4d2ffc99277be6c248c8c70149dc14334a1f536a --- src/arch/x86/Makefile.inc | 3 +- src/arch/x86/init/romstage.ld | 5 + src/include/timestamp.h | 25 ++++ src/lib/timestamp.c | 259 ++++++++++++++++++++++++++++++------------ 4 files changed, 221 insertions(+), 71 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f502bbe..dcb9ff0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -225,7 +225,8 @@ $(objgenerated)/romstage_null.ld: $(obj)/config.h $$(filter %.ld,$$(romstage-src rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp printf '$(foreach ldscript,$(^),#include "$(ldscript)"\n)' >> $@.tmp - $(CC_romstage) $(PREPROCESS_ONLY) $@.tmp > $@ + $(CC_romstage) $(PREPROCESS_ONLY) $(CPPFLAGS_common) $@.tmp > $@ + $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt @printf " GEN $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 7b9cb6a..db1c8ee 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -53,6 +53,11 @@ SECTIONS .car.data . (NOLOAD) : { _car_data_start = .; *(.car.global_data); +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + _timestamp = .; + . = . + 0x100; + _etimestamp = .; +#endif _car_data_end = .; /* The preram cbmem console area comes last to take advantage * of a zero-sized array to hold the memconsole contents. diff --git a/src/include/timestamp.h b/src/include/timestamp.h index a248ea4..a2301fb 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -89,10 +89,35 @@ enum timestamp_id { }; #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) +/* + * Order of usage of timestamp library is: + * Call timestamp_early_init / timestamp_init to set base time before any + * timestamp_add function is called. timestamp_early_init also ensures that the + * cache is valid in _timestamp region. + * After this, timestamp_add / timestamp_add_now can be used to record + * timestamps. Sync will be automatically taken care of by cbmem_initialize + */ +/* + * Initialize the cache to a valid state and set the base time. + * This function is used before DRAM is setup so that the timestamp cache can + * be initialized in _timestamp region. + * Both, timestamp_init and timestamp_early_init reset the cbmem state to + * timestamp table reset required. Thus, whenever a timestamp_add or + * timestamp_sync is done to add new entries into the cbmem timestamp table, it + * first resets the table to 0 entries. + */ +void timestamp_early_init(uint64_t base); +/* Initialize the base time for timestamps and mark cache as valid */ void timestamp_init(uint64_t base); +/* + * Add a new timestamp. Depending on cbmem is available or not, this timestamp + * will be stored to cbmem / timestamp cache. + */ void timestamp_add(enum timestamp_id id, uint64_t ts_time); +/* Calls timestamp_add with current timestamp. */ void timestamp_add_now(enum timestamp_id id); #else +#define timestamp_early_init(base) #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 0c41ea2..c6799ac 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -17,10 +17,12 @@ * Foundation, Inc. */ +#include <assert.h> #include <stddef.h> #include <stdint.h> #include <console/console.h> #include <cbmem.h> +#include <symbols.h> #include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> @@ -29,12 +31,70 @@ #define MAX_TIMESTAMPS 60 -static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL; -static uint64_t ts_basetime CAR_GLOBAL = 0; +#define MAX_TIMESTAMP_CACHE 16 -static void timestamp_stash(enum timestamp_id id, uint64_t ts_time); +struct __attribute__((__packed__)) timestamp_cache { + uint16_t cache_state; + uint16_t cbmem_state; + struct timestamp_table table; + struct timestamp_entry entries[MAX_TIMESTAMP_CACHE]; +}; -static void timestamp_real_init(uint64_t base) +#define USE_TIMESTAMP_REGION \ + (IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) && \ + defined(__PRE_RAM__)) + +#define USE_LOCAL_TIMESTAMP_CACHE (!defined(__PRE_RAM__)) + +#define HAS_CBMEM \ + (defined(__ROMSTAGE__) || defined(__RAMSTAGE__)) + +#if USE_LOCAL_TIMESTAMP_CACHE +static struct timestamp_cache timestamp_cache; +#endif + +enum { + TIMESTAMP_CACHE_UNINITIALIZED = 0, + TIMESTAMP_CACHE_INITIALIZED, + TIMESTAMP_CACHE_NOT_NEEDED, +}; + +enum { + TIMESTAMP_CBMEM_RESET_NOT_REQD = 0, + TIMESTAMP_CBMEM_RESET_REQD, +}; + +static void timestamp_cache_init(struct timestamp_cache *ts_cache, + uint64_t base, uint16_t cbmem_state) +{ + ts_cache->table.num_entries = 0; + ts_cache->table.max_entries = MAX_TIMESTAMP_CACHE; + ts_cache->table.base_time = base; + ts_cache->cache_state = TIMESTAMP_CACHE_INITIALIZED; + ts_cache->cbmem_state = cbmem_state; +} + +static struct timestamp_cache *timestamp_cache_get(void) +{ + struct timestamp_cache *ts_cache = NULL; + +#if USE_LOCAL_TIMESTAMP_CACHE + ts_cache = &timestamp_cache; +#elif IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + if (_timestamp_size < sizeof(*ts_cache)) + BUG(); + ts_cache = car_get_var_ptr((void *)_timestamp); +#endif + + if (ts_cache && ts_cache->cache_state == TIMESTAMP_CACHE_UNINITIALIZED) + timestamp_cache_init(ts_cache, 0, + TIMESTAMP_CBMEM_RESET_NOT_REQD); + + return ts_cache; +} + +#if HAS_CBMEM +static struct timestamp_table *timestamp_alloc_cbmem_table(void) { struct timestamp_table* tst; @@ -43,14 +103,15 @@ static void timestamp_real_init(uint64_t base) MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); if (!tst) - return; + return NULL; - tst->base_time = base; + tst->base_time = 0; tst->max_entries = MAX_TIMESTAMPS; tst->num_entries = 0; - car_set_var(ts_table_p, tst); + return tst; } +#endif /* Determine if one should proceed into timestamp code. This is for protecting * systems that have multiple processors running in romstage -- namely AMD @@ -64,97 +125,162 @@ static int timestamp_should_run(void) return 1; } -void timestamp_add(enum timestamp_id id, uint64_t ts_time) +static struct timestamp_table *timestamp_table_get(void) { - struct timestamp_entry *tse; - struct timestamp_table *ts_table = NULL; + MAYBE_STATIC struct timestamp_table *ts_table = NULL; + struct timestamp_cache *ts_cache; if (!timestamp_should_run()) - return; + return NULL; - ts_table = car_get_var(ts_table_p); - if (!ts_table) { - timestamp_stash(id, ts_time); - return; + ts_cache = timestamp_cache_get(); + + if (ts_cache == NULL) { +#if HAS_CBMEM + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + return ts_table; +} + + if (ts_cache->cache_state != TIMESTAMP_CACHE_NOT_NEEDED) + return &ts_cache->table; + +#if HAS_CBMEM + if (ts_cache->cbmem_state == TIMESTAMP_CBMEM_RESET_REQD) { + ts_table = timestamp_alloc_cbmem_table(); + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_NOT_REQD; } - if (ts_table->num_entries == ts_table->max_entries) + + if (!ts_table) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + + return ts_table; +} + +static void timestamp_add_table_entry(struct timestamp_table *ts_table, + enum timestamp_id id, uint64_t ts_time) +{ + struct timestamp_entry *tse; + + if (ts_table->num_entries == ts_table->max_entries) { + printk(BIOS_ERR, "ERROR: Dropped a timestamp entry\n"); return; + } tse = &ts_table->entries[ts_table->num_entries++]; tse->entry_id = id; tse->entry_stamp = ts_time - ts_table->base_time; } -void timestamp_add_now(enum timestamp_id id) +static void timestamp_sync(void) { - timestamp_add(id, timestamp_get()); + uint32_t i; + + struct timestamp_cache *ts_cache; + struct timestamp_table *ts_cache_table; + struct timestamp_table *ts_cbmem_table = NULL; + + ts_cache = timestamp_cache_get(); + + /* No timestamp cache found */ + if (ts_cache == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp cache found\n"); + return; } -#define MAX_TIMESTAMP_CACHE 8 -struct timestamp_cache { - enum timestamp_id id; - uint64_t time; -} timestamp_cache[MAX_TIMESTAMP_CACHE] CAR_GLOBAL; + ts_cache_table = &ts_cache->table; -static int timestamp_entries CAR_GLOBAL = 0; +#if HAS_CBMEM + ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); -/** - * timestamp_stash() allows to temporarily cache timestamps. - * This is needed when timestamping before the CBMEM area - * is initialized. The function timestamp_do_sync() is used to - * write the timestamps to the CBMEM area and this is done as - * part of CAR migration for romstage, and in ramstage main(). - */ + if ((ts_cache->cbmem_state == TIMESTAMP_CBMEM_RESET_REQD) || + (ts_cbmem_table == NULL)) + ts_cbmem_table = timestamp_alloc_cbmem_table(); +#endif -static void timestamp_stash(enum timestamp_id id, uint64_t ts_time) -{ - struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); - int ts_entries = car_get_var(timestamp_entries); + if (ts_cbmem_table == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + return; + } - if (ts_entries >= MAX_TIMESTAMP_CACHE) { - printk(BIOS_ERR, "ERROR: failed to add timestamp to cache\n"); + if (ts_cbmem_table == ts_cache_table) { + printk(BIOS_ERR, "ERROR: Table error to sync timestamps\n"); return; } - ts_cache[ts_entries].id = id; - ts_cache[ts_entries].time = ts_time; - car_set_var(timestamp_entries, ++ts_entries); + + ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED; + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_NOT_REQD; + + /* + * There can be two cases for timestamp sync: + * 1. Newly added cbmem_table will have base_time of 0. Thus, no + * adjusments are needed for the timestamps being added from cache to + * cbmem table. + * 2. Timestamps added to cache before ramstage: In this case, the + * base_time in cache table would be 0 and add_table_entry will take + * care of subtracting the appropriate base_time. + */ + for (i = 0; i < ts_cache_table->num_entries; i++) { + struct timestamp_entry *tse = &ts_cache_table->entries[i]; + timestamp_add_table_entry(ts_cbmem_table, tse->entry_id, + tse->entry_stamp); } -static void timestamp_do_sync(void) -{ - struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); - int ts_entries = car_get_var(timestamp_entries); + ts_cache_table->num_entries = 0; + /* Freshly added cbmem table has base_time 0. Inherit cache base_time */ + if (ts_cbmem_table->base_time == 0) + ts_cbmem_table->base_time = ts_cache_table->base_time; +} - int i; - for (i = 0; i < ts_entries; i++) - timestamp_add(ts_cache[i].id, ts_cache[i].time); - car_set_var(timestamp_entries, 0); +void timestamp_early_init(uint64_t base) +{ + struct timestamp_cache *ts_cache; + ts_cache = timestamp_cache_get(); + if (ts_cache == NULL) + BUG(); + timestamp_cache_init(ts_cache, base, TIMESTAMP_CBMEM_RESET_REQD); } void timestamp_init(uint64_t base) { + struct timestamp_cache *ts_cache; + struct timestamp_table *tst; + if (!timestamp_should_run()) return; -#ifdef __PRE_RAM__ - /* Copy of basetime, it is too early for CBMEM. */ - car_set_var(ts_basetime, base); -#else - struct timestamp_table *tst = NULL; + ts_cache = timestamp_cache_get(); + + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_REQD; + + tst = timestamp_table_get(); + + if (!tst) { + printk(BIOS_ERR, "ERROR: No timestamp table to init\n"); + return; + } + + tst->base_time = base; +} + +void timestamp_add(enum timestamp_id id, uint64_t ts_time) +{ + struct timestamp_table *ts_table; - /* Locate and use an already existing table. */ - if (!IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) - tst = cbmem_find(CBMEM_ID_TIMESTAMP); + ts_table = timestamp_table_get(); - if (tst) { - car_set_var(ts_table_p, tst); + if (!ts_table) { + printk(BIOS_ERR, "ERROR: No timestamp table found\n"); return; } - /* Copy of basetime, may be too early for CBMEM. */ - car_set_var(ts_basetime, base); - timestamp_real_init(base); -#endif + timestamp_add_table_entry(ts_table, id, ts_time); +} + +void timestamp_add_now(enum timestamp_id id) +{ + timestamp_add(id, timestamp_get()); } static void timestamp_reinit(int is_recovery) @@ -162,14 +288,7 @@ static void timestamp_reinit(int is_recovery) if (!timestamp_should_run()) return; -#ifdef __PRE_RAM__ - timestamp_real_init(car_get_var(ts_basetime)); -#else - if (!car_get_var(ts_table_p)) - timestamp_init(car_get_var(ts_basetime)); -#endif - if (car_get_var(ts_table_p)) - timestamp_do_sync(); + timestamp_sync(); } /* Call timestamp_reinit CBMEM init hooks. */

1 0

Patch merged into coreboot/master: sandy/ivybridge: use LAPIC timer in SMM
by gerrit＠coreboot.org 02 Jul '15

02 Jul '15

the following patch was just integrated into master: commit a3aa8da2acec28670b724b7897ae054592746674 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 16:58:36 2015 -0700 sandy/ivybridge: use LAPIC timer in SMM This fixes an issue with using the flash driver in SMM for writing the event log through an SMM call. Change-Id: If18c77634cca4563f770f09b0f0797ece24308ce Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10762 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10762 for details. -gerrit

1 0

New patch to review for coreboot: Kconfig: Fix references to obsolete symbols
by Martin Roth 02 Jul '15

02 Jul '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10766 -gerrit commit f1563b38c0f48ebbc67d9f1e5ffa31f6a497769f Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Jul 1 23:09:42 2015 -0600 Kconfig: Fix references to obsolete symbols These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/google/foster/Kconfig | 1 - src/mainboard/google/smaug/Kconfig | 1 - src/mainboard/iwave/iWRainbowG6/Kconfig | 1 - src/mainboard/siemens/mc_tcu3/Kconfig | 1 - src/northbridge/intel/haswell/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 6 +----- src/soc/intel/broadwell/Kconfig | 2 +- src/soc/nvidia/tegra210/Kconfig | 4 ++-- 8 files changed, 4 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 765efc7..b8fe708 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHROMEOS_VBNV_FLASH select SPI_FLASH select SOC_NVIDIA_TEGRA210 - select MAINBOARD_HAS_BOOTBLOCK_INIT select MAINBOARD_HAS_CHROMEOS select VIRTUAL_DEV_SWITCH select BOOTROM_SDRAM_INIT # use BootRom to config sdram diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 79bc732..73a40e1 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SOC_NVIDIA_TEGRA210 select MAINBOARD_DO_DSI_INIT - select MAINBOARD_HAS_BOOTBLOCK_INIT select MAINBOARD_HAS_CHROMEOS select VIRTUAL_DEV_SWITCH select RAM_CODE_SUPPORT diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 7bca220..5e92cfb 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_SCH select HAVE_PIRQ_TABLE # select HAVE_MP_TABLE - select USE_PRINTK_IN_CAR select UDELAY_LAPIC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 9eb396b..a4939bf 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select INCLUDE_MICROCODE_IN_BUILD select ENABLE_BUILTIN_COM1 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select ENABLE_FSP_FAST_BOOT diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index c5b8088..0a251b8 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -21,7 +21,6 @@ config NORTHBRIDGE_INTEL_HASWELL bool select CACHE_MRC_BIN select CPU_INTEL_HASWELL - select REQUIRES_BLOB select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select INTEL_DDI diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index dac38ce..5b6fa10 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -14,12 +14,9 @@ config CPU_SPECIFIC_OPTIONS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - select CACHE_ROM - select CAR_MIGRATION select COLLECT_TIMESTAMPS - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select DYNAMIC_CBMEM select ENABLE_MRC_CACHE select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER @@ -39,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_STACK select SOC_INTEL_COMMON_STAGE_CACHE - select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6ad9113..5da8a33 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -160,7 +160,7 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n - select CONSOLE_SERIAL8250MEM + select DRIVERS_UART_8250MEM config INTEL_PCH_UART_CONSOLE_NUMBER hex "Serial IO UART number to use for console" diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 9a707fa..7aa932a 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -50,7 +50,7 @@ config MAX_CPUS choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_TEGRA210_UARTA - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_TEGRA210_UARTA bool "UARTA" @@ -81,7 +81,7 @@ endchoice config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC

1 0

New patch to review for coreboot: don't submit: drop vboot makefiles, and fully integrate in coreboot
by Stefan Reinauer 02 Jul '15

02 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10765 -gerrit commit fb837706bf7eb47fc791115dacadcb97f74e929a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 19:03:52 2015 -0700 don't submit: drop vboot makefiles, and fully integrate in coreboot Change-Id: I2b40a9d35f6d662db6b31b0413a57c5cef80dc97 --- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 23 +++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index 9026df6..8d60070 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -71,7 +71,28 @@ $(VB2_LIB): $(obj)/config.h V=$(V) \ fwlib20 -libverstage-srcs += $(VB2_LIB) +#libverstage-srcs += $(VB2_LIB) + +VBOOT=../../../../../3rdparty/vboot + +libverstage-y += $(VBOOT)/firmware/2lib/2api.c +libverstage-y += $(VBOOT)/firmware/2lib/2common.c +libverstage-y += $(VBOOT)/firmware/2lib/2crc8.c +libverstage-y += $(VBOOT)/firmware/2lib/2misc.c +libverstage-y += $(VBOOT)/firmware/2lib/2nvstorage.c +libverstage-y += $(VBOOT)/firmware/2lib/2rsa.c +libverstage-y += $(VBOOT)/firmware/2lib/2secdata.c +libverstage-y += $(VBOOT)/firmware/2lib/2sha1.c +libverstage-y += $(VBOOT)/firmware/2lib/2sha256.c +libverstage-y += $(VBOOT)/firmware/2lib/2sha512.c +libverstage-y += $(VBOOT)/firmware/2lib/2sha_utility.c +libverstage-y += $(VBOOT)/firmware/2lib/2tpm_bootmode.c +libverstage-y += $(VBOOT)/firmware/lib20/api.c +libverstage-y += $(VBOOT)/firmware/lib20/common.c +libverstage-y += $(VBOOT)/firmware/lib20/misc.c +libverstage-y += $(VBOOT)/firmware/lib20/packed_key.c +libverstage-c-ccopts += -I3rdparty/vboot/firmware/2lib/include +libverstage-c-ccopts += -I3rdparty/vboot/firmware/lib20/include ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/verstage

1 0

New patch to review for coreboot: Kconfig whitespace cleanup: Change leading spaces to tabs
by Martin Roth 02 Jul '15

02 Jul '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10764 -gerrit commit 8eeac6d80834ef42f6e4326f3dec9c1632bbf2b6 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Jul 1 19:38:29 2015 -0600 Kconfig whitespace cleanup: Change leading spaces to tabs Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/google/foster/Kconfig | 14 +++++++------- src/mainboard/google/smaug/Kconfig | 14 +++++++------- src/soc/nvidia/tegra210/Kconfig | 4 ++-- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 571a3b1..765efc7 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -20,7 +20,7 @@ if BOARD_GOOGLE_FOSTER config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y + def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 select CHROMEOS_VBNV_FLASH @@ -34,16 +34,16 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH_WINBOND config MAINBOARD_DIR - string - default google/foster + string + default google/foster config MAINBOARD_PART_NUMBER - string - default "Foster" + string + default "Foster" config DRAM_SIZE_MB - int - default 2048 + int + default 2048 choice prompt "BCT boot media" diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index e96c7c6..79bc732 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -20,7 +20,7 @@ if BOARD_GOOGLE_SMAUG config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y + def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 select CHROMEOS_VBNV_EC @@ -38,16 +38,16 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAM_CODE_SUPPORT config MAINBOARD_DIR - string - default google/smaug + string + default google/smaug config MAINBOARD_PART_NUMBER - string - default "Smaug" + string + default "Smaug" config DRAM_SIZE_MB - int - default 2048 + int + default 2048 choice prompt "BCT boot media" diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index b0f3a02..9a707fa 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -104,8 +104,8 @@ config TRUSTZONE_CARVEOUT_SIZE_MB # Default to 700MHz. This value is based on nv bootloader setting. config PLLX_KHZ - int - default 700000 + int + default 700000 endif config HAVE_MTC

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Patch merged into coreboot/master: purin: chromeos.c also needed in romstage
by gerrit＠coreboot.org 02 Jul '15

02 Jul '15

the following patch was just integrated into master: commit cdf8ee60711c1773337b9a907435b908420de920 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 14:51:41 2015 -0700 purin: chromeos.c also needed in romstage Otherwise the Chrome OS build won't succeed. Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10760 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10760 for details. -gerrit

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Patch merged into coreboot/master: ME/IFD binaries: Implement sane defaults for file paths
by gerrit＠coreboot.org 02 Jul '15

02 Jul '15

the following patch was just integrated into master: commit cecabc19a536f4600fd7d702277baf8313725a07 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 17:37:57 2015 -0700 ME/IFD binaries: Implement sane defaults for file paths Change-Id: I81298aca07c18359e8e4bf5b2d8926d6b45a30c5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10763 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/10763 for details. -gerrit

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New patch to review for coreboot: ME/IFD binaries: Implement sane defaults for file paths
by Stefan Reinauer 02 Jul '15

02 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10763 -gerrit commit 0611441297ac6e806464db65c6e0daa320d99f03 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 17:37:57 2015 -0700 ME/IFD binaries: Implement sane defaults for file paths Change-Id: I81298aca07c18359e8e4bf5b2d8926d6b45a30c5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/intel/common/firmware/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 092d273..ba278c1 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -35,6 +35,7 @@ config HAVE_IFD_BIN config IFD_BIN_PATH string "Path and filename of the descriptor.bin file" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD config HAVE_ME_BIN @@ -52,6 +53,7 @@ config HAVE_ME_BIN config ME_BIN_PATH string "Path to management engine firmware" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" depends on HAVE_ME_BIN ##### Fake IFD #####

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coreboot-gerrit July 2015