Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10816
-gerrit
commit 0329a29c2b15912c788a3a1aeb7e567eb362594b
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue Jul 7 00:26:59 2015 +0200
xcompile: Fix compiler invocation in testcc
While for GCC targets the compiler is just defined as a single
binary, for clang it is defined as a binary and some options, e.g.:
clang -target i386-elf -ccc-gcc-name i386-elf-gcc
When executing the compiler with "$1", the shell will look for a
binary with the above name (instead of just clang) and always fail
detection of any CFLAGS.
By adding -c we prevent the compiler from failing because it can't
link a user space program (when what we're looking for, is whether
a specific compiler flag can be used to compile a coreboot object
file)
Change-Id: I1e9ff32fe40efbe3224c69785f31bc277f21d21b
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
util/xcompile/xcompile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index c671172..7ae1e39 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -72,7 +72,7 @@ testcc() {
local tmp_o="$TMPFILE.o"
rm -f "$tmp_c" "$tmp_o"
echo "void _start(void) {}" >"$tmp_c"
- "$1" -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1
+ $1 -nostdlib -Werror $2 -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1
}
testas() {
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10815
-gerrit
commit 425effb8253dd5b87172a3d10713fe36e3f06ffe
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue Jul 7 00:20:42 2015 +0200
buildgcc: work around bug in --print-librt-file-name
Running "clang -target i386-elf --print-librt-file-name" prints
[..]/bin/../lib/clang/3.6.1/lib/libclang_rt.builtins-i386.a
However, the correct path is [..]/lib/linux/libclang_rt.builtins-i386.a
on a Linux host. Hence, create symbolic links to make sure that our
build system finds the file where it expects it.
Change-Id: I21ef5c4a690d83c326717ca55c5ace558257a0ec
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
util/crossgcc/buildgcc | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index e0b4ed4..367f4d1 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -480,6 +480,13 @@ build_LLVM() {
cp -a ../$CFE_DIR/tools/scan-build/* $DESTDIR$TARGETDIR/bin
cp -a ../$CFE_DIR/tools/scan-view/* $DESTDIR$TARGETDIR/bin
+
+ # create symlinks to work around broken --print-librt-file-name
+ # when used with -target.
+ cd $DESTDIR$TARGETDIR/lib/clang/${CLANG_VERSION}/lib
+ for i in */libclang_rt.builtins*.a; do
+ ln -s $i .
+ done
}
printf "${blue}Welcome to the ${red}coreboot${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n"
the following patch was just integrated into master:
commit 0004ae8f4bf13e549474c5db998f4708fb0b88e8
Author: Alexander Couzens <lynxis(a)fe80.eu>
Date: Thu Jul 2 19:48:22 2015 +0200
util/ectool: don't dump the whole ram when writing to it
Change-Id: Ib2f417ff91862c71de32b3f8929d2017a725ea47
Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu>
Reviewed-on: http://review.coreboot.org/10767
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/10767 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10806
-gerrit
commit 34ec39604747d595d2e7a6d788eea273987864a0
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Jul 6 09:31:42 2015 +0000
gitconfig: Improve robustness when blobs aren't present
With no blobs present the 'make gitconfig' target failed when
trying to add a file to a directory which doesn't exist.
Only try to deal with blobs if they're around.
Change-Id: I27ed33e2e22bb1571bc73fe55cf45aa1e2310bf1
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
Makefile.inc | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 2f1fe82..a6a8431 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -426,10 +426,11 @@ gitconfig:
fi; \
done
# Now set up thehooks for 3rdparty/blobs
- if [ util/gitconfig/commit-msg -nt .git/modules/3rdparty/hooks/commit-msg -o \
- ! -x .git/modules/3rdparty/hooks/commit-msg ]; then \
- sed -e "s,%MAKE%,$(MAKE),g" util/gitconfig/commit-msg > .git/modules/3rdparty/hooks/commit-msg; \
- chmod +x .git/modules/3rdparty/hooks/commit-msg; \
+ if [ -d .git/modules/3rdparty -a \
+ \( util/gitconfig/commit-msg -nt .git/modules/3rdparty/hooks/commit-msg -o \
+ ! -x .git/modules/3rdparty/hooks/commit-msg \) ]; then \
+ sed -e "s,%MAKE%,$(MAKE),g" util/gitconfig/commit-msg > .git/modules/3rdparty/hooks/commit-msg; \
+ chmod +x .git/modules/3rdparty/hooks/commit-msg; \
fi
[ -d 3rdparty/blobs ] && cd 3rdparty/blobs && git config remote.origin.push HEAD:refs/for/master
git config remote.origin.push HEAD:refs/for/master
Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10807
-gerrit
commit 182af0e2e14b803d3f83f8d505277707e5db16e4
Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
Date: Mon Jul 6 08:07:50 2015 -0500
smscsuperio: map interrupt in smscsuperio_enable_serial()
This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the
interrupt is unmapped at reset, but for whatever reason the chip is
inaccessible in smscsuperio/superio.c::enable_dev() and thus the
devicetree.cb IRQ information is not applied in ramstage and then
serial console output fails to work for more than the UART FIFO depth
in the OS.
Change-Id: I00998088975569516f7caeb7f4098b48fe437889
Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
---
src/superio/smsc/smscsuperio/early_serial.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c
index 3eb9347..0d5d6d0 100644
--- a/src/superio/smsc/smscsuperio/early_serial.c
+++ b/src/superio/smsc/smscsuperio/early_serial.c
@@ -55,6 +55,14 @@ void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase)
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ switch (iobase) {
+ case 0x03f8:
+ pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
+ break;
+ case 0x02f8:
+ pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
+ break;
+ }
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
the following patch was just integrated into master:
commit 5a2bd0b69313aabcff7e7965494429c0b8dbdda4
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Jul 6 18:18:22 2015 +0200
Revert "sandy/ivybridge: use LAPIC timer in SMM"
This reverts commit a3aa8da2acec28670b724b7897ae054592746674.
Chrome OS builds require the monotonic timer API in SMM for ELOG_GSMI,
but sandy/ivy doesn't provide it. The commit tried to work around that
by using generic LAPIC code instead, but this leads to multiple
definition errors in other configurations (and it may be unreliable once
the OS reconfigured the APIC timers anyhow).
This fixes the situation for the non-ELOG_GSMI case (which is more or
less everybody but Chrome OS). ELOG_GSMI requires a separate fix.
Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/10811
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/10811 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10811
-gerrit
commit 7c1ac30fff5df07fb13fcce693f217491080a8e7
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Jul 6 18:18:22 2015 +0200
Revert "sandy/ivybridge: use LAPIC timer in SMM"
This reverts commit a3aa8da2acec28670b724b7897ae054592746674.
Chrome OS builds require the monotonic timer API in SMM for ELOG_GSMI,
but sandy/ivy doesn't provide it. The commit tried to work around that
by using generic LAPIC code instead, but this leads to multiple
definition errors in other configurations (and it may be unreliable once
the OS reconfigured the APIC timers anyhow).
This fixes the situation for the non-ELOG_GSMI case (which is more or
less everybody but Chrome OS). ELOG_GSMI requires a separate fix.
Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/cpu/x86/lapic/Makefile.inc | 3 --
src/northbridge/intel/sandybridge/Makefile.inc | 1 +
src/northbridge/intel/sandybridge/udelay.c | 55 ++++++++++++++++++++++++++
3 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index baa8292..3061024 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -3,8 +3,5 @@ ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
-ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y)
-smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
-endif
romstage-y += boot_cpu.c
ramstage-y += boot_cpu.c
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 60765f2..cf79459 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -42,6 +42,7 @@ romstage-y += early_init.c
romstage-y += report_platform.c
romstage-y += ../../../arch/x86/lib/walkcbfs.S
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
# We don't ship that, but booting without it is bound to fail
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
new file mode 100644
index 0000000..b150253
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz
+ */
+
+void udelay(u32 us)
+{
+ u32 dword;
+ tsc_t tsc, tsc1, tscd;
+ msr_t msr;
+ u32 fsb = 100, divisor;
+ u32 d; /* ticks per us */
+
+ msr = rdmsr(0xce);
+ divisor = (msr.lo >> 8) & 0xff;
+
+ d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+ multiply_to_tsc(&tscd, us, d);
+
+ tsc1 = rdtsc();
+ dword = tsc1.lo + tscd.lo;
+ if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+ tsc1.hi++;
+ }
+ tsc1.lo = dword;
+ tsc1.hi += tscd.hi;
+
+ do {
+ tsc = rdtsc();
+ } while ((tsc.hi < tsc1.hi)
+ || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10813
-gerrit
commit 8d4b38e8b3c4b732046742331c3b92d418384193
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Jul 6 20:50:33 2015 +0200
sandybridge: provide monotonic timer function
This fixes building the ELOG_GSMI feature by using the TSC as time source for
the flash drivers.
It's not the most precise clock, but should be good enough for the purpose.
Change-Id: I2d416c34268236228300a9e868628c35e22bf40c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/northbridge/intel/sandybridge/udelay.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
index b150253..7c98380 100644
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -53,3 +53,23 @@ void udelay(u32 us)
} while ((tsc.hi < tsc1.hi)
|| ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
}
+
+#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__)
+#include <timer.h>
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ tsc_t tsc;
+ msr_t msr;
+ u32 fsb = 100, divisor;
+ u32 d; /* ticks per us */
+
+ msr = rdmsr(0xce);
+ divisor = (msr.lo >> 8) & 0xff;
+ d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+
+ tsc = rdtsc();
+
+ mt->microseconds = (long)((((uint64_t)tsc.hi << 32) | tsc.lo) / d);
+}
+#endif