coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

New patch to review for coreboot: xcompile: Fix compiler invocation in testcc
by Stefan Reinauer 06 Jul '15

06 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10816 -gerrit commit 0329a29c2b15912c788a3a1aeb7e567eb362594b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 00:26:59 2015 +0200 xcompile: Fix compiler invocation in testcc While for GCC targets the compiler is just defined as a single binary, for clang it is defined as a binary and some options, e.g.: clang -target i386-elf -ccc-gcc-name i386-elf-gcc When executing the compiler with "$1", the shell will look for a binary with the above name (instead of just clang) and always fail detection of any CFLAGS. By adding -c we prevent the compiler from failing because it can't link a user space program (when what we're looking for, is whether a specific compiler flag can be used to compile a coreboot object file) Change-Id: I1e9ff32fe40efbe3224c69785f31bc277f21d21b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index c671172..7ae1e39 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -72,7 +72,7 @@ testcc() { local tmp_o="$TMPFILE.o" rm -f "$tmp_c" "$tmp_o" echo "void _start(void) {}" >"$tmp_c" - "$1" -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 + $1 -nostdlib -Werror $2 -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 } testas() {

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New patch to review for coreboot: buildgcc: work around bug in --print-librt-file-name
by Stefan Reinauer 06 Jul '15

06 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10815 -gerrit commit 425effb8253dd5b87172a3d10713fe36e3f06ffe Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 00:20:42 2015 +0200 buildgcc: work around bug in --print-librt-file-name Running "clang -target i386-elf --print-librt-file-name" prints [..]/bin/../lib/clang/3.6.1/lib/libclang_rt.builtins-i386.a However, the correct path is [..]/lib/linux/libclang_rt.builtins-i386.a on a Linux host. Hence, create symbolic links to make sure that our build system finds the file where it expects it. Change-Id: I21ef5c4a690d83c326717ca55c5ace558257a0ec Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e0b4ed4..367f4d1 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -480,6 +480,13 @@ build_LLVM() { cp -a ../$CFE_DIR/tools/scan-build/* $DESTDIR$TARGETDIR/bin cp -a ../$CFE_DIR/tools/scan-view/* $DESTDIR$TARGETDIR/bin + + # create symlinks to work around broken --print-librt-file-name + # when used with -target. + cd $DESTDIR$TARGETDIR/lib/clang/${CLANG_VERSION}/lib + for i in */libclang_rt.builtins*.a; do + ln -s $i . + done } printf "${blue}Welcome to the ${red}coreboot${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n"

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Patch merged into coreboot/master: util/ectool: don't dump the whole ram when writing to it
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 0004ae8f4bf13e549474c5db998f4708fb0b88e8 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jul 2 19:48:22 2015 +0200 util/ectool: don't dump the whole ram when writing to it Change-Id: Ib2f417ff91862c71de32b3f8929d2017a725ea47 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/10767 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10767 for details. -gerrit

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New patch to review for coreboot: T210: UTMIP: Correct UTMIP PLL programming as per Mark Kuo
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10814 -gerrit commit 0c53b0f9a7f03098517f065b8ffa8253af9603e8 Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Jun 30 10:22:12 2015 -0700 T210: UTMIP: Correct UTMIP PLL programming as per Mark Kuo BUG=chrome-os-partner:39603 BRANCH=none TEST=Built OK for Smaug. Change-Id: Iba170d8ad6f1dff111421fd61f71da19de57efaa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1bf1c1442dacf45bac5d55b05ada99a2c96f2e45 Original-Change-Id: Iecf04691a637b56e2f2287ab7d4d0cdda0382421 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282720 Original-Reviewed-by: Andrew Bresticker <abrestic(a)chromium.org> Original-Reviewed-by: Mark Kuo <mkuo(a)nvidia.com> --- src/soc/nvidia/tegra210/clock.c | 36 ++++++++++++++------------- src/soc/nvidia/tegra210/include/soc/clk_rst.h | 9 +++++-- 2 files changed, 26 insertions(+), 19 deletions(-) diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index aa72340..394c781 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -328,19 +328,9 @@ static void init_utmip_pll(void) { int khz = clock_get_pll_input_khz(); - /* Shut off PLL crystal clock while we mess with it */ - clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), UTMIP_CFG2_PHY_XTAL_CLOCKEN); - udelay(1); - - /* CFG0 */ - u32 div_n = div_round_up(960000, khz); - write32(CLK_RST_REG(utmip_pll_cfg0), /* 960 MHz VCO */ - 1 << UTMIP_CFG0_PLL_MDIV_SHIFT | - div_n << UTMIP_CFG0_PLL_NDIV_SHIFT); - /* CFG1 */ - u32 pllu_enb_ct = div_round_up(khz, 8000); /* pllu_enb_ct / 8 (1us) */ - u32 phy_stb_ct = div_round_up(khz, 102); /* phy_stb_ct / 256(2.5ms) */ + u32 pllu_enb_ct = 0; + u32 phy_stb_ct = div_round_up(khz, 300); /* phy_stb_ct = 128 */ write32(CLK_RST_REG(utmip_pll_cfg1), pllu_enb_ct << UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT | UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE | @@ -350,16 +340,28 @@ static void init_utmip_pll(void) phy_stb_ct << UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT); /* CFG2 */ - u32 pllu_stb_ct = div_round_up(khz, 256); /* pllu_stb_ct / 256 (1ms) */ - u32 phy_act_ct = div_round_up(khz, 3200); /* phy_act_ct / 16 (5us) */ + u32 pllu_stb_ct = 0; + u32 phy_act_ct = div_round_up(khz, 6400); /* phy_act_ct = 6 */ write32(CLK_RST_REG(utmip_pll_cfg2), phy_act_ct << UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT | pllu_stb_ct << UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT | + UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE | UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE | UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE | - UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE); - - setbits_le32(CLK_RST_REG(utmip_pll_cfg2), UTMIP_CFG2_PHY_XTAL_CLOCKEN); + UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE | + UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE | + UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE | + UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE | + UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE); + + printk(BIOS_DEBUG, "%s: UTMIPLL_HW_PWRDN_CFG0:0x%08x\n", + __func__, read32(CLK_RST_REG(utmipll_hw_pwrdn_cfg0))); + printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG0:0x%08x\n", + __func__, read32(CLK_RST_REG(utmip_pll_cfg0))); + printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG1:0x%08x\n", + __func__, read32(CLK_RST_REG(utmip_pll_cfg1))); + printk(BIOS_DEBUG, "%s: UTMIP_PLL_CFG2:0x%08x\n", + __func__, read32(CLK_RST_REG(utmip_pll_cfg2))); } /* Graphics just has to be different. There's a few more bits we diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 60ee112..817a041 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -428,14 +428,19 @@ enum { #define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE (0 << 12) #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE (0 << 14) #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE (1 << 15) -#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE (1 << 16) +#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE (1 << 16) #define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT (27) #define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE (0 << 0) +#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE (1 << 1) #define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE (0 << 2) +#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE (1 << 3) #define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE (0 << 4) +#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE (1 << 5) +#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE (0 << 24) +#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE (1 << 25) #define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT (6) #define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT (18) -#define UTMIP_CFG2_PHY_XTAL_CLOCKEN (1U << 30) +#define UTMIP_CFG2_PHY_XTAL_CLOCKEN (1U << 30) /* Generic, indiscriminate divisor mask. May catch some innocent bystander bits * on the side that we don't particularly care about. */

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Patch set updated for coreboot: gitconfig: Improve robustness when blobs aren't present
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10806 -gerrit commit 34ec39604747d595d2e7a6d788eea273987864a0 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:31:42 2015 +0000 gitconfig: Improve robustness when blobs aren't present With no blobs present the 'make gitconfig' target failed when trying to add a file to a directory which doesn't exist. Only try to deal with blobs if they're around. Change-Id: I27ed33e2e22bb1571bc73fe55cf45aa1e2310bf1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 2f1fe82..a6a8431 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -426,10 +426,11 @@ gitconfig: fi; \ done # Now set up thehooks for 3rdparty/blobs - if [ util/gitconfig/commit-msg -nt .git/modules/3rdparty/hooks/commit-msg -o \ - ! -x .git/modules/3rdparty/hooks/commit-msg ]; then \ - sed -e "s,%MAKE%,$(MAKE),g" util/gitconfig/commit-msg > .git/modules/3rdparty/hooks/commit-msg; \ - chmod +x .git/modules/3rdparty/hooks/commit-msg; \ + if [ -d .git/modules/3rdparty -a \ + $ util/gitconfig/commit-msg -nt .git/modules/3rdparty/hooks/commit-msg -o \ + ! -x .git/modules/3rdparty/hooks/commit-msg $ ]; then \ + sed -e "s,%MAKE%,$(MAKE),g" util/gitconfig/commit-msg > .git/modules/3rdparty/hooks/commit-msg; \ + chmod +x .git/modules/3rdparty/hooks/commit-msg; \ fi [ -d 3rdparty/blobs ] && cd 3rdparty/blobs && git config remote.origin.push HEAD:refs/for/master git config remote.origin.push HEAD:refs/for/master

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Patch set updated for coreboot: util/cbfstool: use _XOPEN_SOURCE=700 to find strdup(3)
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10809 -gerrit commit 380d5ec8b88ec2878d16ceea5cfb0a4ba8d082a0 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:29:00 2015 -0500 util/cbfstool: use _XOPEN_SOURCE=700 to find strdup(3) Change-Id: I974c6c8733356cc8ea4e0505136a34b6055abf0c Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- util/cbfstool/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index dde8c68..976f0c2 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -45,7 +45,7 @@ TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h -TOOLCPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h +TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool

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Patch set updated for coreboot: smscsuperio: map interrupt in smscsuperio_enable_serial()
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10807 -gerrit commit 182af0e2e14b803d3f83f8d505277707e5db16e4 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:07:50 2015 -0500 smscsuperio: map interrupt in smscsuperio_enable_serial() This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the interrupt is unmapped at reset, but for whatever reason the chip is inaccessible in smscsuperio/superio.c::enable_dev() and thus the devicetree.cb IRQ information is not applied in ramstage and then serial console output fails to work for more than the UART FIFO depth in the OS. Change-Id: I00998088975569516f7caeb7f4098b48fe437889 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/superio/smsc/smscsuperio/early_serial.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 3eb9347..0d5d6d0 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -55,6 +55,14 @@ void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + switch (iobase) { + case 0x03f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + break; + case 0x02f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + break; + } pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); }

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Patch merged into coreboot/master: Revert "sandy/ivybridge: use LAPIC timer in SMM"
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 5a2bd0b69313aabcff7e7965494429c0b8dbdda4 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 18:18:22 2015 +0200 Revert "sandy/ivybridge: use LAPIC timer in SMM" This reverts commit a3aa8da2acec28670b724b7897ae054592746674. Chrome OS builds require the monotonic timer API in SMM for ELOG_GSMI, but sandy/ivy doesn't provide it. The commit tried to work around that by using generic LAPIC code instead, but this leads to multiple definition errors in other configurations (and it may be unreliable once the OS reconfigured the APIC timers anyhow). This fixes the situation for the non-ELOG_GSMI case (which is more or less everybody but Chrome OS). ELOG_GSMI requires a separate fix. Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10811 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10811 for details. -gerrit

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Patch set updated for coreboot: Revert "sandy/ivybridge: use LAPIC timer in SMM"
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10811 -gerrit commit 7c1ac30fff5df07fb13fcce693f217491080a8e7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 18:18:22 2015 +0200 Revert "sandy/ivybridge: use LAPIC timer in SMM" This reverts commit a3aa8da2acec28670b724b7897ae054592746674. Chrome OS builds require the monotonic timer API in SMM for ELOG_GSMI, but sandy/ivy doesn't provide it. The commit tried to work around that by using generic LAPIC code instead, but this leads to multiple definition errors in other configurations (and it may be unreliable once the OS reconfigured the APIC timers anyhow). This fixes the situation for the non-ELOG_GSMI case (which is more or less everybody but Chrome OS). ELOG_GSMI requires a separate fix. Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/cpu/x86/lapic/Makefile.inc | 3 -- src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/udelay.c | 55 ++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index baa8292..3061024 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -3,8 +3,5 @@ ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y) -smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -endif romstage-y += boot_cpu.c ramstage-y += boot_cpu.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 60765f2..cf79459 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S +smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c new file mode 100644 index 0000000..b150253 --- /dev/null +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> + +/** + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 100, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(0xce); + divisor = (msr.lo >> 8) & 0xff; + + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + multiply_to_tsc(&tscd, us, d); + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}

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Patch set updated for coreboot: sandybridge: provide monotonic timer function
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10813 -gerrit commit 8d4b38e8b3c4b732046742331c3b92d418384193 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 20:50:33 2015 +0200 sandybridge: provide monotonic timer function This fixes building the ELOG_GSMI feature by using the TSC as time source for the flash drivers. It's not the most precise clock, but should be good enough for the purpose. Change-Id: I2d416c34268236228300a9e868628c35e22bf40c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/northbridge/intel/sandybridge/udelay.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index b150253..7c98380 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -53,3 +53,23 @@ void udelay(u32 us) } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); } + +#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__) +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + tsc_t tsc; + msr_t msr; + u32 fsb = 100, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(0xce); + divisor = (msr.lo >> 8) & 0xff; + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + + tsc = rdtsc(); + + mt->microseconds = (long)((((uint64_t)tsc.hi << 32) | tsc.lo) / d); +} +#endif

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coreboot-gerrit July 2015