coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: libpayload: drop LIBGCC_FILE_NAME variable
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 46eeb339e978ab8059d8ecf2e74c094f6c928883 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:06:27 2015 +0000 libpayload: drop LIBGCC_FILE_NAME variable It's unused. If we need something like that, .xcompile provides it, and in a cross-platform and clang-aware way. Change-Id: Ic1bdc2e3e252d612a5b99ad4e8caebc5158a485f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10802 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10802 for details. -gerrit

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Patch merged into coreboot/master: libpayload: defer including .xcompile
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit db0325591d5abe39544602b92cc141f7ba4d6f5a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:05:48 2015 +0000 libpayload: defer including .xcompile It needs to come after DOTCONFIG so that the compiler decision can be made. Change-Id: I5c6730ac58ab8731f07bb7c5161b2d0a59588e28 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10801 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Add compiler switch
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit b7d8f26eec171aa6964cf617221aeb2eaec0a976 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:04:42 2015 +0000 libpayload: Add compiler switch clang is totally untested, but it mirrors coreboot now. Change-Id: I0e13ff8bba2007159a4a795ca07d187504b606b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10800 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10800 for details. -gerrit

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Patch merged into coreboot/master: libpayload: mark util/xcompile/xcompile executable
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 3f02466b002c721d7e5f8bc37d0598bb5b880037 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:02:51 2015 +0000 libpayload: mark util/xcompile/xcompile executable Change-Id: I97088df1550f580d4648c7cccbd81c696fcfe2dc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10799 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10799 for details. -gerrit

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New patch to review for coreboot: Revert "sandy/ivybridge: use LAPIC timer in SMM"
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10811 -gerrit commit 375c5ffa63301aa5c185074dd4a59499a5ee4263 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 18:18:22 2015 +0200 Revert "sandy/ivybridge: use LAPIC timer in SMM" This reverts commit a3aa8da2acec28670b724b7897ae054592746674. There's still a problem for Chrome OS builds, but we need to fix it in a way that doesn't make everything else explode. Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/cpu/x86/lapic/Makefile.inc | 3 -- src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/udelay.c | 55 ++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index baa8292..3061024 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -3,8 +3,5 @@ ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y) -smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -endif romstage-y += boot_cpu.c ramstage-y += boot_cpu.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 60765f2..cf79459 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S +smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c new file mode 100644 index 0000000..b150253 --- /dev/null +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> + +/** + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 100, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(0xce); + divisor = (msr.lo >> 8) & 0xff; + + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + multiply_to_tsc(&tscd, us, d); + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}

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Patch set updated for coreboot: libpayload: Add compiler switch
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10800 -gerrit commit da69f6945993d8bc37e4b660de010eb62ded6063 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:04:42 2015 +0000 libpayload: Add compiler switch clang is totally untested, but it mirrors coreboot now. Change-Id: I0e13ff8bba2007159a4a795ca07d187504b606b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/Kconfig | 18 ++++++++++++++++++ payloads/libpayload/util/xcompile/xcompile | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 77d4f6b..dee970c 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -55,6 +55,24 @@ config DEVELOPER Prompt for developer options. These options are only interesting for libpayload developers. +choice + prompt "Compiler to use" + default COMPILER_GCC + help + This option allows you to select the compiler. + +config COMPILER_GCC + bool "GCC" + help + Use the GNU Compiler Collection (GCC). + +config COMPILER_LLVM_CLANG + bool "LLVM/clang" + help + Use LLVM/clang. + +endchoice + config REMOTEGDB bool "Remote GDB stub" default n diff --git a/payloads/libpayload/util/xcompile/xcompile b/payloads/libpayload/util/xcompile/xcompile index 1af02ad..b6759a9 100755 --- a/payloads/libpayload/util/xcompile/xcompile +++ b/payloads/libpayload/util/xcompile/xcompile @@ -182,7 +182,7 @@ report_arch_toolchain() { # elf${TWIDTH}-${TBFDARCH} toolchain (${GCC}) ARCH_SUPPORTED+=${TARCH} SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} -ifeq (\$(CONFIG_COMPILER_GCC),y) +ifeq (\$(CONFIG_LP_COMPILER_GCC),y) CC_${TARCH}:=${GCC} CFLAGS_${TARCH}:=${CFLAGS_GCC} COMPILER_RT_${TARCH}:=${CC_RT_GCC}

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New patch to review for coreboot: util/cbfstool: don't override ntohl(3) and htonl(3) on NetBSD
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10810 -gerrit commit b536e2b07b5514779da8d7bcf445a1ed6aa9219f Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:30:13 2015 -0500 util/cbfstool: don't override ntohl(3) and htonl(3) on NetBSD Change-Id: I9bfc017dee86fe6cbc51de99f46429d53efe7d11 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- util/cbfstool/common.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 7fa7c7e..06ee00b 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -28,9 +28,11 @@ /* Endianess */ #include "swab.h" -#ifndef __APPLE__ +#if !defined(__APPLE__) && !defined(__NetBSD__) #define ntohl(x) (is_big_endian() ? (uint32_t)(x) : swab32(x)) #define htonl(x) (is_big_endian() ? (uint32_t)(x) : swab32(x)) +#elif defined(__NetBSD__) +#include <arpa/inet.h> #endif #define ntohll(x) (is_big_endian() ? (uint64_t)(x) : swab64(x)) #define htonll(x) (is_big_endian() ? (uint64_t)(x) : swab64(x))

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New patch to review for coreboot: util/cbfstool: find strdup(3) on NetBSD
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10809 -gerrit commit 972c6a84c0729424bc3b4fcaa24619b8723754fb Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:29:00 2015 -0500 util/cbfstool: find strdup(3) on NetBSD Change-Id: I974c6c8733356cc8ea4e0505136a34b6055abf0c Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- util/cbfstool/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index dde8c68..19e9414 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -46,6 +46,9 @@ TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h TOOLCPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h +ifeq ($(shell uname -s), NetBSD) +TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h +endif TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool

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New patch to review for coreboot: util/xcompile/xcompile: use env(1) to find bash
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10808 -gerrit commit 16fa5ea10f3dc50adbc2e7d37328b98e58203d7d Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:22:45 2015 -0500 util/xcompile/xcompile: use env(1) to find bash Not all systems put bash at /bin/bash. Change-Id: Ib58cd2f6cf330b5b2678d55bb929696872fba9c9 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index d2509db..c671172 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # # This file is part of the coreboot project. #

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Patch set updated for coreboot: smscsuperio: map interrupt in smscsuperio_enable_serial()
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10807 -gerrit commit 7f10499ea9dbc90d8822ba97a993aad56e8651f6 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:07:50 2015 -0500 smscsuperio: map interrupt in smscsuperio_enable_serial() This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the interrupt is unmapped at reset, but for whatever reason the chip is inaccessible in smscsuperio/superio.c::enable_dev() and thus the devicetree.cb IRQ information is not applied in ramstage and then serial console output fails to work for more than the UART FIFO depth in the OS. Change-Id: I00998088975569516f7caeb7f4098b48fe437889 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/superio/smsc/smscsuperio/early_serial.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 3eb9347..fd26169 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -55,6 +55,10 @@ void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + if (iobase == 0x03f8) + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + if (iobase == 0x02f8) + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); }

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coreboot-gerrit July 2015