coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: libpayload: usb: dwc2: support interrupt transfer
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit aa33609d289c4ee07ec10e4825bc055492fa107c Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Fri Jun 19 17:09:04 2015 +0800 libpayload: usb: dwc2: support interrupt transfer dwc2 host core do not have a periodic schedule list, so try to send an interrupt packet in poll_intr_queue() function and use frame number read from usb core register to calculate time and schedule transfers. BUG=None TEST=Tested on RK3288 with two USB keyboards(connect to SoC without USB hub), both work correctly. BRANCH=None Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157 Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280750 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Reviewed-on: http://review.coreboot.org/10774 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10774 for details. -gerrit

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Patch merged into coreboot/master: libpayload: arm(64): add read8/16/32 and write8/16/32
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 394933640bc0515617117ed0cb8de7702bc9c1bf Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 25 16:19:49 2015 -0700 libpayload: arm(64): add read8/16/32 and write8/16/32 This applys the same change made by https://chromium-review.googlesource.com/261692 to libpayload. BUG=none BRANCH=tot TEST=built for veyron_jerry, rush_ryu, samus Change-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030 Original-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282541 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10773 for details. -gerrit

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Patch merged into coreboot/master: rockchip: rk3288: correct ddr 300MHz clock setting
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit c2b48e55f1d4bd02a07515164ddcca472bf47351 Author: huang lin <hl(a)rock-chips.com> Date: Tue Jun 30 10:01:14 2015 +0800 rockchip: rk3288: correct ddr 300MHz clock setting CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz setting can't meet this request, so modify it BRANCH=None BUG=None TEST=Set ddr frequency to 300MHz and boot from mickey Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5 Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282445 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10772 for details. -gerrit

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Patch merged into coreboot/master: veyron_danger: EDP changes for v2
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit a1e5a7761ad824ffd8449db02fec9274eb165bc2 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jun 1 15:17:24 2015 -0700 veyron_danger: EDP changes for v2 EDP-related hardware modifications for v2: - BL_EN moved from GPIO7_A3 to GPIO7_A2 - EDP_HPD added to GPIO7_B3 BUG=none BRANCH=none TEST=built and booted Danger v2 with EDP panel attached, saw dev mode screen come up Change-Id: I47383610082b371a612aced656e56f1bd1cfa098 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b Original-Reviewed-on: https://chromium-review.googlesource.com/280855 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10771 for details. -gerrit

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Patch merged into coreboot/master: libpayload: udc: dwc2: support force_shutdown() routine
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit d8a3ed49a59fdf54ac3f311a75dca3e94b13eb26 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Tue Jun 23 17:42:34 2015 +0800 libpayload: udc: dwc2: support force_shutdown() routine Add force_shutdown() routine for dwc2 udc driver to support disconnect and reconnect case when fastboot receiving data. BUG=chrome-os-partner:41687 BRANCH=None TEST=None Change-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9 Original-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281130 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Commit-Queue: Jeffy Chen <jeffy.chen(a)rock-chips.com> Reviewed-on: http://review.coreboot.org/10770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10770 for details. -gerrit

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Patch set updated for coreboot: lenovo/x201: run `enable acpi` smi before s3 resume
by Alexander Couzens 05 Jul '15

05 Jul '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10797 -gerrit commit 14dbdd53a4a35e83314d11460da40c873b612e1f Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jul 2 16:58:19 2015 +0200 lenovo/x201: run `enable acpi` smi before s3 resume Fix missing ec event bug. After multiple suspend resume cycles no EC events are processed because the EC doesn't notice the OSPM anymore. Calling the acpi resume handler fixes this by calling: ec_write(0x80, 0x01); /* discard all events, and enable attention */ Change-Id: I157e69e6e1e643c7b5d94f5efd87adf899b15443 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/mainboard.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 62e4fc9..ff13fb7 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -122,6 +122,12 @@ static void mainboard_enable(device_t dev) } +void mainboard_suspend_resume(void) +{ + /* Enable ACPI mode before OS resume */ + outb(0xe1, 0xb2); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, };

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New patch to review for coreboot: intel sandybridge: add VGA pci device id
by Patrick Rudolph 05 Jul '15

05 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10798 -gerrit commit 12524ca5a73557cdd9666c314f828a5a62ffd579 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 5 13:29:41 2015 +0200 intel sandybridge: add VGA pci device id Add VGA pci device id 0x0152 for Intel IvyBridge CPUs. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: Ia546fdf0cc3bbd4c0ef6b5fd969232f105bceb22 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 21ef223..e77cf22 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -96,6 +96,7 @@ static void sandybridge_setup_graphics(void) case 0x0116: /* GT2 Mobile */ case 0x0122: /* GT2 Desktop >=1.3GHz */ case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0152: /* IvyBridge */ case 0x0156: /* IvyBridge */ case 0x0162: /* IvyBridge */ case 0x0166: /* IvyBridge */

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Patch merged into coreboot/master: nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab
by gerrit＠coreboot.org 05 Jul '15

05 Jul '15

the following patch was just integrated into master: commit 2c2e05ad79f712d33136319bbc5049d3865c0a47 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sat Jul 4 18:44:56 2015 -0500 nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab Change-Id: Ia84df2f4467e102fd5f675dba6432996584d78c1 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10796 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/10796 for details. -gerrit

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Patch set updated for coreboot: lenovo/x201: run `enable acpi` smi before s3 resume
by Alexander Couzens 05 Jul '15

05 Jul '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10797 -gerrit commit 80f065689b413e5ad586f9cbba0ebe2377f31b35 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jul 2 16:58:19 2015 +0200 lenovo/x201: run `enable acpi` smi before s3 resume Fixes missing ec event bug. After multiple suspend resume cycles no EC event are processed because the EC doesn't notice the OSPM anymore. Calling the acpi resume handler fix this by calling: ec_write(0x80, 0x01); /* discard all events, and enable attention */ Change-Id: I157e69e6e1e643c7b5d94f5efd87adf899b15443 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/mainboard.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 62e4fc9..ff13fb7 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -122,6 +122,12 @@ static void mainboard_enable(device_t dev) } +void mainboard_suspend_resume(void) +{ + /* Enable ACPI mode before OS resume */ + outb(0xe1, 0xb2); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, };

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Patch set updated for coreboot: lenovo/x201: run `enable acpi` smi before s3 resume
by Alexander Couzens 05 Jul '15

05 Jul '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10797 -gerrit commit 9468b243c2e0685c034f282f0755aecc0eed8aeb Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jul 2 16:58:19 2015 +0200 lenovo/x201: run `enable acpi` smi before s3 resume Fixes missing ec event bug. After multiple suspend-resume cycle no EC event are processed because the EC doesn't notice the OSPM anymore. Calling the acpi resume handler fix this mainly by calling: ec_write(0x80, 0x01); /* discard all events, and enable attention */ Change-Id: I157e69e6e1e643c7b5d94f5efd87adf899b15443 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/mainboard.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 62e4fc9..ff13fb7 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -122,6 +122,12 @@ static void mainboard_enable(device_t dev) } +void mainboard_suspend_resume(void) +{ + /* Enable ACPI mode before OS resume */ + outb(0xe1, 0xb2); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, };

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coreboot-gerrit July 2015