coreboot-gerrit July 2015

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New patch to review for coreboot: lenovo/x201: run `enable acpi` smi before s3 resume
by Alexander Couzens 05 Jul '15

05 Jul '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10797 -gerrit commit 59b203e29c3a74184a8c2ec0a16075b6d231c247 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jul 2 16:58:19 2015 +0200 lenovo/x201: run `enable acpi` smi before s3 resume Fixes missing ec event bug. After multiple suspend-resume cycle no EC event are processed because the EC doesn't notice the OSPM anymore. Calling the acpi resume handler fix this mainly by calling: ec_write(0x80, 0x01); /* discard all events, and enable attention */ Change-Id: I157e69e6e1e643c7b5d94f5efd87adf899b15443 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/mainboard.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 62e4fc9..c14f699 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -122,6 +122,13 @@ static void mainboard_enable(device_t dev) } +void mainboard_suspend_resume(void) +{ + /* Enable ACPI mode before OS resume */ + outb(0xe1, 0xb2); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; +

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New patch to review for coreboot: nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab
by Jonathan A. Kollasch 04 Jul '15

04 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10796 -gerrit commit f2715a1fde775284a4ae083dcd0109a9ca44dffc Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sat Jul 4 18:44:56 2015 -0500 nvidia/l1_2pvv: whitespace: remove spaces that are followed by tab Change-Id: Ia84df2f4467e102fd5f675dba6432996584d78c1 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/nvidia/l1_2pvv/resourcemap.c | 2 +- src/mainboard/nvidia/l1_2pvv/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/nvidia/l1_2pvv/resourcemap.c b/src/mainboard/nvidia/l1_2pvv/resourcemap.c index b1a6309..62b927b 100644 --- a/src/mainboard/nvidia/l1_2pvv/resourcemap.c +++ b/src/mainboard/nvidia/l1_2pvv/resourcemap.c @@ -270,7 +270,7 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 21112fb..b5731c8 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); + soft_reset(); } allow_all_aps_stop(bsp_apicid);

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Patch merged into coreboot/master: Kconfig: Fix references to obsolete symbols
by gerrit＠coreboot.org 04 Jul '15

04 Jul '15

the following patch was just integrated into master: commit df02c338ef601d1c0fed6e5d8767bf5c5c835507 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Jul 1 23:09:42 2015 -0600 Kconfig: Fix references to obsolete symbols These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10766 for details. -gerrit

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Patch merged into coreboot/master: intel raminit: rename register
by gerrit＠coreboot.org 04 Jul '15

04 Jul '15

the following patch was just integrated into master: commit 8c2f39714f4d6b8f2ab9692669474fb5ada3ed37 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Jul 3 21:11:25 2015 +0200 intel raminit: rename register Found while doing code review. Rename reg_4004_b30 to cmd_stretch. Found in 4th-gen-core-family-desktop-vol-2-datasheet.pdf chapter 4.2.1. Change-Id: Ib07059625ed458332708562e836803f2b587d5d8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: http://review.coreboot.org/10789 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> See http://review.coreboot.org/10789 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Deal with gmp on 32bit Linux on 64bit CPUs
by gerrit＠coreboot.org 04 Jul '15

04 Jul '15

the following patch was just integrated into master: commit ddb8f808940899240411282d0feb1e2f65ef43a9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Jul 4 17:45:54 2015 +0200 buildgcc: Deal with gmp on 32bit Linux on 64bit CPUs GMP is overeager to detect 64bit ABIs even if the entire running codebase is 32bit (but on a 64bit CPU). Enforce a 32bit build in that situation. Change-Id: I23e9e57f3c8b0e3ad2e4e1e3eb106f7830aa76a1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10792 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10792 for details. -gerrit

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Patch merged into coreboot/master: xcompile: ask for compiler runtime using appropriate CFLAGS
by gerrit＠coreboot.org 04 Jul '15

04 Jul '15

the following patch was just integrated into master: commit 8d7b719c0e8c6f50315e6ea8f13ddb188130aa53 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Jul 4 23:28:54 2015 +0200 xcompile: ask for compiler runtime using appropriate CFLAGS xcompile keeps two CFLAGS around now, for GCC and CLANG. Normally they're not required to request the libgcc/compiler-rt path, but with the multilib capable x86_64-elf target it's required to make it pick the right libgcc when used as i386-elf builder. Change-Id: I700e7aa5783dc36698dd2ab8a38642a144e80fe9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10795 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10795 for details. -gerrit

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New patch to review for coreboot: xcompile: ask for compiler runtime using appropriate CFLAGS
by Patrick Georgi 04 Jul '15

04 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10795 -gerrit commit 48bef80c638a2452759458c2511519eddb7d3e9e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Jul 4 23:28:54 2015 +0200 xcompile: ask for compiler runtime using appropriate CFLAGS xcompile keeps two CFLAGS around now, for GCC and CLANG. Normally they're not required to request the libgcc/compiler-rt path, but with the multilib capable x86_64-elf target it's required to make it pick the right libgcc when used as i386-elf builder. Change-Id: I700e7aa5783dc36698dd2ab8a38642a144e80fe9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/xcompile/xcompile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 1af02ad..d2509db 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -172,9 +172,9 @@ detect_special_flags() { detect_compiler_runtime() { test -z "$CLANG" || \ - CC_RT_CLANG="`${CLANG} ${CFLAGS} -print-librt-file-name 2>/dev/null`" + CC_RT_CLANG="`${CLANG} ${CFLAGS_CLANG} -print-librt-file-name 2>/dev/null`" test -z "$GCC" || \ - CC_RT_GCC="`${GCC} ${CFLAGS} -print-libgcc-file-name`" + CC_RT_GCC="`${GCC} ${CFLAGS_GCC} -print-libgcc-file-name`" } report_arch_toolchain() {

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Patch set updated for coreboot: southbridge/intel/bd82x6x: add option to not enable display audio codec
by Nicolas Reinecke 04 Jul '15

04 Jul '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303 -gerrit commit b846322c219cc990e62797b0885b1aa55cb8d47a Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Jul 4 22:44:19 2015 +0200 southbridge/intel/bd82x6x: add option to not enable display audio codec Some Thinkpads like T420s or T520 with discrete GPU have only VGA and LVDS conntected to the IGP. For this devices is it usefull to have an option to not enable audio codec. The audio dev shows up in linux as hdmi codec but is complete useless. Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t420s/devicetree.cb | 3 +++ src/mainboard/lenovo/t520/devicetree.cb | 3 +++ src/southbridge/intel/bd82x6x/azalia.c | 17 ++++++++++------- src/southbridge/intel/bd82x6x/chip.h | 2 ++ 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index cd70228..6648aa5 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -60,6 +60,9 @@ chip northbridge/intel/sandybridge # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" + # not enable audio codec on digital video outups. (for discrete gpu models) + register "azalia_video_codec_not_enable" = "1" + register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index ff9745e..06b1e1c 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -57,6 +57,9 @@ chip northbridge/intel/sandybridge # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" + # not enable audio codec on digital video outups. (for discrete gpu models) + register "azalia_video_codec_not_enable" = "1" + register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 2dd8836..e5a3866 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -229,6 +229,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) static void azalia_init(struct device *dev) { + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; u8 *base; struct resource *res; u32 codec_mask; @@ -268,14 +269,16 @@ static void azalia_init(struct device *dev) reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32); - // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + if (!(config->azalia_video_codec_not_enable)) { + // Enable HDMI codec: + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xc4, reg32); - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + reg8 = pci_read_config8(dev, 0x43); + reg8 |= (1 << 6); + pci_write_config8(dev, 0x43, reg8); + } /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 3fa9192..4d4663a 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -96,6 +96,8 @@ struct southbridge_intel_bd82x6x_config { uint32_t superspeed_capable_ports; /* Overcurrent Mapping for USB 3.0 Ports */ uint32_t xhci_overcurrent_mapping; + /* do not enable audio codec on digital video outputs */ + uint8_t azalia_video_codec_not_enable; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

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New patch to review for coreboot: cbfstool: Make sure CBFS data structures are packed gcc style
by Stefan Reinauer 04 Jul '15

04 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10794 -gerrit commit 4f4b4fe52d5b4562c049ab37506bff7bc795a4fc Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jul 4 11:30:59 2015 -0700 cbfstool: Make sure CBFS data structures are packed gcc style On Windows systems, structs can be packed gcc style or ms style. Make sure we use the same one (gcc style) in our user space tools that we use in coreboot. Change-Id: I7a9ea7368f77fba53206e953b4d5ca219ed4c12e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- util/cbfstool/cbfs.h | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index befdb2f..8092057 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -32,6 +32,12 @@ #define makemagic(b3, b2, b1, b0)\ (((b3)<<24) | ((b2) << 16) | ((b1) << 8) | (b0)) +#if defined(__WIN32) || defined(__WIN64) +#define __PACKED __attribute__((gcc_struct, packed)) +#else +#define __PACKED __attribute__((packed)) +#endif + // Alignment (in bytes) to be used when no master header is present #define CBFS_ENTRY_ALIGNMENT 64 @@ -50,7 +56,7 @@ struct cbfs_header { uint32_t offset; uint32_t architecture; /* Version 2 */ uint32_t pad[1]; -} __attribute__ ((packed)); +} __PACKED; #define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF #define CBFS_ARCHITECTURE_X86 0x00000001 @@ -67,7 +73,7 @@ struct cbfs_file { uint32_t type; uint32_t checksum; uint32_t offset; -} __attribute__ ((packed)); +} __PACKED; struct cbfs_stage { uint32_t compression; @@ -75,7 +81,7 @@ struct cbfs_stage { uint64_t load; uint32_t len; uint32_t memlen; -} __attribute__ ((packed)); +} __PACKED; #define PAYLOAD_SEGMENT_CODE makemagic('C', 'O', 'D', 'E') #define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A') @@ -90,11 +96,11 @@ struct cbfs_payload_segment { uint64_t load_addr; uint32_t len; uint32_t mem_len; -} __attribute__ ((packed)); +} __PACKED; struct cbfs_payload { struct cbfs_payload_segment segments; -} __attribute__ ((packed)); +} __PACKED; /** These are standard component types for well known components (i.e - those that coreboot needs to consume.

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New patch to review for coreboot: cbfstool: Fix kv_pair on Windows
by Stefan Reinauer 04 Jul '15

04 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10793 -gerrit commit c8ff7d447dbb7babc90bdfc266280780ba672334 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jul 4 11:28:03 2015 -0700 cbfstool: Fix kv_pair on Windows On Windows systems the archetype printf defaults to ms_printf instead of gnu_printf. Keep the archetype print for all non- Windows compiles to not break compatibility with other systems out there. Change-Id: Iad8441f4dc814366176646f6a7a5df653fda4c15 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- util/cbfstool/flashmap/kv_pair.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/cbfstool/flashmap/kv_pair.h b/util/cbfstool/flashmap/kv_pair.h index 7024dd3..1185a08 100644 --- a/util/cbfstool/flashmap/kv_pair.h +++ b/util/cbfstool/flashmap/kv_pair.h @@ -108,7 +108,11 @@ extern struct kv_pair *kv_pair_add_bool(struct kv_pair *kv_list, */ extern struct kv_pair *kv_pair_fmt(struct kv_pair *kv_list, const char *kv_key, const char *format, ...) +#if defined(_WIN32) || (_WIN64) + __attribute__((format(gnu_printf, 3, 4))); +#else __attribute__((format(printf, 3, 4))); +#endif /* * kv_pair_free - clean a key=value pair list

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coreboot-gerrit July 2015