coreboot-gerrit July 2015

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Patch set updated for coreboot: rk3288: Use timestamp region for pre-cbmem timestamps
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10740 -gerrit commit f283e2b00891ec532ce392f3e9d0a98c0d9f073d Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Nov 3 14:39:11 2014 -0800 rk3288: Use timestamp region for pre-cbmem timestamps BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 --- src/mainboard/google/veyron_brain/romstage.c | 14 +++----------- src/mainboard/google/veyron_danger/romstage.c | 14 +++----------- src/mainboard/google/veyron_jerry/romstage.c | 14 +++----------- src/mainboard/google/veyron_mickey/romstage.c | 14 +++----------- src/mainboard/google/veyron_mighty/romstage.c | 14 +++----------- src/mainboard/google/veyron_minnie/romstage.c | 14 +++----------- src/mainboard/google/veyron_pinky/romstage.c | 14 +++----------- src/mainboard/google/veyron_rialto/romstage.c | 14 +++----------- src/mainboard/google/veyron_romy/romstage.c | 14 +++----------- src/mainboard/google/veyron_speedy/romstage.c | 14 +++----------- src/soc/rockchip/rk3288/Kconfig | 1 + src/soc/rockchip/rk3288/bootblock.c | 3 +++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 + 13 files changed, 35 insertions(+), 110 deletions(-) diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 80d9081..0328e95 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -81,11 +81,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -98,11 +94,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -114,10 +110,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index e509a4a..06eabe0 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -86,11 +86,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -103,11 +99,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -119,10 +115,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index e509a4a..06eabe0 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -86,11 +86,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -103,11 +99,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -119,10 +115,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index b536391..5031ad9d 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -94,11 +94,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -111,11 +107,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -127,10 +123,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3a4712e..1800b16 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -24,6 +24,7 @@ config SOC_ROCKCHIP_RK3288 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 + select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAVE_UART_SPECIAL diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d60c860..6ba3230 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,9 +26,12 @@ #include <soc/grf.h> #include <soc/timer.h> #include <symbols.h> +#include <timestamp.h> void bootblock_soc_init(void) { + timestamp_early_init(timestamp_get()); + rkclk_init(); mmu_init(); diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index cd484c8..0b75932 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -41,6 +41,7 @@ SECTIONS OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 41K) TTB_SUBTABLES(0xFF716C00, 1K) PRERAM_CBFS_CACHE(0xFF717000, 1K) + TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) SRAM_END(0xFF718000)

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Patch set updated for coreboot: timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10742 -gerrit commit 1f746eb5836582bb1e17e96fb9f98152e8a1b13a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 6 09:58:07 2014 -0600 timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS so stop guarding the compilation. BUG=None BRANCH=None TEST=Built Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228190 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392 --- src/arch/x86/boot/acpi.c | 4 ---- src/mainboard/google/cosmos/romstage.c | 15 ++++----------- src/mainboard/google/veyron_brain/romstage.c | 11 +++-------- src/mainboard/google/veyron_danger/romstage.c | 11 +++-------- src/mainboard/google/veyron_jerry/romstage.c | 12 ++++-------- src/mainboard/google/veyron_mickey/romstage.c | 11 +++-------- src/mainboard/google/veyron_mighty/romstage.c | 11 +++-------- src/mainboard/google/veyron_minnie/romstage.c | 12 ++++-------- src/mainboard/google/veyron_pinky/romstage.c | 14 ++++++-------- src/mainboard/google/veyron_rialto/romstage.c | 11 +++-------- src/mainboard/google/veyron_romy/romstage.c | 11 +++-------- src/mainboard/google/veyron_speedy/romstage.c | 12 ++++-------- src/southbridge/intel/bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/i82801gx/bootblock.c | 3 +-- src/southbridge/intel/lynxpoint/bootblock.c | 3 +-- 16 files changed, 44 insertions(+), 103 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index cf33e40..134e437 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -34,9 +34,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> -#if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> -#endif #include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ @@ -1124,9 +1122,7 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_ACPI_WAKE_JUMP); -#endif acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index 0988bee..e5fa67e 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -37,37 +37,30 @@ void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); -#endif console_init(); -#if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); -#endif + sdram_init(); -#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); -#endif + mmu_init(); mmu_config_range(0, 4096, DCACHE_OFF); dcache_mmu_enable(); cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif - -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 0328e95..e9857b8 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -80,9 +80,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -93,13 +91,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,9 +106,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 06eabe0..fb6e631 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,8 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index 06eabe0..5ccbe3e 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 5031ad9d..492c0f0 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -93,9 +93,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -106,13 +104,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -122,9 +120,9 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif + run_ramstage(); } diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index ffdfdb0..9cdacc3 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 4df6bb5..18532df 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -86,9 +86,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 46aa58f..8f6ddbc 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 64c4410..dde1ae9 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -47,9 +47,8 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); /* Enable RCBA */ diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 6727173..8c2133b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc();

1 0

Patch set updated for coreboot: timestamp: Make timestamp library more flexible and intelligent
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10735 -gerrit commit 1f983cf63bf6f59de0bc9f9308c7b5707141b68d Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Oct 15 15:17:49 2014 -0700 timestamp: Make timestamp library more flexible and intelligent Add support for: 1) Using timestamps in bootblock and verstage 2) Allowing the timestamps to be stashed into _timestamp region so that they can be used across multiple stages 3) Performing operations over the timestamps in _timestamp region Instead of having two separate APIs for stashing and adding timestamps, let the timestamp library decide on its own where to save depending on timestamp cache status. Now the sequence of operations would be something like: timestamp_init / timestamp_early_init : Set the base time timestamp_add / timestamp_add_now cbmem_initialize : It internally calls timestamp_sync timestamp_add / timestamp_add_now BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully for ryu and samus. cbmem -t on ryu works fine. Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224024 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 2f6b472984f4971ece172b789aab3bc82afa8a9d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4d2ffc99277be6c248c8c70149dc14334a1f536a --- src/arch/x86/Makefile.inc | 3 +- src/arch/x86/init/romstage.ld | 5 + src/include/timestamp.h | 25 ++++ src/lib/timestamp.c | 263 +++++++++++++++++++++++++++++++----------- 4 files changed, 228 insertions(+), 68 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f502bbe..dcb9ff0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -225,7 +225,8 @@ $(objgenerated)/romstage_null.ld: $(obj)/config.h $$(filter %.ld,$$(romstage-src rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp printf '$(foreach ldscript,$(^),#include "$(ldscript)"\n)' >> $@.tmp - $(CC_romstage) $(PREPROCESS_ONLY) $@.tmp > $@ + $(CC_romstage) $(PREPROCESS_ONLY) $(CPPFLAGS_common) $@.tmp > $@ + $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt @printf " GEN $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 7b9cb6a..951ca65 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -52,6 +52,11 @@ SECTIONS . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_data_start = .; +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + _timestamp = .; + . = . + 0x100; + _etimestamp = .; +#endif *(.car.global_data); _car_data_end = .; /* The preram cbmem console area comes last to take advantage diff --git a/src/include/timestamp.h b/src/include/timestamp.h index a248ea4..0a13209 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -89,10 +89,35 @@ enum timestamp_id { }; #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) +/* + * Order of usage of timestamp library is: + * Call timestamp_early_init / timestamp_init to set base time before any + * timestamp_add function is called. timestamp_early_init also ensures that the + * cache is valid in _timestamp region. + * After this, timestamp_add / timestamp_add_now can be used to record + * timestamps. Sync will be automatically taken care of by cbmem_initialize. + */ +/* + * Initialize the cache to a valid state and set the base time. + * This function is used before DRAM is set up so that the timestamp cache can + * be initialized in _timestamp region. + * Both, timestamp_init and timestamp_early_init reset the cbmem state to + * "timestamp table reset required". Thus, whenever a timestamp_add or + * timestamp_sync is done to add new entries into the cbmem timestamp table, it + * first resets the table to 0 entries. + */ +void timestamp_early_init(uint64_t base); +/* Initialize the base time for timestamps and mark cache as valid. */ void timestamp_init(uint64_t base); +/* + * Add a new timestamp. Depending on cbmem is available or not, this timestamp + * will be stored to cbmem / timestamp cache. + */ void timestamp_add(enum timestamp_id id, uint64_t ts_time); +/* Calls timestamp_add with current timestamp. */ void timestamp_add_now(enum timestamp_id id); #else +#define timestamp_early_init(base) #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 0c41ea2..c845757 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -17,10 +17,12 @@ * Foundation, Inc. */ +#include <assert.h> #include <stddef.h> #include <stdint.h> #include <console/console.h> #include <cbmem.h> +#include <symbols.h> #include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> @@ -29,12 +31,68 @@ #define MAX_TIMESTAMPS 60 -static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL; -static uint64_t ts_basetime CAR_GLOBAL = 0; +#define MAX_TIMESTAMP_CACHE 16 -static void timestamp_stash(enum timestamp_id id, uint64_t ts_time); +struct __attribute__((__packed__)) timestamp_cache { + uint16_t cache_state; + uint16_t cbmem_state; + struct timestamp_table table; + struct timestamp_entry entries[MAX_TIMESTAMP_CACHE]; +}; -static void timestamp_real_init(uint64_t base) +#define USE_TIMESTAMP_REGION \ + (IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) && \ + defined(__PRE_RAM__)) + +#define USE_LOCAL_TIMESTAMP_CACHE (!defined(__PRE_RAM__)) + +#define HAS_CBMEM (ENV_ROMSTAGE || ENV_RAMSTAGE) + +#if USE_LOCAL_TIMESTAMP_CACHE +static struct timestamp_cache timestamp_cache __attribute__((unused)); +#endif + +enum { + TIMESTAMP_CACHE_UNINITIALIZED = 0, + TIMESTAMP_CACHE_INITIALIZED, + TIMESTAMP_CACHE_NOT_NEEDED, +}; + +enum { + TIMESTAMP_CBMEM_RESET_NOT_REQD = 0, + TIMESTAMP_CBMEM_RESET_REQD, +}; + +static void timestamp_cache_init(struct timestamp_cache *ts_cache, + uint64_t base, uint16_t cbmem_state) +{ + ts_cache->table.num_entries = 0; + ts_cache->table.max_entries = MAX_TIMESTAMP_CACHE; + ts_cache->table.base_time = base; + ts_cache->cache_state = TIMESTAMP_CACHE_INITIALIZED; + ts_cache->cbmem_state = cbmem_state; +} + +static struct timestamp_cache *timestamp_cache_get(void) +{ + struct timestamp_cache *ts_cache = NULL; + +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + if (_timestamp_size < sizeof(*ts_cache)) + BUG(); + ts_cache = car_get_var_ptr((void *)_timestamp); +#elif USE_LOCAL_TIMESTAMP_CACHE + ts_cache = &timestamp_cache; +#endif + + if (ts_cache && ts_cache->cache_state == TIMESTAMP_CACHE_UNINITIALIZED) + timestamp_cache_init(ts_cache, 0, + TIMESTAMP_CBMEM_RESET_NOT_REQD); + + return ts_cache; +} + +static struct timestamp_table *timestamp_alloc_cbmem_table(void) { struct timestamp_table* tst; @@ -43,13 +101,13 @@ static void timestamp_real_init(uint64_t base) MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); if (!tst) - return; + return NULL; - tst->base_time = base; + tst->base_time = 0; tst->max_entries = MAX_TIMESTAMPS; tst->num_entries = 0; - car_set_var(ts_table_p, tst); + return tst; } /* Determine if one should proceed into timestamp code. This is for protecting @@ -66,23 +124,16 @@ static int timestamp_should_run(void) void timestamp_add(enum timestamp_id id, uint64_t ts_time) { - struct timestamp_entry *tse; - struct timestamp_table *ts_table = NULL; + struct timestamp_table *ts_table; - if (!timestamp_should_run()) - return; + ts_table = timestamp_table_get(); - ts_table = car_get_var(ts_table_p); if (!ts_table) { - timestamp_stash(id, ts_time); + printk(BIOS_ERR, "ERROR: No timestamp table found\n"); return; } - if (ts_table->num_entries == ts_table->max_entries) - return; - tse = &ts_table->entries[ts_table->num_entries++]; - tse->entry_id = id; - tse->entry_stamp = ts_time - ts_table->base_time; + timestamp_add_table_entry(ts_table, id, ts_time); } void timestamp_add_now(enum timestamp_id id) @@ -90,86 +141,164 @@ void timestamp_add_now(enum timestamp_id id) timestamp_add(id, timestamp_get()); } -#define MAX_TIMESTAMP_CACHE 8 -struct timestamp_cache { - enum timestamp_id id; - uint64_t time; -} timestamp_cache[MAX_TIMESTAMP_CACHE] CAR_GLOBAL; +static struct timestamp_table *timestamp_table_get(void) +{ + MAYBE_STATIC struct timestamp_table *ts_table = NULL; + struct timestamp_cache *ts_cache; -static int timestamp_entries CAR_GLOBAL = 0; + if (!timestamp_should_run()) + return NULL; -/** - * timestamp_stash() allows to temporarily cache timestamps. - * This is needed when timestamping before the CBMEM area - * is initialized. The function timestamp_do_sync() is used to - * write the timestamps to the CBMEM area and this is done as - * part of CAR migration for romstage, and in ramstage main(). - */ + ts_cache = timestamp_cache_get(); + + if (ts_cache == NULL) { +#if HAS_CBMEM + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + return ts_table; + } + + if (ts_cache->cache_state != TIMESTAMP_CACHE_NOT_NEEDED) + return &ts_cache->table; + +#if HAS_CBMEM + if (ts_cache->cbmem_state == TIMESTAMP_CBMEM_RESET_REQD) { + ts_table = timestamp_alloc_cbmem_table(); + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_NOT_REQD; + } + + if (!ts_table) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + + return ts_table; +} -static void timestamp_stash(enum timestamp_id id, uint64_t ts_time) +static void timestamp_add_table_entry(struct timestamp_table *ts_table, + enum timestamp_id id, uint64_t ts_time) { - struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); - int ts_entries = car_get_var(timestamp_entries); + struct timestamp_entry *tse; - if (ts_entries >= MAX_TIMESTAMP_CACHE) { - printk(BIOS_ERR, "ERROR: failed to add timestamp to cache\n"); + if (ts_table->num_entries == ts_table->max_entries) { + printk(BIOS_ERR, "ERROR: Timestamp table full\n"); return; } - ts_cache[ts_entries].id = id; - ts_cache[ts_entries].time = ts_time; - car_set_var(timestamp_entries, ++ts_entries); + + tse = &ts_table->entries[ts_table->num_entries++]; + tse->entry_id = id; + tse->entry_stamp = ts_time - ts_table->base_time; +} + +void timestamp_early_init(uint64_t base) +{ + struct timestamp_cache *ts_cache; + ts_cache = timestamp_cache_get(); + if (ts_cache == NULL) + BUG(); + timestamp_cache_init(ts_cache, base, TIMESTAMP_CBMEM_RESET_REQD); } static void timestamp_do_sync(void) { - struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); - int ts_entries = car_get_var(timestamp_entries); + uint32_t i; + + struct timestamp_cache *ts_cache; + struct timestamp_table *ts_cache_table; + struct timestamp_table *ts_cbmem_table = NULL; + + ts_cache = timestamp_cache_get(); + + /* No timestamp cache found */ + if (ts_cache == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp cache found\n"); + return; + } + + ts_cache_table = &ts_cache->table; + + ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); + + if ((ts_cache->cbmem_state == TIMESTAMP_CBMEM_RESET_REQD) || + (ts_cbmem_table == NULL)) + ts_cbmem_table = timestamp_alloc_cbmem_table(); + + if (ts_cbmem_table == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + return; + } - int i; - for (i = 0; i < ts_entries; i++) - timestamp_add(ts_cache[i].id, ts_cache[i].time); - car_set_var(timestamp_entries, 0); + if (ts_cbmem_table == ts_cache_table) { + printk(BIOS_ERR, "ERROR: Table error to sync timestamps\n"); + return; + } + + if (ts_cache->cache_state == TIMESTAMP_CACHE_NOT_NEEDED) { + printk(BIOS_INFO, "Timestamp cache already synced\n"); + return; + } + + ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED; + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_NOT_REQD; + + /* + * There can be two cases for timestamp sync: + * 1. Newly added cbmem_table will have base_time of 0. Thus, no + * adjusments are needed for the timestamps being added from cache to + * cbmem table. + * 2. Timestamps added to cache before ramstage: In this case, the + * base_time in cache table would be 0 and add_table_entry will take + * care of subtracting the appropriate base_time. + */ + for (i = 0; i < ts_cache_table->num_entries; i++) { + struct timestamp_entry *tse = &ts_cache_table->entries[i]; + timestamp_add_table_entry(ts_cbmem_table, tse->entry_id, + tse->entry_stamp); + } + + ts_cache_table->num_entries = 0; + /* Freshly added cbmem table has base_time 0. Inherit cache base_time */ + if (ts_cbmem_table->base_time == 0) + ts_cbmem_table->base_time = ts_cache_table->base_time; } void timestamp_init(uint64_t base) { + struct timestamp_cache *ts_cache; + struct timestamp_table *tst; + if (!timestamp_should_run()) return; -#ifdef __PRE_RAM__ - /* Copy of basetime, it is too early for CBMEM. */ - car_set_var(ts_basetime, base); -#else - struct timestamp_table *tst = NULL; + ts_cache = timestamp_cache_get(); - /* Locate and use an already existing table. */ - if (!IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) - tst = cbmem_find(CBMEM_ID_TIMESTAMP); + if (!ts_cache) { + printk(BIOS_ERR, "ERROR: No timestamp cache to init\n"); + return; + } - if (tst) { - car_set_var(ts_table_p, tst); + /* the table is already used, so we shouldn't reset its base */ + if (ts_cache->cache_state == TIMESTAMP_CACHE_NOT_NEEDED) + return; + + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_REQD; + + tst = timestamp_table_get(); + + if (!tst) { + printk(BIOS_ERR, "ERROR: No timestamp table to init\n"); return; } - /* Copy of basetime, may be too early for CBMEM. */ - car_set_var(ts_basetime, base); - timestamp_real_init(base); -#endif + tst->base_time = base; } +/* moves timestamp data from cache to cbmem region */ static void timestamp_reinit(int is_recovery) { if (!timestamp_should_run()) return; -#ifdef __PRE_RAM__ - timestamp_real_init(car_get_var(ts_basetime)); -#else - if (!car_get_var(ts_table_p)) - timestamp_init(car_get_var(ts_basetime)); -#endif - if (car_get_var(ts_table_p)) - timestamp_do_sync(); + timestamp_do_sync(); } /* Call timestamp_reinit CBMEM init hooks. */

1 0

New patch to review for coreboot: veyron*: Kill SKIP_DISPLAY_INIT_HACK
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10785 -gerrit commit 7d449b2d8e50f2446c813f2ca3e632679f4a54b2 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 25 17:10:00 2015 -0700 veyron*: Kill SKIP_DISPLAY_INIT_HACK Now that we have functioning display code for all platforms, we can just get rid of this ugly hack used on non-Chromebook veyrons. BUG=none BRANCH=none TEST=built for Brain, Rialto, Mickey, Romy Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5 Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282049 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_brain/Kconfig | 8 -------- src/mainboard/google/veyron_brain/mainboard.c | 5 +++++ src/mainboard/google/veyron_romy/Kconfig | 8 -------- src/mainboard/google/veyron_romy/mainboard.c | 5 +++++ src/soc/rockchip/rk3288/soc.c | 2 -- 5 files changed, 10 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index 2391660..ca5d0fc 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -64,14 +64,6 @@ config CONSOLE_SERIAL_UART_ADDRESS depends on DRIVERS_UART default 0xFF690000 -# FIXME(dhendrix): This is a gross hack intended to get us past -# display init which currently hangs the machine. It will be removed -# once we've re-factored the display init code to properly handle -# various types of displays. -config SKIP_DISPLAY_INIT_HACK - int - default 1 - config PMIC_BUS int default 0 diff --git a/src/mainboard/google/veyron_brain/mainboard.c b/src/mainboard/google/veyron_brain/mainboard.c index 29f66e3..c54e96f 100644 --- a/src/mainboard/google/veyron_brain/mainboard.c +++ b/src/mainboard/google/veyron_brain/mainboard.c @@ -126,3 +126,8 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = _dma_coherent_size; } + +void mainboard_power_on_backlight(void) +{ + return; +} diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index 4734520..c15e29f 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -64,14 +64,6 @@ config CONSOLE_SERIAL_UART_ADDRESS depends on DRIVERS_UART default 0xFF690000 -# FIXME(dhendrix): This is a gross hack intended to get us past -# display init which currently hangs the machine. It will be removed -# once we've re-factored the display init code to properly handle -# various types of displays. -config SKIP_DISPLAY_INIT_HACK - int - default 1 - config PMIC_BUS int default 0 diff --git a/src/mainboard/google/veyron_romy/mainboard.c b/src/mainboard/google/veyron_romy/mainboard.c index 2f61d01..3c7da54 100644 --- a/src/mainboard/google/veyron_romy/mainboard.c +++ b/src/mainboard/google/veyron_romy/mainboard.c @@ -115,3 +115,8 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = _dma_coherent_size; } + +void mainboard_power_on_backlight(void) +{ + return; +} diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 6cdcc51..a13086a 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -39,11 +39,9 @@ static void soc_init(device_t dev) ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB)); if (vboot_skip_display_init()) printk(BIOS_INFO, "Skipping display init.\n"); -#if !IS_ENABLED(CONFIG_SKIP_DISPLAY_INIT_HACK) else rk_display_init(dev, (uintptr_t)_framebuffer, _framebuffer_size); -#endif } static struct device_operations soc_ops = {

1 0

New patch to review for coreboot: veyron_rialto: Use VOP_MODE_NONE for display init.
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10784 -gerrit commit b6feb15e5a23f6f08f06951f6973eaac071a721c Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 25 18:03:12 2015 -0700 veyron_rialto: Use VOP_MODE_NONE for display init. This uses VOP_MODE_NONE for display init on veyron_rialto and adds a mainboard_power_on_backlight() stub so that we can finally get rid of SKIP_DISPLAY_INIT_HACK. BUG=none BRANCH=none TEST=built for veyron_rialto Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282048 --- src/mainboard/google/veyron_rialto/Kconfig | 8 -------- src/mainboard/google/veyron_rialto/devicetree.cb | 1 + src/mainboard/google/veyron_rialto/mainboard.c | 1 + 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 30c54f6..1886db9 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -63,14 +63,6 @@ config CONSOLE_SERIAL_UART_ADDRESS depends on DRIVERS_UART default 0xFF690000 -# FIXME(dhendrix): This is a gross hack intended to get us past -# display init which currently hangs the machine. It will be removed -# once we've re-factored the display init code to properly handle -# various types of displays. -config SKIP_DISPLAY_INIT_HACK - int - default 1 - config PMIC_BUS int default 0 diff --git a/src/mainboard/google/veyron_rialto/devicetree.cb b/src/mainboard/google/veyron_rialto/devicetree.cb index 4c2ea8f..c40bbbb 100644 --- a/src/mainboard/google/veyron_rialto/devicetree.cb +++ b/src/mainboard/google/veyron_rialto/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_NONE" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 6e3e51b..52a27bb 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -108,4 +108,5 @@ void lb_board(struct lb_header *header) void mainboard_power_on_backlight(void) { + return; }

1 0

New patch to review for coreboot: cbfs: define libpayload_init_default_cbfs_media weakly
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10783 -gerrit commit 5ab6e7f4ac35bb15333ff85e8fa1a9bfe0775b2a Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Jul 1 10:31:49 2015 -0700 cbfs: define libpayload_init_default_cbfs_media weakly To allow a payload to define its own libpayload_init_default_cbfs_media, default implementation needs to be defined weakly. BUG=none BRANCH=tot TEST=dumped a cbfs file from depthcharge cli on jerry Change-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352 Original-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283061 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm/dummy_media.c | 3 ++- payloads/libpayload/arch/arm64/dummy_media.c | 3 ++- payloads/libpayload/arch/mips/dummy_media.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/arch/arm/dummy_media.c b/payloads/libpayload/arch/arm/dummy_media.c index 7926976..c67344f 100644 --- a/payloads/libpayload/arch/arm/dummy_media.c +++ b/payloads/libpayload/arch/arm/dummy_media.c @@ -36,7 +36,8 @@ int libpayload_init_default_cbfs_media(struct cbfs_media *media); -int libpayload_init_default_cbfs_media(struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media( + struct cbfs_media *media) { return -1; } diff --git a/payloads/libpayload/arch/arm64/dummy_media.c b/payloads/libpayload/arch/arm64/dummy_media.c index 7926976..c67344f 100644 --- a/payloads/libpayload/arch/arm64/dummy_media.c +++ b/payloads/libpayload/arch/arm64/dummy_media.c @@ -36,7 +36,8 @@ int libpayload_init_default_cbfs_media(struct cbfs_media *media); -int libpayload_init_default_cbfs_media(struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media( + struct cbfs_media *media) { return -1; } diff --git a/payloads/libpayload/arch/mips/dummy_media.c b/payloads/libpayload/arch/mips/dummy_media.c index 539773d..112d7fe 100644 --- a/payloads/libpayload/arch/mips/dummy_media.c +++ b/payloads/libpayload/arch/mips/dummy_media.c @@ -35,7 +35,8 @@ int libpayload_init_default_cbfs_media(struct cbfs_media *media); -int libpayload_init_default_cbfs_media(struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media( + struct cbfs_media *media) { return -1; }

1 0

New patch to review for coreboot: sysinfo: remove unused tag for struct spi_flash
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10782 -gerrit commit 9a2803841a706c9af065aae1ef012fbdba4a27b0 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jun 29 14:06:17 2015 -0700 sysinfo: remove unused tag for struct spi_flash This will conflict with struct spi_flash defined in spi_flash.h BUG=none BRANCH=tot TEST=built libpayload for veyron jerry Change-Id: I7e1be28cf430021944fc96890082a0704d093e9f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0f0b8a7ec114046335fb1a51b6a92e10e5a16520 Original-Change-Id: I6d4f8a8e93aeb055f7dd6e5e8fd5e6c6153ab837 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282588 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> --- payloads/libpayload/include/sysinfo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 5b58f55..c407c3d 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -119,7 +119,7 @@ struct sysinfo_t { void *wifi_calibration; uint64_t ramoops_buffer; uint32_t ramoops_buffer_size; - struct spi_flash { + struct { uint32_t size; uint32_t sector_size; uint32_t erase_cmd;

1 0

New patch to review for coreboot: update common base header files
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10781 -gerrit commit df33dbb7251f7808c123793ef1d7429a9eb05257 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jun 29 13:33:34 2015 -0700 update common base header files IS_ENABLED is defined in kconfig.h, thus, should be included in libpayload.h. BUG=none BRANCH=tot TEST=built coreboot/libpayload for veyron_jerry Change-Id: I9c5879b6125ac66a75a507ab07a6816ab54ed0ba Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 51dcd58a841009081fdefcadf9aa74286152dde6 Original-Change-Id: I30e6d87c9de827a214a6100449cd716e773c2ba3 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282587 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> --- payloads/libpayload/include/libpayload.h | 1 + payloads/libpayload/include/stddef.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 3e24071..c09fc17 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -48,6 +48,7 @@ #include <die.h> #include <endian.h> #include <ipchksum.h> +#include <kconfig.h> #include <stddef.h> #include <stdio.h> #include <stdarg.h> diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index bb2971d..fe455b8 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -16,7 +16,15 @@ typedef __SIZE_TYPE__ ssize_t; #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *) 0)->MEMBER) #define member_size(TYPE, MEMBER) (sizeof(((TYPE *) 0)->MEMBER)) +#define check_member(structure, member, offset) _Static_assert( \ + offsetof(struct structure, member) == offset, \ + "`struct " #structure "` offset for `" #member "` is not " #offset) + /* Standard units. */ #define KiB (1<<10) #define MiB (1<<20) #define GiB (1<<30) + +#define KHz (1000) +#define MHz (1000*KHz) +#define GHz (1000*MHz)

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New patch to review for coreboot: t210: MTC cleanup
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10780 -gerrit commit 4838e367d7019b9e6fe2acb3257ce2260fdc1238 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 16 13:02:40 2015 -0700 t210: MTC cleanup 1. Correct MTC weak function definitions. 2. Correct MTC message in case no training data is present. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug. Change-Id: Iba3c994982da947af3fbd2d7e9a06dff7947f2b9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce9a4cd7d824acd0da5615b33319869f6cf1cd56 Original-Change-Id: I037439246709c8ec0ec7f12ea109cbe0ae1073ae Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/278027 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/include/soc/mtc.h | 2 +- src/soc/nvidia/tegra210/soc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h index c94d79b..c9f19cb 100644 --- a/src/soc/nvidia/tegra210/include/soc/mtc.h +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -29,7 +29,7 @@ void soc_add_mtc(struct lb_header *header); #else -static inline int tegra210_run_mtc(void) { return -1; } +static inline int tegra210_run_mtc(void) { return 0; } static inline void soc_add_mtc(struct lb_header *header) {} #endif /* CONFIG_HAVE_MTC */ diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index f3290c3..7d91bc5 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -156,7 +156,7 @@ static void tegra210_cpu_init(device_t cpu) { if (cpu_is_bsp()) if (tegra210_run_mtc() != 0) - printk(BIOS_ERR, "MTC: Training failed\n"); + printk(BIOS_ERR, "MTC: No training data.\n"); } static const struct cpu_device_id ids[] = {

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New patch to review for coreboot: rk3288: Add VOP_MODE_NONE for headless devices
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10779 -gerrit commit 78fce742c15d797c503df2a6762ab37f55e98967 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 25 18:00:37 2015 -0700 rk3288: Add VOP_MODE_NONE for headless devices BUG=none BRANCH=none TEST=built w/ follow-up rialto patch Change-Id: I166c75673c199e8c6860f601db6759cdc3cb9c96 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ba0e0b639f12654ec54216d4366c688baa5b3253 Original-Change-Id: Id21c87ace2f4d381a1e374e1d5fe15cf1cd96da0 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282047 --- src/soc/rockchip/rk3288/display.c | 2 ++ src/soc/rockchip/rk3288/include/soc/vop.h | 1 + 2 files changed, 3 insertions(+) diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index ab297a2..d241e3e 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -54,6 +54,8 @@ void rk_display_init(device_t dev, u32 lcdbase, mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); switch (conf->vop_mode) { + case VOP_MODE_NONE: + return; case VOP_MODE_AUTO_DETECT: /* try EDP first, then HDMI */ case VOP_MODE_EDP: diff --git a/src/soc/rockchip/rk3288/include/soc/vop.h b/src/soc/rockchip/rk3288/include/soc/vop.h index 2690726..6df4c60 100644 --- a/src/soc/rockchip/rk3288/include/soc/vop.h +++ b/src/soc/rockchip/rk3288/include/soc/vop.h @@ -107,6 +107,7 @@ enum vop_modes { */ VOP_MODE_EDP = 0, VOP_MODE_HDMI, + VOP_MODE_NONE, VOP_MODE_AUTO_DETECT, VOP_MODE_UNKNOWN, };

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coreboot-gerrit July 2015