coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: veyron_brain: Add basic HDMI support
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10778 -gerrit commit 125db64cf564754cdfff08ac0fd23f596ba22e43 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 25 16:59:02 2015 -0700 veyron_brain: Add basic HDMI support This adds a configure_hdmi() function that drives the HDMI enable output high and configures the iomux. Calls to PMIC functions to enable HDMI power are moved here as well. BUG=none BRANCH=none TEST=with follow-up patches, we now get a dev screen on Brain. Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013 Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282046 --- src/mainboard/google/veyron_brain/devicetree.cb | 1 + src/mainboard/google/veyron_brain/mainboard.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/google/veyron_brain/devicetree.cb b/src/mainboard/google/veyron_brain/devicetree.cb index 4c2ea8f..3ed746c 100644 --- a/src/mainboard/google/veyron_brain/devicetree.cb +++ b/src/mainboard/google/veyron_brain/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_HDMI" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_brain/mainboard.c b/src/mainboard/google/veyron_brain/mainboard.c index a5c40c23..29f66e3 100644 --- a/src/mainboard/google/veyron_brain/mainboard.c +++ b/src/mainboard/google/veyron_brain/mainboard.c @@ -76,10 +76,20 @@ static void configure_vop(void) /* lcdc(vop) iodomain select 1.8V */ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0)); +} +static void configure_hdmi(void) +{ rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */ rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */ rk808_configure_switch(1, 1); /* VCC33_LCD */ + + /* set POWER_HDMI_ON */ + gpio_output(GPIO(7, A, 2), 1); + + /* HDMI I2C */ + write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA); + write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL); } static void mainboard_init(device_t dev) @@ -90,6 +100,7 @@ static void mainboard_init(device_t dev) configure_emmc(); configure_codec(); configure_vop(); + configure_hdmi(); elog_init(); elog_add_watchdog_reset();

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New patch to review for coreboot: lzma: Return correct amount of decompressed bytes
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10777 -gerrit commit 094fd5dc30161556439a1fa4174284f43852f959 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jun 25 23:22:36 2015 -0700 lzma: Return correct amount of decompressed bytes The LZMA functions are supposed to return the decompressed size, but what they actually return is just an unaltered field from the LZMA header that is *supposed* to contain the decompressed size. Apparently some encoders just overshoot that for no good reason. This patch changes the code such that the actual amount of decompressed bytes is returned. BRANCH=smaug BUG=None TEST=Printed output bytes when decompressing kernels with LZMA in depthcharge, noted that amounts now make sense. Change-Id: Icdd8f782aa87841f770eff4c14a08973530c7446 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 24b2fa8c9a342ca4288dad1430c8965395f00263 Original-Change-Id: Ib4cf8673846aedd34656e594ce7b8ea875b56099 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282742 Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/liblzma/lzma.c | 2 +- src/lib/lzma.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/liblzma/lzma.c b/payloads/libpayload/liblzma/lzma.c index 23c9562..767eb86 100644 --- a/payloads/libpayload/liblzma/lzma.c +++ b/payloads/libpayload/liblzma/lzma.c @@ -48,7 +48,7 @@ unsigned long ulzman(const unsigned char *src, unsigned long srcn, printf("lzma: Decoding error = %d\n", res); return 0; } - return outSize; + return outProcessed; } unsigned long ulzma(const unsigned char *src, unsigned char *dst) diff --git a/src/lib/lzma.c b/src/lib/lzma.c index 89e4d97..c04f4a4 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -54,5 +54,5 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst) return 0; } timestamp_add_now(TS_END_ULZMA); - return outSize; + return outProcessed; }

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New patch to review for coreboot: veyron_*: Set vop_mode in devicetree.cb files
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10776 -gerrit commit fe4e1997fc47a6c205e1223ffffbf6ac1a1a81e3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jun 29 14:27:23 2015 -0700 veyron_*: Set vop_mode in devicetree.cb files This avoids any ambiguity or breakage in case the vop_modes get shuffled around or changed in some future patch or copy+paste job. Brain and Rialto need some more work done so their devicetree.cb files will be updated in follow-up patches. BUG=none BRANCH=none TEST=compiled only (for danger, jerry, mickey, romy, speedy) Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282610 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_danger/devicetree.cb | 1 + src/mainboard/google/veyron_jerry/devicetree.cb | 1 + src/mainboard/google/veyron_mickey/devicetree.cb | 2 +- src/mainboard/google/veyron_mighty/devicetree.cb | 1 + src/mainboard/google/veyron_minnie/devicetree.cb | 1 + src/mainboard/google/veyron_pinky/devicetree.cb | 1 + src/mainboard/google/veyron_romy/devicetree.cb | 1 + src/mainboard/google/veyron_shark/devicetree.cb | 1 + src/mainboard/google/veyron_speedy/devicetree.cb | 1 + 9 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_danger/devicetree.cb b/src/mainboard/google/veyron_danger/devicetree.cb index 4c2ea8f..64f1779 100644 --- a/src/mainboard/google/veyron_danger/devicetree.cb +++ b/src/mainboard/google/veyron_danger/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_AUTO_DETECT" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_jerry/devicetree.cb b/src/mainboard/google/veyron_jerry/devicetree.cb index 4c2ea8f..b958e26 100644 --- a/src/mainboard/google/veyron_jerry/devicetree.cb +++ b/src/mainboard/google/veyron_jerry/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_mickey/devicetree.cb b/src/mainboard/google/veyron_mickey/devicetree.cb index 6d0555a..3ed746c 100644 --- a/src/mainboard/google/veyron_mickey/devicetree.cb +++ b/src/mainboard/google/veyron_mickey/devicetree.cb @@ -21,6 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_HDMI" register "framebuffer_bits_per_pixel" = "16" - register "vop_mode" = "1" end diff --git a/src/mainboard/google/veyron_mighty/devicetree.cb b/src/mainboard/google/veyron_mighty/devicetree.cb index 4c2ea8f..b958e26 100644 --- a/src/mainboard/google/veyron_mighty/devicetree.cb +++ b/src/mainboard/google/veyron_mighty/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_minnie/devicetree.cb b/src/mainboard/google/veyron_minnie/devicetree.cb index 4c2ea8f..b958e26 100644 --- a/src/mainboard/google/veyron_minnie/devicetree.cb +++ b/src/mainboard/google/veyron_minnie/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_pinky/devicetree.cb b/src/mainboard/google/veyron_pinky/devicetree.cb index 4c2ea8f..b958e26 100644 --- a/src/mainboard/google/veyron_pinky/devicetree.cb +++ b/src/mainboard/google/veyron_pinky/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_romy/devicetree.cb b/src/mainboard/google/veyron_romy/devicetree.cb index 4c2ea8f..64f1779 100644 --- a/src/mainboard/google/veyron_romy/devicetree.cb +++ b/src/mainboard/google/veyron_romy/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_AUTO_DETECT" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_shark/devicetree.cb b/src/mainboard/google/veyron_shark/devicetree.cb index 4c2ea8f..b958e26 100644 --- a/src/mainboard/google/veyron_shark/devicetree.cb +++ b/src/mainboard/google/veyron_shark/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/veyron_speedy/devicetree.cb b/src/mainboard/google/veyron_speedy/devicetree.cb index 4c2ea8f..b958e26 100644 --- a/src/mainboard/google/veyron_speedy/devicetree.cb +++ b/src/mainboard/google/veyron_speedy/devicetree.cb @@ -21,5 +21,6 @@ chip soc/rockchip/rk3288 device cpu_cluster 0 on end register "vop_id" = "1" + register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "16" end

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New patch to review for coreboot: rk3288: Auto-detect display.
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10775 -gerrit commit fe8eb57b3e1561e8c86d476c27327e2e46d32e25 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jun 17 13:47:28 2015 -0700 rk3288: Auto-detect display. We currently select either HDMI or EDP (default). This patch allows us to use HDMI as a fallback for devices that may have a display connected on either interface. It also renames the enums to sound a little more sensible in other contexts (more on that in the follow-up patches). VOP_MODE_AUTO is added to the mode enum which will make it explicit that a board can support either. In AUTO_MODE we will try EDP first and then fallback to HDMI. Other modes can be set to force a certain behavior such as HDMI-only on Mickey where it doesn't make sense to try EDP. A follow-up patch will add logic for when we explicitly don't want to probe for any display (headless devices). BUG=none BRANCH=none TEST=On veyron_danger, connected EDP and HDMI displays and saw dev mode screen appear on EDP display. Unplugged EDP and then dev mode screen showed up on HDMI. Change-Id: I22b38031c4ab3d79fbb182f7a906da1197f35543 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3f57ed3758c4e516d9fd226ad9499b102b81b423 Original-Change-Id: I352dcde16f7f3ebbf5796852b685685e541eb794 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281076 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/chip.h | 1 + src/soc/rockchip/rk3288/display.c | 54 ++++++++++++++++++++----------- src/soc/rockchip/rk3288/include/soc/vop.h | 12 +++++-- src/soc/rockchip/rk3288/vop.c | 4 +-- 4 files changed, 47 insertions(+), 24 deletions(-) diff --git a/src/soc/rockchip/rk3288/chip.h b/src/soc/rockchip/rk3288/chip.h index 3a6b14d..2c4390a 100644 --- a/src/soc/rockchip/rk3288/chip.h +++ b/src/soc/rockchip/rk3288/chip.h @@ -21,6 +21,7 @@ #define __SOC_ROCKCHIP_RK3288_CHIP_H__ #include <soc/gpio.h> +#include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */ struct soc_rockchip_rk3288_config { u32 vop_id; diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 192580b..ab297a2 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -46,6 +46,7 @@ void rk_display_init(device_t dev, u32 lcdbase, struct soc_rockchip_rk3288_config *conf = dev->chip_info; uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + enum vop_modes detected_mode = VOP_MODE_UNKNOWN; printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ @@ -53,26 +54,41 @@ void rk_display_init(device_t dev, u32 lcdbase, mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); switch (conf->vop_mode) { - case HDMI_MODE: + case VOP_MODE_AUTO_DETECT: + /* try EDP first, then HDMI */ + case VOP_MODE_EDP: + printk(BIOS_DEBUG, "Attempting to setup EDP display.\n"); + rkclk_configure_edp(); + rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); + rk_edp_init(conf->vop_id); + + if (rk_edp_get_edid(&edid) == 0) { + detected_mode = VOP_MODE_EDP; + break; + } else { + printk(BIOS_WARNING, "Cannot get EDID from EDP.\n"); + if (conf->vop_mode == VOP_MODE_EDP) + return; + } + /* fall thru */ + case VOP_MODE_HDMI: + printk(BIOS_DEBUG, "Attempting to setup HDMI display.\n"); rkclk_configure_hdmi(); rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz); rk_hdmi_init(conf->vop_id); - if (rk_hdmi_get_edid(&edid)) { - printk(BIOS_WARNING, "can not get edid\n"); - return; - } - break; - case EDP_MODE: - default: - rkclk_configure_edp(); - rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); - rk_edp_init(conf->vop_id); - if (rk_edp_get_edid(&edid)) { - printk(BIOS_WARNING, "can not get edid\n"); - return; + if (rk_hdmi_get_edid(&edid) == 0) { + detected_mode = VOP_MODE_HDMI; + break; + } else { + printk(BIOS_WARNING, "Cannot get EDID from HDMI.\n"); + if (conf->vop_mode == VOP_MODE_HDMI) + return; } - break; + /* fall thru */ + default: + printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n"); + return; } if (rkclk_configure_vop_dclk(conf->vop_id, edid.pixel_clock * KHz)) { @@ -84,12 +100,12 @@ void rk_display_init(device_t dev, u32 lcdbase, edid.bytes_per_line = edid.ha * conf->framebuffer_bits_per_pixel / 8; edid.x_resolution = edid.ha; edid.y_resolution = edid.va; - rkvop_mode_set(conf->vop_id, &edid, conf->vop_mode); + rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid); - switch (conf->vop_mode) { - case HDMI_MODE: + switch (detected_mode) { + case VOP_MODE_HDMI: if (rk_hdmi_enable(&edid)) { printk(BIOS_WARNING, "hdmi enable err\n"); return; @@ -103,7 +119,7 @@ void rk_display_init(device_t dev, u32 lcdbase, mdelay(2000); break; - case EDP_MODE: + case VOP_MODE_EDP: default: if (rk_edp_enable()) { printk(BIOS_WARNING, "edp enable err\n"); diff --git a/src/soc/rockchip/rk3288/include/soc/vop.h b/src/soc/rockchip/rk3288/include/soc/vop.h index 6cb883a..2690726 100644 --- a/src/soc/rockchip/rk3288/include/soc/vop.h +++ b/src/soc/rockchip/rk3288/include/soc/vop.h @@ -100,9 +100,15 @@ enum { LB_RGB_1280X8 = 0x5 }; -enum { - EDP_MODE, - HDMI_MODE, +enum vop_modes { + /* EDP == 0 is used for early RK3288 products and is the most likely + * use case, so keep it as the default. Other desired modes should + * be set explicitly in the board's devicetree.cb. + */ + VOP_MODE_EDP = 0, + VOP_MODE_HDMI, + VOP_MODE_AUTO_DETECT, + VOP_MODE_UNKNOWN, }; /* VOP_VERSION_INFO */ diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c index 03338e8..8c69321 100644 --- a/src/soc/rockchip/rk3288/vop.c +++ b/src/soc/rockchip/rk3288/vop.c @@ -110,12 +110,12 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) switch (mode) { - case HDMI_MODE: + case VOP_MODE_HDMI: clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); break; - case EDP_MODE: + case VOP_MODE_EDP: default: clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1));

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New patch to review for coreboot: libpayload: usb: dwc2: support interrupt transfer
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10774 -gerrit commit fa5b8735ccbad2a3f4d028c4aa40b26861a515f7 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Fri Jun 19 17:09:04 2015 +0800 libpayload: usb: dwc2: support interrupt transfer dwc2 host core do not have a periodic schedule list, so try to send an interrupt packet in poll_intr_queue() function and use frame number read from usb core register to calculate time and schedule transfers. BUG=None TEST=Tested on RK3288 with two USB keyboards(connect to SoC without USB hub), both work correctly. BRANCH=None Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157 Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280750 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> --- payloads/libpayload/drivers/usb/dwc2.c | 117 +++++++++++++++++++++-- payloads/libpayload/drivers/usb/dwc2_private.h | 11 ++- payloads/libpayload/include/usb/dwc2_registers.h | 23 ++++- 3 files changed, 139 insertions(+), 12 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index faf1f46..fa0fd34 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -37,7 +37,8 @@ static void dwc2_reinit(hci_t *controller) grxfsiz_t grxfsiz = { .d32 = 0 }; ghwcfg3_t hwcfg3 = { .d32 = 0 }; hcintmsk_t hcintmsk = { .d32 = 0 }; - gnptxfsiz_t gnptxfsiz = { .d32 = 0 }; + gtxfsiz_t gnptxfsiz = { .d32 = 0 }; + gtxfsiz_t hptxfsiz = { .d32 = 0 }; const int timeout = 10000; int i, fifo_blocks, tx_blocks; @@ -97,15 +98,19 @@ static void dwc2_reinit(hci_t *controller) * Reserve 2 spaces for the status entries of received packets * and 2 spaces for bulk and control OUT endpoints. Calculate how * many blocks can be alloted, assume largest packet size is 512. + * 16 locations reserved for periodic TX . */ - fifo_blocks = (hwcfg3.dfifodepth - 4) / (512 / 4); + fifo_blocks = (hwcfg3.dfifodepth - 4 - 16) / (512 / 4); tx_blocks = fifo_blocks / 2; grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4; writel(grxfsiz.d32, &reg->core.grxfsiz); - gnptxfsiz.nptxfstaddr = grxfsiz.rxfdep; - gnptxfsiz.nptxfdep = tx_blocks * (512 / 4); + gnptxfsiz.txfstaddr = grxfsiz.rxfdep; + gnptxfsiz.txfdep = tx_blocks * (512 / 4); writel(gnptxfsiz.d32, &reg->core.gnptxfsiz); + hptxfsiz.txfstaddr = gnptxfsiz.txfstaddr + gnptxfsiz.txfdep; + hptxfsiz.txfdep = 16; + writel(hptxfsiz.d32, &reg->core.hptxfsiz); /* Init host channels */ hcintmsk.xfercomp = 1; @@ -159,9 +164,10 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) if (hcint.chhltd) { writel(hcint.d32, &reg->host.hchn[ch_num].hcintn); - if (hcint.xfercomp) return hctsiz.xfersize; + else if (hcint.nak || hcint.frmovrun) + return hctsiz.xfersize; else if (hcint.xacterr) return -HCSTAT_XFERERR; else if (hcint.bblerr) @@ -327,6 +333,101 @@ dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, return ret; } +static int +dwc2_intr(endpoint_t *ep, int size, u8 *src) +{ + ep_dir_t data_dir; + + if (ep->direction == IN) + data_dir = EPDIR_IN; + else if (ep->direction == OUT) + data_dir = EPDIR_OUT; + else + return -1; + + return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src); +} + +static u32 dwc2_intr_get_timestamp(intr_queue_t *q) +{ + hprt_t hprt; + hfnum_t hfnum; + hci_t *controller = q->endp->dev->controller; + dwc_ctrl_t *dwc2 = DWC2_INST(controller); + dwc2_reg_t *reg = DWC2_REG(controller); + + hfnum.d32 = readl(&reg->host.hfnum); + hprt.d32 = readl(dwc2->hprt0); + + /* + * hfnum.frnum increments when a new SOF is transmitted on + * the USB, and is reset to 0 when it reaches 16'h3FFF + */ + switch (hprt.prtspd) { + case PRTSPD_HIGH: + /* 8 micro-frame per ms for high-speed */ + return hfnum.frnum / 8; + case PRTSPD_FULL: + case PRTSPD_LOW: + default: + /* 1 micro-frame per ms for high-speed */ + return hfnum.frnum / 1; + } +} + +/* create and hook-up an intr queue into device schedule */ +static void * +dwc2_create_intr_queue(endpoint_t *ep, const int reqsize, + const int reqcount, const int reqtiming) +{ + intr_queue_t *q = (intr_queue_t *)xzalloc(sizeof(intr_queue_t)); + + q->data = dma_memalign(4, reqsize); + q->endp = ep; + q->reqsize = reqsize; + q->reqtiming = reqtiming; + + return q; +} + +static void +dwc2_destroy_intr_queue(endpoint_t *ep, void *_q) +{ + intr_queue_t *q = (intr_queue_t *)_q; + + free(q->data); + free(q); +} + +/* + * read one intr-packet from queue, if available. extend the queue for + * new input. Return NULL if nothing new available. + * Recommended use: while (data=poll_intr_queue(q)) process(data); + */ +static u8 * +dwc2_poll_intr_queue(void *_q) +{ + intr_queue_t *q = (intr_queue_t *)_q; + int ret = 0; + u32 timestamp = dwc2_intr_get_timestamp(q); + + /* + * If hfnum.frnum run overflow it will schedule + * an interrupt transfer immediately + */ + if (timestamp - q->timestamp < q->reqtiming) + return NULL; + + q->timestamp = timestamp; + + ret = dwc2_intr(q->endp, q->reqsize, q->data); + + if (ret > 0) + return q->data; + else + return NULL; +} + hci_t *dwc2_init(void *bar) { hci_t *controller = new_controller(); @@ -349,9 +450,9 @@ hci_t *dwc2_init(void *bar) controller->set_address = generic_set_address; controller->finish_device_config = NULL; controller->destroy_device = NULL; - controller->create_intr_queue = NULL; - controller->destroy_intr_queue = NULL; - controller->poll_intr_queue = NULL; + controller->create_intr_queue = dwc2_create_intr_queue; + controller->destroy_intr_queue = dwc2_destroy_intr_queue; + controller->poll_intr_queue = dwc2_poll_intr_queue; controller->reg_base = (uintptr_t)bar; init_device_entry(controller, 0); diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h index 7e6621d..c109042 100644 --- a/payloads/libpayload/drivers/usb/dwc2_private.h +++ b/payloads/libpayload/drivers/usb/dwc2_private.h @@ -24,9 +24,18 @@ typedef struct dwc_ctrl { #define DMA_SIZE (64 * 1024) void *dma_buffer; - uint32_t *hprt0; + u32 *hprt0; + u32 frame; } dwc_ctrl_t; +typedef struct { + u8 *data; + endpoint_t *endp; + int reqsize; + u32 reqtiming; + u32 timestamp; +} intr_queue_t; + #define DWC2_INST(controller) ((dwc_ctrl_t *)((controller)->instance)) #define DWC2_REG(controller) ((dwc2_reg_t *)((controller)->reg_base)) diff --git a/payloads/libpayload/include/usb/dwc2_registers.h b/payloads/libpayload/include/usb/dwc2_registers.h index b6ae2ed..0e46985 100644 --- a/payloads/libpayload/include/usb/dwc2_registers.h +++ b/payloads/libpayload/include/usb/dwc2_registers.h @@ -364,10 +364,10 @@ typedef union { uint32_t d32; /* register bits */ struct { - unsigned nptxfstaddr:16; - unsigned nptxfdep:16; + unsigned txfstaddr:16; + unsigned txfdep:16; }; -} gnptxfsiz_t; +} gtxfsiz_t; /** * This union represents the bit fields of the Core Receive FIFO Size @@ -512,6 +512,23 @@ typedef union { } hcfg_t; /** + * This union represents the bit fields in the Host Frame Number/Frame Time + * Remaining Register + */ +typedef union { + /* raw register data */ + uint32_t d32; + + /* register bits */ + struct { + /** Frame Number */ + unsigned frnum:16; + /** Frame Time Remaining */ + unsigned frrem:16; + }; +} hfnum_t; + +/** * This union represents the bit fields in the Host Port Control and status * Register. */

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New patch to review for coreboot: libpayload: arm(64): add read8/16/32 and write8/16/32
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10773 -gerrit commit 06dd3b0255be0ffdfc575bd925b905b7416d4550 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 25 16:19:49 2015 -0700 libpayload: arm(64): add read8/16/32 and write8/16/32 This applys the same change made by https://chromium-review.googlesource.com/261692 to libpayload. BUG=none BRANCH=tot TEST=built for veyron_jerry, rush_ryu, samus Change-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030 Original-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282541 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/include/arm/arch/io.h | 47 +++++++++++++++++++++++++++++ payloads/libpayload/include/arm64/arch/io.h | 47 +++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/payloads/libpayload/include/arm/arch/io.h b/payloads/libpayload/include/arm/arch/io.h index df3a0d5..2743852 100644 --- a/payloads/libpayload/include/arm/arch/io.h +++ b/payloads/libpayload/include/arm/arch/io.h @@ -34,6 +34,14 @@ #include <stdint.h> #include <arch/cache.h> +/* + * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 + * instead for future development. + * + * TODO: make the existing code use read8/16/32 and write8/16/32 then remove + * readb/w/l and writeb/w/l. + */ + static inline uint8_t readb(volatile const void *_a) { dmb(); @@ -73,4 +81,43 @@ static inline void writel(uint32_t _v, volatile void *_a) dmb(); } +static inline uint8_t read8(const void *addr) +{ + dmb(); + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(const void *addr) +{ + dmb(); + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(const void *addr) +{ + dmb(); + return *(volatile uint32_t *)addr; +} + +static inline void write8(void *addr, uint8_t val) +{ + dmb(); + *(volatile uint8_t *)addr = val; + dmb(); +} + +static inline void write16(void *addr, uint16_t val) +{ + dmb(); + *(volatile uint16_t *)addr = val; + dmb(); +} + +static inline void write32(void *addr, uint32_t val) +{ + dmb(); + *(volatile uint32_t *)addr = val; + dmb(); +} + #endif diff --git a/payloads/libpayload/include/arm64/arch/io.h b/payloads/libpayload/include/arm64/arch/io.h index f8be1ae..c177598 100644 --- a/payloads/libpayload/include/arm64/arch/io.h +++ b/payloads/libpayload/include/arm64/arch/io.h @@ -35,6 +35,14 @@ #include <arch/cache.h> #include <arch/lib_helpers.h> +/* + * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 + * instead for future development. + * + * TODO: make the existing code use read8/16/32 and write8/16/32 then remove + * readb/w/l and writeb/w/l. + */ + static inline uint8_t readb(volatile const void *_a) { dmb(); @@ -74,4 +82,43 @@ static inline void writel(uint32_t _v, volatile void *_a) dmb(); } +static inline uint8_t read8(const void *addr) +{ + dmb(); + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(const void *addr) +{ + dmb(); + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(const void *addr) +{ + dmb(); + return *(volatile uint32_t *)addr; +} + +static inline void write8(void *addr, uint8_t val) +{ + dmb(); + *(volatile uint8_t *)addr = val; + dmb(); +} + +static inline void write16(void *addr, uint16_t val) +{ + dmb(); + *(volatile uint16_t *)addr = val; + dmb(); +} + +static inline void write32(void *addr, uint32_t val) +{ + dmb(); + *(volatile uint32_t *)addr = val; + dmb(); +} + #endif

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New patch to review for coreboot: rockchip: rk3288: correct ddr 300MHz clock setting
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10772 -gerrit commit 28e0f3caae412039ba0a33d2c295886bd65ea9c5 Author: huang lin <hl(a)rock-chips.com> Date: Tue Jun 30 10:01:14 2015 +0800 rockchip: rk3288: correct ddr 300MHz clock setting CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz setting can't meet this request, so modify it BRANCH=None BUG=None TEST=Set ddr frequency to 300MHz and boot from mickey Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5 Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282445 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index b823e01..878c194 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -360,7 +360,7 @@ void rkclk_configure_ddr(unsigned int hz) switch (hz) { case 300*MHz: - dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1}; + dpll_cfg = (struct pll_div){.nf = 50, .nr = 2, .no = 2}; break; case 533*MHz: /* actually 533.3P MHz */ dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2};

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New patch to review for coreboot: veyron_danger: EDP changes for v2
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10771 -gerrit commit 2b0eae79891b03612202ed07922b65d79000e565 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jun 1 15:17:24 2015 -0700 veyron_danger: EDP changes for v2 EDP-related hardware modifications for v2: - BL_EN moved from GPIO7_A3 to GPIO7_A2 - EDP_HPD added to GPIO7_B3 BUG=none BRANCH=none TEST=built and booted Danger v2 with EDP panel attached, saw dev mode screen come up Change-Id: I47383610082b371a612aced656e56f1bd1cfa098 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b Original-Reviewed-on: https://chromium-review.googlesource.com/280855 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_danger/mainboard.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/veyron_danger/mainboard.c b/src/mainboard/google/veyron_danger/mainboard.c index 7b06742..f105d36 100644 --- a/src/mainboard/google/veyron_danger/mainboard.c +++ b/src/mainboard/google/veyron_danger/mainboard.c @@ -99,10 +99,32 @@ static void configure_vop(void) * To minimize display corruption, turn off LCDC_BL before * powering on the backlight. */ - gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */ - gpio_output(GPIO_LCDC_BL, 0); + switch (board_id()) { + case 0: + gpio_output(GPIO(7, A, 3), 1); + break; + default: + gpio_output(GPIO(7, A, 2), 1); + break; + } + gpio_output(GPIO_LCDC_BL, 0); rk808_configure_switch(1, 1); /* VCC33_LCD */ + + /* EDP_HPD setup */ + switch (board_id()) { + case 0: + /* not present */ + break; + default: + /* Unlike other Veyrons, Danger has external pull resistors on + * EDP_HPD. Default for GPIO(7, B, 3) is pull-down, set to + * float. + */ + gpio_input(GPIO(7, B, 3)); + write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG); + break; + } } static void configure_hdmi(void)

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New patch to review for coreboot: libpayload: udc: dwc2: support force_shutdown() routine
by Patrick Georgi 03 Jul '15

03 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10770 -gerrit commit b1cd9d2dfae4cfd1457e49f664f601a698f18df6 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Tue Jun 23 17:42:34 2015 +0800 libpayload: udc: dwc2: support force_shutdown() routine Add force_shutdown() routine for dwc2 udc driver to support disconnect and reconnect case when fastboot receiving data. BUG=chrome-os-partner:41687 BRANCH=None TEST=None Change-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9 Original-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281130 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Commit-Queue: Jeffy Chen <jeffy.chen(a)rock-chips.com> --- payloads/libpayload/drivers/udc/dwc2.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index 99ee0b3..ab36844 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -675,12 +675,29 @@ static int dwc2_check_irq(struct usbdev_ctrl *this) return 1; } +static void dwc2_force_shutdown(struct usbdev_ctrl *this) +{ + gusbcfg_t gusbcfg; + dwc2_pdata_t *p = DWC2_PDATA(this); + + /* Disconnect */ + dwc2_connect(this, 0); + + /* Back to normal otg mode */ + gusbcfg.d32 = readl(&p->regs->core.gusbcfg); + gusbcfg.forcehstmode = 0; + gusbcfg.forcedevmode = 0; + writel(gusbcfg.d32, &p->regs->core.gusbcfg); + + free(p); + free(this); +} + static void dwc2_shutdown(struct usbdev_ctrl *this) { dwc2_pdata_t *p = DWC2_PDATA(this); int i, j; int is_empty = 0; - gusbcfg_t gusbcfg; while (!is_empty) { is_empty = 1; @@ -691,17 +708,7 @@ static void dwc2_shutdown(struct usbdev_ctrl *this) is_empty = 0; } - /* Disconnect */ - dwc2_connect(this, 0); - - /* Back to normal otg mode */ - gusbcfg.d32 = readl(&p->regs->core.gusbcfg); - gusbcfg.forcehstmode = 0; - gusbcfg.forcedevmode = 0; - writel(gusbcfg.d32, &p->regs->core.gusbcfg); - - free(p); - free(this); + dwc2_force_shutdown(this); } static void dwc2_set_address(struct usbdev_ctrl *this, int address) @@ -910,6 +917,7 @@ struct usbdev_ctrl *dwc2_udc_init(device_descriptor_t *dd) ctrl->poll = dwc2_check_irq; ctrl->add_gadget = udc_add_gadget; ctrl->enqueue_packet = dwc2_enqueue_packet; + ctrl->force_shutdown = dwc2_force_shutdown; ctrl->shutdown = dwc2_shutdown; ctrl->set_address = dwc2_set_address; ctrl->stall = dwc2_stall;

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New patch to review for coreboot: storm: Enable DRIVER_UART since we use CONSOLE_CBMEM_DUMP_TO_UART
by Stefan Reinauer 03 Jul '15

03 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10769 -gerrit commit 77a31d951cf7cba82f63a071900736711c37ccc2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 1 17:51:26 2015 -0700 storm: Enable DRIVER_UART since we use CONSOLE_CBMEM_DUMP_TO_UART This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART. Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/google/storm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 1989640..55cc5ba 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER - select CONSOLE_CBMEM_DUMP_TO_UART select DRIVERS_I2C_WW_RING select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS @@ -35,6 +34,8 @@ config BOARD_SPECIFIC_OPTIONS select VBOOT_DISABLE_DEV_ON_RECOVERY select VIRTUAL_DEV_SWITCH select WIPEOUT_SUPPORTED + select DRIVERS_UART + select CONSOLE_CBMEM_DUMP_TO_UART config BOARD_VARIANT_AP148 bool "pick this to build an image for ap148"

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coreboot-gerrit July 2015