coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: smscsuperio: map interrupt in smscsuperio_enable_serial()
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10807 -gerrit commit 612927b6bdc51b3c1e1ccd90b45587afb088a806 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:07:50 2015 -0500 smscsuperio: map interrupt in smscsuperio_enable_serial() This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the interrupt is unmapped at reset, but for whatever reason the chip is inaccessible in smscsuperio/superio.c::enable_dev() and thus the devicetree.cb IRQ information is not applied in ramstage and then serial console output fails to work for more than the UART FIFO depth in the OS. Change-Id: I00998088975569516f7caeb7f4098b48fe437889 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/superio/smsc/smscsuperio/early_serial.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 3eb9347..0d5d6d0 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -55,6 +55,14 @@ void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + switch (iobase) { + case 0x03f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + break; + case 0x02f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + break; + } pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); }

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Patch set updated for coreboot: util/cbfstool: use _XOPEN_SOURCE=700 to find strdup(3)
by Jonathan A. Kollasch 06 Jul '15

06 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10809 -gerrit commit 952129fecfc05246189aa0422ad42bb65844431c Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:29:00 2015 -0500 util/cbfstool: use _XOPEN_SOURCE=700 to find strdup(3) Change-Id: I974c6c8733356cc8ea4e0505136a34b6055abf0c Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- util/cbfstool/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index dde8c68..976f0c2 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -45,7 +45,7 @@ TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h -TOOLCPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h +TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool

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New patch to review for coreboot: sandybridge: provide monotonic timer function
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10813 -gerrit commit 8bae7b98e88eab956469d2bdc8892f68f0a6afd0 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 20:50:33 2015 +0200 sandybridge: provide monotonic timer function This fixes building the ELOG_GSMI feature by using the TSC as time source for the flash drivers. It's not the most precise clock, but should be good enough for the purpose. Change-Id: I2d416c34268236228300a9e868628c35e22bf40c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/northbridge/intel/sandybridge/udelay.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index b150253..3ac6022 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -53,3 +53,27 @@ void udelay(u32 us) } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); } + +#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__) +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + struct mono_time time; + + tsc_t tsc; + msr_t msr; + u32 fsb = 100, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(0xce); + divisor = (msr.lo >> 8) & 0xff; + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + + tsc = rdtsc(); + + time.microseconds = (long)((((uint64_t)tsc.hi << 32) | tsc.lo) / d); + + *mt = time; +} +#endif

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Patch merged into coreboot/master: util/cbfstool: don't override ntohl(3) and htonl(3) on NetBSD
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 1142197e27a9887b9a7aa284d244dfd2c4fc38cb Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:30:13 2015 -0500 util/cbfstool: don't override ntohl(3) and htonl(3) on NetBSD Change-Id: I9bfc017dee86fe6cbc51de99f46429d53efe7d11 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10810 for details. -gerrit

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Patch merged into coreboot/master: util/xcompile/xcompile: use env(1) to find bash
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit fb6f78e61ebdb264c8d17dc94bf9db97276339ff Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 6 08:22:45 2015 -0500 util/xcompile/xcompile: use env(1) to find bash Not all systems put bash at /bin/bash. Change-Id: Ib58cd2f6cf330b5b2678d55bb929696872fba9c9 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10808 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10808 for details. -gerrit

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Patch merged into coreboot/master: Braswell: Update to end of June.
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit acb9c0b6616f96357c303964678eac05177a078d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 2 11:55:18 2015 -0700 Braswell: Update to end of June. Remove some CamelCase in acpi.c Add FSP PcdDvfsEnable configuration parameter. Add lpc_init and lpc_set_low_power routines. Remove Braswell reference to make code easier to port to another SOC. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10768 for details. -gerrit

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Patch merged into coreboot/master: Braswell: Update the ACPI tables
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 2bc9cee0f70f133bb31a79b92ea4d982d55d048d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jun 30 15:25:44 2015 -0700 Braswell: Update the ACPI tables Build the GNVS pointer and add it to the DSDT. Add the opregion for GOP support. Build the SSDT entry and add it to the RSDP. The arch/x86/boot/acpi.c module adds the HPET entry, remove the acpi_create_intel_hpet routine. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10748 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10748 for details. -gerrit

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Patch set updated for coreboot: Revert "sandy/ivybridge: use LAPIC timer in SMM"
by Patrick Georgi 06 Jul '15

06 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10811 -gerrit commit fc820995a75d463a95995e3b64ef0adbbf4206f8 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 18:18:22 2015 +0200 Revert "sandy/ivybridge: use LAPIC timer in SMM" This reverts commit a3aa8da2acec28670b724b7897ae054592746674. There's still a problem for Chrome OS builds, but we need to fix it in a way that doesn't make everything else explode. Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/cpu/x86/lapic/Makefile.inc | 3 -- src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/udelay.c | 55 ++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index baa8292..3061024 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -3,8 +3,5 @@ ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y) -smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -endif romstage-y += boot_cpu.c ramstage-y += boot_cpu.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 60765f2..cf79459 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S +smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c new file mode 100644 index 0000000..b150253 --- /dev/null +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> + +/** + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 100, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(0xce); + divisor = (msr.lo >> 8) & 0xff; + + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + multiply_to_tsc(&tscd, us, d); + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}

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Patch merged into coreboot/master: libpayload: don't overwrite CFLAGS
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 9b8c738942c79c5c34e09d78bbe000cc8a8dfb46 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:09:30 2015 +0000 libpayload: don't overwrite CFLAGS Makefile already sets it to contain the architecture specific flags, don't drop them, but add to that instead. Change-Id: I147e6480ab2b3c1ee4f4ace511197b4ba94280b8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10804 for details. -gerrit

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Patch merged into coreboot/master: libpayload: architecture mapping is now done in xcompile
by gerrit＠coreboot.org 06 Jul '15

06 Jul '15

the following patch was just integrated into master: commit 21fc58b66080c6d4eea6b17b0c9f21d8b82ca450 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 6 09:07:11 2015 +0000 libpayload: architecture mapping is now done in xcompile This helps the build system find i386 and mips compilers. Change-Id: I17d18019b556190f860d288e66f368f8d29ca24d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10803 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10803 for details. -gerrit

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coreboot-gerrit July 2015