coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: cbfstool: Make sure CBFS data structures are packed gcc style
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit cfa9b99b23702ed35d61c9fcf3ad30ec55280174 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jul 4 11:30:59 2015 -0700 cbfstool: Make sure CBFS data structures are packed gcc style On Windows systems, structs can be packed gcc style or ms style. Make sure we use the same one (gcc style) in our user space tools that we use in coreboot. Change-Id: I7a9ea7368f77fba53206e953b4d5ca219ed4c12e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10794 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10794 for details. -gerrit

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Patch merged into coreboot/master: cbfstool: Fix kv_pair on Windows
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit 19ba110c2d04452553b9e07d910ccf6458be4f9b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jul 4 11:28:03 2015 -0700 cbfstool: Fix kv_pair on Windows On Windows systems the archetype printf defaults to ms_printf instead of gnu_printf. Keep the archetype print for all non- Windows compiles to not break compatibility with other systems out there. Change-Id: Iad8441f4dc814366176646f6a7a5df653fda4c15 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10793 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10793 for details. -gerrit

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Patch set updated for coreboot: x86: Drop -Wa, --divide
by Stefan Reinauer 07 Jul '15

07 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10819 -gerrit commit 664d877deb6b390193fd128ab36d804c17e4ff99 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 00:54:05 2015 +0200 x86: Drop -Wa,--divide Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Makefile.inc | 3 --- src/cpu/amd/car/cache_as_ram.inc | 8 ++++---- src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +- src/cpu/intel/car/cache_as_ram.inc | 8 ++++---- src/cpu/intel/car/cache_as_ram_ht.inc | 4 ++-- src/cpu/intel/haswell/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_2065x/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_206ax/cache_as_ram.inc | 6 +++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++-- src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 2 +- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 4 ++-- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 4 ++-- src/vendorcode/amd/agesa/f10/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f12/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f14/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f15/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 6 +++--- 19 files changed, 44 insertions(+), 47 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 20740a4..f502bbe 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -247,9 +247,6 @@ $(objgenerated)/crt0.S: $$(crt0s) # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 -# Some cache as ram code is doing divisions -romstage-S-ccopts +=-Wa,--divide - endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ############################################################################### diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index ac6ea33..133daac 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -240,15 +240,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 7ddd3af..837352f 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -166,7 +166,7 @@ done_cache_as_ram_main: /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index df6f942..bcb0d4b 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -192,7 +192,7 @@ done_cache_as_ram_main: * copying it back to itself to invalidate the cache */ push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1d8ea8d..f9be6e8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -195,15 +195,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 29d7113..193ad41 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -47,7 +47,7 @@ cache_as_ram: * For hyper-threaded CPUs these are shared. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -296,7 +296,7 @@ no_msr_11e: cld xorl %eax, %eax movl $CACHE_AS_RAM_BASE, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 595b4df..0a070b2 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -60,7 +60,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -116,7 +116,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 62f816a..cfa3b6b 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -57,7 +57,7 @@ wait_for_sipi: post_code(0x22) /* Zero out all fixed range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -121,7 +121,7 @@ clear_var_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index f54c691..2d469ff 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -55,7 +55,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -111,7 +111,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl @@ -298,7 +298,7 @@ before_romstage: cld movl $CONFIG_RAMBASE, %esi movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE / 4, %ecx + movl $HIGH_MEMORY_SAVE >> 2, %ecx rep movsl __acpi_resume_backup_done: diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d7d932e..271b756 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -40,7 +40,7 @@ cache_as_ram: /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -90,7 +90,7 @@ clear_mtrrs: /* Clear the cache memory reagion. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 2e560d9..86c10ce 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -36,7 +36,7 @@ cache_as_ram: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 7c6a67f..583ec58 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -82,7 +82,7 @@ wait_for_sipi: /* Zero out all fixed range and variable range MTRRs. */ movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi + movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx 1: @@ -152,7 +152,7 @@ wait_for_sipi: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index ba90c25..05d4889 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -63,7 +63,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -119,7 +119,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 11f50db..b0f4ee6 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -1380,7 +1380,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1389,7 +1389,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1411,7 +1411,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index f6b0899..147d16e 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1374,7 +1374,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1383,7 +1383,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1405,7 +1405,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index f0a1901..2104c27 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1388,7 +1388,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1397,7 +1397,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1419,7 +1419,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index c88709c..1ccefcf 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -1395,7 +1395,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1404,7 +1404,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1426,7 +1426,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index d6c6278..5118a4c 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1704,7 +1704,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1713,7 +1713,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1735,7 +1735,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 90c8cc6..862c8cb 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1069,7 +1069,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1078,7 +1078,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1100,7 +1100,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax #

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Patch merged into coreboot/master: blobs: move marker
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit 5e4d53e12be94e697f9f3fd6b2cd8ca87ce20c74 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 17:32:17 2015 +0200 blobs: move marker Makes the following changes available: 61d663e blobs: Fix assembler code to allow dropping -Wa,--divide a6c34a6 AMD Steppe Eagle: add PlatformMemoryConfiguration.h 95b8050 AMD FT3b binary PI: Fix Windows 7 graphics driver hang c7c816e AMD Kern: remove PspSecureOs_prod_CZ.sbin Change-Id: Ie8ce8278f72c998b91717658a6fc1d0948c7c50a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10824 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10824 for details. -gerrit

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Patch set updated for coreboot: haswell: Use _timestamp region
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10737 -gerrit commit b594756d4ec169dda318f95e29969e56f4f2f330 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Oct 29 10:48:57 2014 -0700 haswell: Use _timestamp region Use timestamp region instead of storing timestamps in local variables before cbmem is up. BUG=None BRANCH=None TEST=cbmem -t reports correct timestamps on falco and peppy (for both normal boot and suspend/resume). Original-Change-Id: If5883721553090f51c0bfcb5677aad55c54f82b3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226362 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 61dbca0b181335d187d742c4a63472f2f2cc9a1b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ibb98f32f24bac1d3560eb257bf0d9f4310a5828f --- src/cpu/intel/haswell/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 779f1d6..2ed1c61 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select HAS_PRECBMEM_TIMESTAMP_REGION config BOOTBLOCK_CPU_INIT string

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Patch set updated for coreboot: t132: Add timestamp collection support in t132
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10736 -gerrit commit 11ab19be9117eff217011b2c32fffb57fb34a1d4 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Oct 13 14:50:08 2014 -0700 t132: Add timestamp collection support in t132 Add a region TIMESTAMP to store all the timestamps starting from bootblock to end of romstage. At the end of romstage take all the timestamps in TIMESTAMP region and put it into cbmem BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully and cbmem -t prints all timestamps Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223110 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1 --- src/soc/nvidia/tegra132/Kconfig | 1 + src/soc/nvidia/tegra132/bootblock.c | 4 ++++ src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 1 + src/soc/nvidia/tegra132/romstage.c | 5 +++++ src/soc/nvidia/tegra132/verstage.c | 2 ++ 5 files changed, 13 insertions(+) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index a5df92a..ee3b80e 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -15,6 +15,7 @@ config SOC_NVIDIA_TEGRA132 select SMP select ARM64_USE_SECURE_MONITOR select GENERIC_GPIO_LIB + select HAS_PRECBMEM_TIMESTAMP_REGION if SOC_NVIDIA_TEGRA132 diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index b19cf49..29a15d9 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -26,6 +26,7 @@ #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> #include <soc/power.h> +#include <timestamp.h> #define BCT_OFFSET_IN_BIT 0x50 #define ODMDATA_OFFSET_IN_BCT 0x6A8 @@ -57,6 +58,9 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void) void main(void) { + timestamp_init(0); + timestamp_add_now(TS_START_BOOTBLOCK); + // enable JTAG at the earliest stage enable_jtag(); diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 2fba8ef..0f98fd2 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -36,6 +36,7 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) + TIMESTAMP(0x40018800, 2K) BOOTBLOCK(0x40019000, 22K) VERSTAGE(0x4001e800, 58K) ROMSTAGE(0x4002d000, 76K) diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 6476e06..ae295c0 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -31,6 +31,7 @@ #include <soc/sdram_configs.h> #include <soc/romstage.h> #include <timer.h> +#include <timestamp.h> void __attribute__((weak)) romstage_mainboard_init(void) { @@ -39,6 +40,8 @@ void __attribute__((weak)) romstage_mainboard_init(void) void romstage(void) { + timestamp_add_now(TS_START_ROMSTAGE); + console_init(); exception_init(); @@ -52,6 +55,8 @@ void romstage(void) printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); #endif + timestamp_add_now(TS_AFTER_INITRAM); + /* * Trust Zone needs to be initialized after the DRAM initialization * because carveout registers are programmed during DRAM init. diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c index b70028a..d6eba9a 100644 --- a/src/soc/nvidia/tegra132/verstage.c +++ b/src/soc/nvidia/tegra132/verstage.c @@ -24,6 +24,7 @@ #include <console/console.h> #include <soc/verstage.h> #include <program_loading.h> +#include <timestamp.h> void __attribute__((weak)) verstage_mainboard_init(void) { @@ -33,6 +34,7 @@ void __attribute__((weak)) verstage_mainboard_init(void) static void verstage(void) { console_init(); + timestamp_add_now(TS_START_VBOOT); exception_init(); verstage_mainboard_init();

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Patch set updated for coreboot: broadwell: Use _timestamp region
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10739 -gerrit commit 14186f7ca4c15b8a373e4cff9a83104a7d1e0810 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Oct 29 16:50:35 2014 -0700 broadwell: Use _timestamp region Use timestamp region instead of storing timestamps in local data structures before cbmem is up BUG=None BRANCH=None TEST=Compiles successfully for Auron and Samus. cbmem -t reports correct timestamps on auron(for both normal boot and suspend/resume) Original-Change-Id: Ib70a3632c2034963c819c1bb90a3cdb2d7d9c355 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226420 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit e2ac6132aa874c13cd8e9333b8e1413ce8359852) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I70f608fc50b2cf180554f817c9aaf833257d7d80 --- src/soc/intel/broadwell/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5da8a33..4308343 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select HAVE_HARD_RESET select HAVE_USBDEBUG + select HAS_PRECBMEM_TIMESTAMP_REGION select IOAPIC select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT

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Patch set updated for coreboot: baytrail: Use _timestamp region
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10738 -gerrit commit 35cce1b4f62206103d8022d08bd23dd407d07afd Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Oct 29 17:37:25 2014 -0700 baytrail: Use _timestamp region Use timestamp region instead of storing timestamps in local data structures before cbmem is up. BUG=None BRANCH=None TEST=cbmem -t reports correct timestamps on rambi(for both normal boot and suspend/resume). Original-Change-Id: I4cce22514041edc7808278d45eac4370a2bf0810 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226421 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 58e212498ffc0ac32e8ad60e0e59caf1aa81c8d8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8cc686327c7bacf28aa97f001b4fd6c0f4aeb585 --- src/soc/intel/baytrail/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5754c15..b394a57 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select HAVE_HARD_RESET + select HAS_PRECBMEM_TIMESTAMP_REGION select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES

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Patch set updated for coreboot: rk3288: Use timestamp region for pre-cbmem timestamps
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10740 -gerrit commit b1428290845e1e8f1fc78c4105b539196b631af9 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Nov 3 14:39:11 2014 -0800 rk3288: Use timestamp region for pre-cbmem timestamps BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 --- src/mainboard/google/veyron_brain/romstage.c | 14 +++----------- src/mainboard/google/veyron_danger/romstage.c | 14 +++----------- src/mainboard/google/veyron_jerry/romstage.c | 14 +++----------- src/mainboard/google/veyron_mickey/romstage.c | 14 +++----------- src/mainboard/google/veyron_mighty/romstage.c | 14 +++----------- src/mainboard/google/veyron_minnie/romstage.c | 14 +++----------- src/mainboard/google/veyron_pinky/romstage.c | 14 +++----------- src/mainboard/google/veyron_rialto/romstage.c | 14 +++----------- src/mainboard/google/veyron_romy/romstage.c | 14 +++----------- src/mainboard/google/veyron_speedy/romstage.c | 14 +++----------- src/soc/rockchip/rk3288/Kconfig | 1 + src/soc/rockchip/rk3288/bootblock.c | 3 +++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 + 13 files changed, 35 insertions(+), 110 deletions(-) diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 80d9081..0328e95 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -81,11 +81,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -98,11 +94,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -114,10 +110,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index e509a4a..06eabe0 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -86,11 +86,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -103,11 +99,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -119,10 +115,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index e509a4a..06eabe0 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -86,11 +86,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -103,11 +99,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -119,10 +115,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index b536391..5031ad9d 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -94,11 +94,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -111,11 +107,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -127,10 +123,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3a4712e..1800b16 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -24,6 +24,7 @@ config SOC_ROCKCHIP_RK3288 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 + select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAVE_UART_SPECIAL diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d60c860..4377652 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,9 +26,12 @@ #include <soc/grf.h> #include <soc/timer.h> #include <symbols.h> +#include <timestamp.h> void bootblock_soc_init(void) { + timestamp_init(timestamp_get()); + rkclk_init(); mmu_init(); diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index cd484c8..0b75932 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -41,6 +41,7 @@ SECTIONS OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 41K) TTB_SUBTABLES(0xFF716C00, 1K) PRERAM_CBFS_CACHE(0xFF717000, 1K) + TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) SRAM_END(0xFF718000)

1 0

Patch set updated for coreboot: timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10742 -gerrit commit 4b0a35f3b88f322d4ef5f3097280726b54764552 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 6 09:58:07 2014 -0600 timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS so stop guarding the compilation. BUG=None BRANCH=None TEST=Built Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228190 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392 --- src/arch/x86/boot/acpi.c | 4 ---- src/mainboard/google/cosmos/romstage.c | 15 ++++----------- src/mainboard/google/veyron_brain/romstage.c | 11 +++-------- src/mainboard/google/veyron_danger/romstage.c | 11 +++-------- src/mainboard/google/veyron_jerry/romstage.c | 12 ++++-------- src/mainboard/google/veyron_mickey/romstage.c | 11 +++-------- src/mainboard/google/veyron_mighty/romstage.c | 11 +++-------- src/mainboard/google/veyron_minnie/romstage.c | 12 ++++-------- src/mainboard/google/veyron_pinky/romstage.c | 14 ++++++-------- src/mainboard/google/veyron_rialto/romstage.c | 11 +++-------- src/mainboard/google/veyron_romy/romstage.c | 11 +++-------- src/mainboard/google/veyron_speedy/romstage.c | 12 ++++-------- src/southbridge/intel/bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/i82801gx/bootblock.c | 3 +-- src/southbridge/intel/lynxpoint/bootblock.c | 3 +-- 16 files changed, 44 insertions(+), 103 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index cf33e40..134e437 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -34,9 +34,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> -#if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> -#endif #include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ @@ -1124,9 +1122,7 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_ACPI_WAKE_JUMP); -#endif acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index 0988bee..e5fa67e 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -37,37 +37,30 @@ void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); -#endif console_init(); -#if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); -#endif + sdram_init(); -#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); -#endif + mmu_init(); mmu_config_range(0, 4096, DCACHE_OFF); dcache_mmu_enable(); cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif - -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 0328e95..e9857b8 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -80,9 +80,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -93,13 +91,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,9 +106,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 06eabe0..fb6e631 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,8 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index 06eabe0..5ccbe3e 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 5031ad9d..492c0f0 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -93,9 +93,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -106,13 +104,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -122,9 +120,9 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif + run_ramstage(); } diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index ffdfdb0..9cdacc3 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 4df6bb5..18532df 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -86,9 +86,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 46aa58f..8f6ddbc 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 64c4410..dde1ae9 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -47,9 +47,8 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); /* Enable RCBA */ diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 6727173..8c2133b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc();

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coreboot-gerrit July 2015