coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: marvel/bg4cd: move timestamp init to SoC code
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit 3957ddc41408a85a509b9f0f39b2aafc05c6eb18 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Jul 7 19:25:14 2015 +0200 marvel/bg4cd: move timestamp init to SoC code No need to repeat this in the mainboard code (even if there's only one right now). Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/10825 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10825 for details. -gerrit

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Patch merged into coreboot/master: timestamp: add generic cache region
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit 1936f6cf25bee5a0eb313d6734df7af871757e7c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 3 17:04:21 2015 -0500 timestamp: add generic cache region In order to accommodate tracking timestamps in all the __PRE_RAM__ stages (bootblock, verstage, romstage, etc) of a platform one needs to provide a way to specify a persistent region of SRAM or cache-as-ram to store the timestamps until cbmem comes online. Provide that infrastructure. Based on original patches from chromium.org: Original-Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223348 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224024 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Change-Id: I8779526136e89ae61a6f177ce5c74a6530469ae1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10790 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10790 for details. -gerrit

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Patch merged into coreboot/master: rk3288: Use timestamp region for pre-cbmem timestamps
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit d17a8623a54f40c3a8e0aab35859d8e18e73e4a0 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Nov 3 14:39:11 2014 -0800 rk3288: Use timestamp region for pre-cbmem timestamps BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 Reviewed-on: http://review.coreboot.org/10740 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10740 for details. -gerrit

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Patch merged into coreboot/master: t132: Add timestamp collection support in t132
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit 8e584aed2af173260ea6ed8bbe954a7763357810 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Oct 13 14:50:08 2014 -0700 t132: Add timestamp collection support in t132 Add a region TIMESTAMP to store all the timestamps starting from bootblock to end of romstage. At the end of romstage take all the timestamps in TIMESTAMP region and put it into cbmem BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully and cbmem -t prints all timestamps Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223110 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1 Reviewed-on: http://review.coreboot.org/10736 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10736 for details. -gerrit

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Patch merged into coreboot/master: x86 makefile: Use preprocessed linker files
by gerrit＠coreboot.org 07 Jul '15

07 Jul '15

the following patch was just integrated into master: commit ac630f7070bba6a39d6778ae437cd52085a68bf5 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Jun 30 15:46:49 2015 -0600 x86 makefile: Use preprocessed linker files The top level Makefile runs the $stage-src .ld scripts through the preprocessor and puts them in $(obj). Use the preprocessed .ld files and cat them together into x86 romstage_null.ld. Change-Id: If71240fbf7231df2b1333a1f8e5160cb8694f6ce Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/10743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10743 for details. -gerrit

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Patch set updated for coreboot: t132: Add timestamp collection support in t132
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10736 -gerrit commit b819070a983d4cbaaceb91afae6e1c9787ccb385 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Oct 13 14:50:08 2014 -0700 t132: Add timestamp collection support in t132 Add a region TIMESTAMP to store all the timestamps starting from bootblock to end of romstage. At the end of romstage take all the timestamps in TIMESTAMP region and put it into cbmem BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully and cbmem -t prints all timestamps Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223110 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1 --- src/soc/nvidia/tegra132/Kconfig | 1 + src/soc/nvidia/tegra132/bootblock.c | 4 ++++ src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 1 + src/soc/nvidia/tegra132/romstage.c | 5 +++++ src/soc/nvidia/tegra132/verstage.c | 2 ++ 5 files changed, 13 insertions(+) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index a5df92a..ee3b80e 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -15,6 +15,7 @@ config SOC_NVIDIA_TEGRA132 select SMP select ARM64_USE_SECURE_MONITOR select GENERIC_GPIO_LIB + select HAS_PRECBMEM_TIMESTAMP_REGION if SOC_NVIDIA_TEGRA132 diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index b19cf49..29a15d9 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -26,6 +26,7 @@ #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> #include <soc/power.h> +#include <timestamp.h> #define BCT_OFFSET_IN_BIT 0x50 #define ODMDATA_OFFSET_IN_BCT 0x6A8 @@ -57,6 +58,9 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void) void main(void) { + timestamp_init(0); + timestamp_add_now(TS_START_BOOTBLOCK); + // enable JTAG at the earliest stage enable_jtag(); diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 2fba8ef..0f98fd2 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -36,6 +36,7 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) + TIMESTAMP(0x40018800, 2K) BOOTBLOCK(0x40019000, 22K) VERSTAGE(0x4001e800, 58K) ROMSTAGE(0x4002d000, 76K) diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 6476e06..ae295c0 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -31,6 +31,7 @@ #include <soc/sdram_configs.h> #include <soc/romstage.h> #include <timer.h> +#include <timestamp.h> void __attribute__((weak)) romstage_mainboard_init(void) { @@ -39,6 +40,8 @@ void __attribute__((weak)) romstage_mainboard_init(void) void romstage(void) { + timestamp_add_now(TS_START_ROMSTAGE); + console_init(); exception_init(); @@ -52,6 +55,8 @@ void romstage(void) printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); #endif + timestamp_add_now(TS_AFTER_INITRAM); + /* * Trust Zone needs to be initialized after the DRAM initialization * because carveout registers are programmed during DRAM init. diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c index b70028a..d6eba9a 100644 --- a/src/soc/nvidia/tegra132/verstage.c +++ b/src/soc/nvidia/tegra132/verstage.c @@ -24,6 +24,7 @@ #include <console/console.h> #include <soc/verstage.h> #include <program_loading.h> +#include <timestamp.h> void __attribute__((weak)) verstage_mainboard_init(void) { @@ -33,6 +34,7 @@ void __attribute__((weak)) verstage_mainboard_init(void) static void verstage(void) { console_init(); + timestamp_add_now(TS_START_VBOOT); exception_init(); verstage_mainboard_init();

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Patch set updated for coreboot: marvel/bg4cd: move timestamp init to SoC code
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10825 -gerrit commit c3e6ef616038e896fe86657af9eca5ef645fb663 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Jul 7 19:25:14 2015 +0200 marvel/bg4cd: move timestamp init to SoC code No need to repeat this in the mainboard code (even if there's only one right now). Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/mainboard/google/cosmos/romstage.c | 28 +++++++--------------------- src/soc/marvell/bg4cd/bootblock.c | 2 ++ 2 files changed, 9 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index 0988bee..e10b3ac 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -37,37 +37,23 @@ void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); + mmu_init(); mmu_config_range(0, 4096, DCACHE_OFF); dcache_mmu_enable(); cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif + run_ramstage(); } diff --git a/src/soc/marvell/bg4cd/bootblock.c b/src/soc/marvell/bg4cd/bootblock.c index e7893fe..79b9d3f 100644 --- a/src/soc/marvell/bg4cd/bootblock.c +++ b/src/soc/marvell/bg4cd/bootblock.c @@ -19,10 +19,12 @@ #include <console/console.h> #include <program_loading.h> +#include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> void main(void) { console_init(); + timestamp_init(timestamp_get()); run_romstage(); }

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Patch set updated for coreboot: rk3288: Use timestamp region for pre-cbmem timestamps
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10740 -gerrit commit aadd980dd384ac2ae03a429046fd5cd05d7914d3 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Nov 3 14:39:11 2014 -0800 rk3288: Use timestamp region for pre-cbmem timestamps BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 --- src/mainboard/google/veyron_brain/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_danger/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_jerry/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_mickey/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_mighty/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_minnie/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_pinky/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_rialto/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_romy/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_shark/romstage.c | 25 ++++++------------------ src/mainboard/google/veyron_speedy/romstage.c | 25 ++++++------------------ src/soc/rockchip/rk3288/Kconfig | 1 + src/soc/rockchip/rk3288/bootblock.c | 3 +++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 + 14 files changed, 71 insertions(+), 209 deletions(-) diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 9f7b1a5..f243235 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -79,13 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,13 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 80d9081..e9857b8 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -80,13 +80,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -97,13 +91,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -113,13 +106,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index e509a4a..5ccbe3e 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -85,13 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -102,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -118,13 +111,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 9f7b1a5..f243235 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -79,13 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,13 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index e509a4a..5ccbe3e 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -85,13 +85,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -102,13 +96,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -118,13 +111,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index 68ab661..9cdacc3 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index b536391..3792e62 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -93,13 +93,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -110,13 +104,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -126,13 +119,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 68ab661..9cdacc3 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 9f7b1a5..f243235 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -79,13 +79,7 @@ static void configure_l2ctlr(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +87,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,13 +102,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_shark/romstage.c b/src/mainboard/google/veyron_shark/romstage.c index 68ab661..9cdacc3 100644 --- a/src/mainboard/google/veyron_shark/romstage.c +++ b/src/mainboard/google/veyron_shark/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index 68ab661..9cdacc3 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -86,13 +86,7 @@ static void sdmmc_power_off(void) void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -103,13 +97,12 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -119,13 +112,7 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3a4712e..1800b16 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -24,6 +24,7 @@ config SOC_ROCKCHIP_RK3288 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 + select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAVE_UART_SPECIAL diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d60c860..4377652 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,9 +26,12 @@ #include <soc/grf.h> #include <soc/timer.h> #include <symbols.h> +#include <timestamp.h> void bootblock_soc_init(void) { + timestamp_init(timestamp_get()); + rkclk_init(); mmu_init(); diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index cd484c8..0b75932 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -41,6 +41,7 @@ SECTIONS OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 41K) TTB_SUBTABLES(0xFF716C00, 1K) PRERAM_CBFS_CACHE(0xFF717000, 1K) + TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) SRAM_END(0xFF718000)

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Patch set updated for coreboot: x86 makefile: Use preprocessed linker files
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10743 -gerrit commit d34e3350004c6caa2e0336d53b68c13dc0c9be84 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Jun 30 15:46:49 2015 -0600 x86 makefile: Use preprocessed linker files The top level Makefile runs the $stage-src .ld scripts through the preprocessor and puts them in $(obj). Use the preprocessed .ld files and cat them together into x86 romstage_null.ld. Change-Id: If71240fbf7231df2b1333a1f8e5160cb8694f6ce Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/x86/Makefile.inc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f502bbe..88fb8b4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -101,9 +101,10 @@ ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ endif -$(objgenerated)/bootblock.ld: $(obj)/config.h $$(filter %.ld,$$(bootblock-srcs)) +$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach ldscript,$(^),#include "$(ldscript)"\n)' | $(CC_bootblock) $(PREPROCESS_ONLY) - > $@ + cat $^ >> $@.tmp + mv $@.tmp $@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -220,12 +221,12 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $(obj)/config.h $$(filter %.ld,$$(romstage-srcs)) +$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - printf '$(foreach ldscript,$(^),#include "$(ldscript)"\n)' >> $@.tmp - $(CC_romstage) $(PREPROCESS_ONLY) $@.tmp > $@ + cat $^ >> $@.tmp + mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt @printf " GEN $(subst $(obj)/,,$(@))\n"

1 0

Patch set updated for coreboot: timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
by Patrick Georgi 07 Jul '15

07 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10742 -gerrit commit f2cd189a7a849b00019ac6ede9aff0670211dce4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 6 09:58:07 2014 -0600 timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS so stop guarding the compilation. BUG=None BRANCH=None TEST=Built Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228190 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392 --- src/arch/x86/boot/acpi.c | 4 ---- src/southbridge/intel/bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/i82801gx/bootblock.c | 3 +-- src/southbridge/intel/lynxpoint/bootblock.c | 3 +-- 5 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index cf33e40..134e437 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -34,9 +34,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> -#if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> -#endif #include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ @@ -1124,9 +1122,7 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_ACPI_WAKE_JUMP); -#endif acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 4df6bb5..18532df 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -86,9 +86,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 46aa58f..8f6ddbc 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 64c4410..dde1ae9 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -47,9 +47,8 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); /* Enable RCBA */ diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 6727173..8c2133b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc();

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coreboot-gerrit July 2015